DATASHEET

X5648, X5649
®
(Replaces X25648, X25649)
Data Sheet
March 17, 2005
CPU Supervisor with 64Kbit SPI EEPROM
FEATURES
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock™ protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14-lead SOIC, 8-lead PDIP
FN8136.0
DESCRIPTION
These devices combine three popular functions, Poweron Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions by holding
RESET/RESET active when VCC falls below a minimum
VCC trip point. RESET/RESET remains asserted until
VCC returns to proper operating level and stabilizes. Five
industry standard VTRIP thresholds are available,
however, Intersil’s unique circuits allow the threshold to
be reprogrammed to meet custom requirements or to
fine-tune the threshold in applications requiring higher
precision.
BLOCK DIAGRAM
WP
Protect Logic
Data
Register
SO
Status
Register
Command
Decode &
Control
Logic
SCK
CS
16Kbits
16Kbits
32Kbits
EEPROM Array
SI
Reset
Timebase
VCC
+
VTRIP
1
-
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5648 = RESET
X5649 = RESET
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5648, X5649
PIN CONFIGURATION
14-Lead SOIC
8-Lead PDIP
CS
1
SO
2
X5648/49
8
VCC
7
RESET/RESET
NC
1
14
NC
CS
2
13
VCC
CS
3
12
VCC
SO
4
11
RESET/RESET
SCK
X5648/49
WP
3
6
SCK
WP
5
10
VSS
4
5
SI
VSS
6
9
SI
NC
7
8
NC
PIN DESCRIPTION
Pin
(PDIP)
Pin
(SOIC)
Name
Function
1
2, 3
CS
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
2
4
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
5
9
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
10
SCK
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
3
5
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
4
6
VSS
Ground
8
12, 13
VCC
Supply Voltage
7
11
RESET/
RESET
1, 7, 8, 14
NC
2
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is enabled and CS remains either
HIGH or LOW longer than the selectable watchdog time out period. A falling
edge of CS will reset the watchdog timer. RESET/RESET goes active on powerup at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
FN8136.0
March 17, 2005
X5648, X5649
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X5648/X5649 activates a
power-on reset circuit. This circuit goes active at about
1V and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When VCC exceeds the device VTRIP
value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin executing code.
Low Voltage Monitoring
During operation, the X5648/X5649 monitors the VCC
level and asserts RESET/RESET if supply voltage
falls below a preset minimum VTRIP. The
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
VCC returns and exceeds VTRIP for 200ms.
VCC Threshold Reset Procedure
The X5648/X5649 has a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or
for higher precision in the VTRIP value, the
X5648/X5649 threshold may be adjusted.
Figure 1. Set VTRIP Voltage
CS
VP
SCK
VP
SI
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the
VTRIP is reset, the new VTRIP is something less than
1.7V. This procedure must be used to set the voltage
to a lower value.
To reset the VTRIP voltage, apply a voltage between 2.7
and 5.5V to the VCC pin. Tie the CS pin, the WP pin,
and the SCK pin HIGH. RESET/RESET and SO pins
are left unconnected. Then apply the programming voltage VP to the SI pin ONLY and pulse CS LOW then
HIGH. Remove VP and the sequence is complete.
Figure 2. Reset VTRIP Voltage
CS
SCK
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and
the new VTRIP is 4.6V, this procedure directly makes
the change. If the new setting is lower than the current
setting, then it is necessary to reset the trip point
before setting the new value.
VCC
VP
SI
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the Vcc pin and tie the CS pin and the WP
pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to
both SCK and SI and pulse CS LOW then HIGH.
Remove VP and the sequence is complete.
3
FN8136.0
March 17, 2005
X5648, X5649
Figure 3. VTRIP Programming Sequence Flow Chart
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied + Error
Execute
Set VTRIP
Sequence
New VCC Applied =
Old VCC Applied - Error
Apply 5V to VCC
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC - 10mV)
NO
RESET pin
goes active?
YES
Error ≥ Emax
Measured VTRIP Desired VTRIP
Error > Emax
Error < Emax
Emax = Maximum Desired Error
4
DONE
FN8136.0
March 17, 2005
X5648, X5649
Figure 4. Sample VTRIP Reset Circuit
VP
NC
4.7K
NC
VTRIP
Adj.
4.7K
+
RESET
1
8
2
7
X5648/49
3
6
4
5
NC
Program
10K
Reset VTRIP
Test VTRIP
Set VTRIP
10K
SPI SERIAL MEMORY
Write Enable Latch
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.
The device contains a write enable latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid write cycle.
The device utilizes Intersil’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular micro controller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on
the first rising edge of SCK after CS goes LOW. Data is
output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start
it again to resume operations where left off.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is formatted as follows:
7
6
5
4
3
2
1
0
WPEN
FLB
0
0
BL1
BL0
WEL
WIP
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name
Note:
Instruction Format*
Operation
WREN
0000 0110
Set the write enable latch (enable write operations)
SFLB
0000 0000
Set flag bit
WRDI/RFLB
0000 0100
Reset the write enable latch/reset flag bit
RSDR
0000 0101
Read status register
WRSR
0000 0001
Write status register (watchdog, block lock, WPEN & flag bits)
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
*Instructions are shown MSB in left most position. Instructions are transferred MSB first.
5
FN8136.0
March 17, 2005
X5648, X5649
Table 2. Block Protect Matrix
WREN CMD
Status Register
Device Pin
Block
Block
Status Register
WEL
WPEN
WP#
Protected Block
Unprotected Block
WPEN, BL0, BL1
WD0, WD1
0
X
X
Protected
Protected
Protected
1
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
Writable
1
X
1
Protected
Writable
Writable
The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When WEL = 1, the
latch is set HIGH and when WEL = 0 the latch is reset
LOW. The WEL bit is a volatile, read only bit. It can
be set by the WREN instruction and can be reset by
the WRDS instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
Status
Register Bits
BL1
Array Addresses Protected
BL0
X5648/X5649
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress
will not stop this write operation, but the operation disables subsequent write attempts to the status register.
When WP is HIGH, all functions, including nonvolatile
writes to the status register operate normally. Setting
the WPEN bit in the status register to “0” blocks the
WP pin function, allowing writes to the status register
when WP is HIGH or LOW. Setting the WPEN bit to
“1” while the WP pin is LOW activates the programmable ROM mode, thus requiring a change in the WP pin
prior to subsequent status register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
status register. Manufacturing can then load configuration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
0
0
None
0
1
$1800-$1FFF
1
0
$1000-$1FFF
Read Sequence
1
1
$0000-$1FFF
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation
is terminated by taking CS high. Refer to the read
EEPROM array sequence (Figure 1).
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The flag bit is automatically
reset upon power-up.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an in-circuit programmable ROM function (Table 2). WP is LOW and WPEN bit programmed
HIGH disables all status register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog
bits from inadvertent corruption.
In the locked state (programmable ROM Mode) the
WP pin is LOW and the nonvolatile bit WPEN is “1”.
This mode disables nonvolatile writes to the device’s
status register.
6
To read the status register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the
status register are shifted out on the SO line. Refer to
the read status register sequence (Figure 2).
FN8136.0
March 17, 2005
X5648, X5649
Figure 5. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
SCK
Instruction
16 Bit Address
15 14 13
SI
3
2
1
0
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
Write Sequence
OPERATIONAL NOTES
Prior to any attempt to write data into the device, the
Write Enable Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
write operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
The device powers-up in the following state:
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to
the first address of the page and overwrite any data
that may have been previously written.
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation
will not be completed (Figure 4).
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The write enable latch is reset.
– The flag bit is reset.
– Reset signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the write
enable latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
While the write is in progress following a status register or EEPROM sequence, the status register may be
read to check the WIP bit. During this time the WIP bit
will be high.
7
FN8136.0
March 17, 2005
X5648, X5649
Figure 6. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11 12 13 14
SCK
Instruction
SI
Data Out
SO
High Impedance
4
3
2
1
0
MSB
Figure 7. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
SO
8
High Impedance
FN8136.0
March 17, 2005
X5648, X5649
Figure 8. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
10
SCK
Instruction
16 Bit Address
15 14 13
SI
3
Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
SI
7
6
5
4
3
Data Byte 3
2
1
0
7
6
5
4
3
Data Byte N
2
1
6
0
5
4
3
2
1
0
Figure 9. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11 12 13 14 15
SCK
Instruction
SI
SO
Data Byte
4
3
2
1
0
High Impedance
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
9
FN8136.0
March 17, 2005
X5648, X5649
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any Pin with respect to VSS ... -1.0V to +7V
D.C. Output Current ............................................. 5mA
Lead temperature (soldering, 10 seconds) ........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
-40°C
Max.
70°C
+85°C
Voltage Option
Supply Voltage
-2.7 or -2.7A
2.7V to 5.5V
Blank or -4.5A
4.5V-5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
ICC1
VCC write current (active)
5
mA
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
ICC2
VCC read current (active)
0.4
mA
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
ISB
VCC standby current
WDT = OFF
1
µA
CS = VCC, VIN = VSS or VCC,
VCC = 5.5V
ILI
Input leakage current
0.1
10
µA
VIN = VSS to VCC
ILO
Output leakage current
0.1
10
µA
VOUT = VSS to VCC
(1)
Input LOW voltage
-0.5
VCC x 0.3
V
VIH(1)
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output LOW voltage
0.4
V
VOL2
Output LOW voltage
0.4
V
VOL3
Output LOW voltage
0.4
V
VCC ≤ 2V, IOL = 0.5mA
VOH1
Output HIGH voltage
VCC - 0.8
V
VCC > 3.3V, IOH = –1.0mA
VOH2
Output HIGH voltage
VCC - 0.4
V
VOH3
Output HIGH voltage
VCC - 0.2
V
VCC ≤ 2V, IOH = -0.25mA
VOLS
Reset output LOW voltage
V
IOL = 1mA
VIL
0.4
VCC > 3.3V, IOL = 2.1mA
2V < VCC ≤ 3.3V, IOL = 1mA
2V < VCC ≤ 3.3V, IOH = –0.4mA
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
COUT
CIN
(2)
(2)
Test
Max.
Unit
Conditions
Output capacitance (SO, RESET/RESET)
8
pF
VOUT = 0V
Input capacitance (SCK, SI, CS, WP)
6
pF
VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
10
FN8136.0
March 17, 2005
X5648, X5649
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
5V
5V
4.6kΩ
2.06kΩ
Output
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
RESET/RESET
3.03kΩ
30pF
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
2.7-5.5V
Symbol
Parameter
Min.
Max.
Unit
0
2
MHz
fSCK
Clock frequency
tCYC
Cycle time
500
ns
tLEAD
CS lead time
250
ns
tLAG
CS lag time
250
ns
tWH
Clock HIGH time
200
ns
tWL
Clock LOW time
250
ns
tSU
Data setup time
50
ns
tH
Data hold time
50
ns
tRI(3)
tFI(3)
Input rise time
100
ns
Input fall time
100
ns
tCS
tWC
(4)
CS deselect time
500
ns
Write cycle time
10
ms
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
SI
SO
tH
MSB IN
tRI
tFI
LSB IN
High Impedance
11
FN8136.0
March 17, 2005
X5648, X5649
Serial Output Timing
2.7-5.5V
Symbol
Parameter
Min.
Unit
fSCK
Clock frequency
2
MHz
tDIS
Output disable time
250
ns
Output valid from clock low
250
ns
tV
0
Max.
tHO
Output hold time
tRO(3)
tFO(3)
Output rise time
100
ns
Output fall time
100
ns
0
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
SO
SI
tHO
MSB Out
tWL
MSB–1 Out
tDIS
LSB Out
ADDR
LSB IN
Power-Up and Power-Down Timing
VTRIP
VTRIP
VCC
tPURST
0 Volts
tPURST
tR
tF
tRPD
RESET (X5648)
RESET (X5649)
12
FN8136.0
March 17, 2005
X5648, X5649
RESET Output Timing
Symbol
VTRIP
VTH
tPURST
tRPD
(5)
Parameter
Reset trip point voltage, X5648-4.5A, X5648-4.5A
Reset trip point voltage, X5648, X5649
Reset trip point voltage, X5648-2.7A, X5649-2.7A
Reset trip point voltage, X5648-2.7, X5649-2.7
Min.
Typ.
Max.
Unit
4.5
4.25
2.85
2.55
4.63
4.38
2.93
2.63
4.75
4.5
3.0
2.7
V
VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
Power-up reset time out
20
100
VCC detect to reset/output
200
mV
280
ms
500
ns
tF(5)
VCC fall time
100
µs
tR(5)
VCC rise time
100
µs
1
V
VRVALID
Note:
Reset valid VCC
(5) This parameter is periodically sampled and not 100% tested.
VTRIP Set Conditions
tTHD
VCC
VTRIP
tTSU
tVPS
CS
tVPS
tRP
tP
tVPH
tVPH
tVPO
VP
SCK
VP
tVPO
SI
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VTRIP Reset Conditions
VCC*
tRP
tP
tVPS
CS
tVPS
tVP1
tVPH
tVPO
VCC
SCK
VP
tVPO
SI
*VCC > Programmed VTRIP
VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C
Parameter
Description
Min.
Max.
tVPS
SCK VTRIP program voltage setup time
tVPH
SCK VTRIP program voltage hold time
1
µs
VTRIP program pulse width
1
µs
tTSU
VTRIP level setup time
10
µs
tTHD
VTRIP level hold (stable) time
10
ms
tWC
VTRIP write cycle time
tRP
VTRIP program cycle recovery period (between successive programming cycles)
10
ms
tVPO
SCK VTRIP program voltage off time before next cycle
0
ms
Programming voltage
15
tP
VP
VTRAN
1
Unit
µs
10
ms
18
V
VTRIP programed voltage range
1.7
5.0
V
Vta1
Initial VTRIP program voltage accuracy (VCC applied - VTRIP) (programmed at 25°C)
-0.1
+0.4
V
Vta2
Subsequent VTRIP program voltage accuracy [(VCC applied - Vta1) - VTRIP)
(programmed at 25°C)
-25
+25
mV
Vtr
VTRIP program voltage repeatability (successive program operations) (programmed at
25°C)
-25
+25
mV
Vtv
VTRIP program variation after programming (0 - 75°C). (programmed at 25°C.)
-25
+25
mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
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TYPICAL PERFORMANCE
tPURST vs. Temperature
VCC Supply Current vs. Temperature (ISB)
205
18
200
Watchdog Timer On (VCC = 5V)
16
195
14
190
Time (ms)
Isb (µA)
12
Watchdog Timer On (VCC = 5V)
10
8
6
185
180
175
170
165
4
Watchdog Timer Off (VCC = 3V, 5V)
2
160
-40
0
-40
25
Temp (°C)
90
25
Degrees °C
90
VTRIP vs. Temperature (programmed at 25°C)
5.025
VTRIP = 5V
5.000
4.975
Voltage
3.525
VTRIP = 3.5V
3.500
3.475
2.525
VTRIP = 2.5V
2.500
2.475
0
25
Temperature
15
85
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March 17, 2005
X5648, X5649
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
.073 (1.84)
Max.
Typ. 0.010 (0.25)
0.060 (1.52)
0.020 (0.51)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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PACKAGING INFORMATION
14-Lead Plastic, SOIC, Package Code S14
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030"Typical
14 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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Ordering Information
VCC Range
VTRIP
Range
Package
Operating
Temperature Range
Part Number RESET
(Active LOW)
Part Number RESET
(Active HIGH)
4.5-5.5V
4.5.4.75
8 pin PDIP
0-70°C
X5648P-4.5A
X5649P-4.5A
14L SOIC
0-70°C
X5648S14-4.5A
X5649S14-4.5A
-40-85°C
X5648S14I-4.5A
X5649S14I-4.5A
8 pin PDIP
0-70°C
X5648P
X5649P
14L SOIC
0-70°C
X5648S14
X5649S14
-40-85°C
X5648S14I
X5649S14I
4.5-5.5V
4.25.4.5
2.7-5.5V
2.85-3.0
14L SOIC
0-70°C
X5648S14-2.7A
X5649S14-2.7A
2.7-5.5V
2.55-2.7
14L SOIC
0-70°C
X5648S14-2.7
X5649S14-2.7
Part Mark Information
X5648/49 W
X
Blank = 14-Lead SOIC
P = 8 Pin DIP
Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5
AL = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75
I = 5V ±10%, -40°C to +85°C, VTRIP = 4.25-4.5
AM = 5V ±10%, -40°C to +85°C, VTRIP = 4.5-4.75
F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7
AN = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0
G = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.55-2.7
AP = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.85-3.0
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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