DATASHEET

X5083
Data Sheet
November 12, 2015
FN8127.4
CPU Supervisor with 8Kbit SPI EEPROM
Features
This device combines four popular functions, Power-on Reset
Control, Watchdog Timer, Supply Voltage Supervision, and
Block Lock Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
• Low VCC detection and reset assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
Applying power to the device activates the power-on reset
circuit which holds RESET active for a period of time. This
allows the power supply and oscillator to stabilize before the
processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to
restart a timer within a selectable time out interval, the device
activates the RESET signal. The user selects the interval
from three preset values. Once selected, the interval does
not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point. RESET is
asserted until VCC returns to the proper operating level and
stabilizes. Five industry standard VTRIP thresholds are
available, however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or to finetune the threshold for applications requiring higher precision.
Pinouts
ED
RT
O
P
RESET
1
8 UP SCK
S
SI
VCC
R
2
7
X5083E O
VSS
CS/WDI
L
3
6
AB
WP
4 AIL
5
SO
AV
ER
NG
O
L
NO
8 LD SOIC, 8 LD PDIP
1
8
2
7
3 X5083 6
4
5
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lock™ memory
- Block lock first or last page, any 1/4 or lower 1/2 of
EEPROM array
• Built-in inadvertent write protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
- 16 byte page write mode
- 5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
8 LD TSSOP
CS/WDI
SO
WP
VSS
• Selectable time out watchdog timer
VCC
RESET
SCK
SI
• Available packages
- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2005-2006, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5083
Typical Application
2.7-5.0V
VCC
uC
VCC
10K
X5083
RESET
CS
SCK
SI
SO
WP
RESET
SPI
VSS
VSS
Block Diagram
VCC
POR AND LOW
VOLTAGE RESET
GENERATION
+
VTRIP
RESET (X5083)
-
RESET & WATCHDOG
TIMEBASE
X5083
WATCHDOG
TRANSITION
DETECTOR
CS/WDI
SI
SO
SCK
WP
COMMAND
DECODE &
CONTROL
LOGIC
PROTECT LOGIC
WATCHDOG
TIMER
RESET
STATUS
REGISTER
EEPROM
ARRAY
8KBITS
STANDARD VTRIP LEVEL
SUFFIX
4.63V (+/-2.5%)
-4.5A
4.38V (+/-2.5%)
-4.5
2.93V (+/-2.5%)
-2.7A
2.63V (+/-2.5%)
-2.7
See “Ordering Information” on page 3 for
more details
For Custom Settings, call Intersil.
2
FN8127.4
November 12, 2015
X5083
Ordering Information
PART NUMBER RESET (ACTIVE LOW)
(Note 1)
PART
MARKING
VCC RANGE
(V)
VTRIP RANGE
(V)
TEMPERATURE
RANGE (°C)
X5083PIZ-4.5A (No longer available or X5083P ZAM
supported)
X5083S8Z-4.5A
X5083 ZAL
X5083S8IZ-4.5A (Note 2)
X5083 ZAM
X5083S8Z
X5083 Z
X5083S8IZ (Note 2)
X5083 ZI
X5083V8IZ (No longer available,
recommended replacement:
X5083S8IZ)
583 IZ
X5083S8Z-2.7A
X5083 ZAN
X5083S8IZ-2.7A*
X5083 ZAP
X5083S8Z-2.7*
X5083 ZF
X5083S8IZ-2.7*
X5083 ZG
X5083V8IZ-2.7 (No longer available,
recommended replacement:
X5083S8IZ-2.7)
583 GZ
4.5-5.5
4.5-4.75
4.5-5.5
4.25-4.5
2.7-5.5
2.85-3.0
2.7-5.5
2.55-2.7
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
-40 to 85
8 Ld PDIP*
MDP0031
0 to 70
8 Ld SOIC
M8.15E
-40 to 85
8 Ld SOIC
M8.15E
0 to 70
8 Ld SOIC
M8.15E
-40 to 85
8 Ld SOIC
M8.15E
-40 to 85
8 Ld TSSOP
M8.173
0 to 70
8 Ld SOIC
M8.15E
-40 to 85
8 Ld SOIC
M8.15E
0 to 70
8 Ld SOIC
M8.15E
-40 to 85
8 Ld SOIC
M8.15E
-40 to 85
8 Ld TSSOP
M8.173
NOTE:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. *Add "-T1" suffix for tape and reel.
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Description
PIN
(SOIC/
PDIP)
PIN
TSSOP
1
3
2
4
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the
serial clock (SCK) clocks the data out.
5
7
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge
of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.
6
8
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in
the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.
3
5
WP
Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the
memory to protect it against inadvertent changes when WP is HIGH, the device operates normally.
4
6
VSS
Ground
8
2
VCC
Supply Voltage
7
1
NAME
FUNCTION
CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a
nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device,
placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition
on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH
to LOW transition within the watchdog time out period results in RESET going active.
RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the
minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms.
RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable
watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on power-up at
about 1V and remains active for 250ms after the power supply stabilizes.
3
FN8127.4
November 12, 2015
X5083
Principles of Operation
Power-on Reset
Application of power to the X5083 activates a power-on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. RESET
active also blocks communication to the device through the
SPI interface. When VCC exceeds the device VTRIP value for
200ms (nominal) the circuit releases RESET, allowing the
processor to begin executing code. While VCC < VTRIP
communications to the device are inhibited.
Low Voltage Monitoring
During operation, the X5083 monitors the VCC level and
asserts RESET if supply voltage falls below a preset
minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition and terminates any SPI communication in
progress. The RESET signal remains active until the voltage
drops below 1V. It also remains active until VCC returns and
exceeds VTRIP for 200ms.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to the
programming voltage VP. Then send a WREN command,
followed by a write of Data 00h to address 01h. CS going
HIGH on the write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 01h.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the new
VTRIP must be 4.0V, then the VTRIP must be reset. When
VTRIP is reset, the new VTRIP is something less than 1.7V.
This procedure must be used to set the voltage to a lower
value.
To reset the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the Vcc pin and tie the WP pin to the
programming voltage VP. Then send a WREN command,
followed by a write of data 00h to address 03h. CS going
HIGH on the write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 03h.
When VCC falls below VTRIP, any communications in
progress are terminated and communications are inhibited
until VCC exceeds VTRIP for tPURST.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle
the CS/WDI pin periodically to prevent a RESET signal. The
CS/WDI pin must be toggled from HIGH to LOW prior to the
expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits with no action taken by the microprocessor
these bits remain unchanged, even after total power failure.
VCC Threshold Reset Procedure
The X5083 is shipped with a standard VCC threshold (VTRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or if higher precision is
needed in the VTRIP value, the X5083 threshold may be
adjusted. The procedure is described below, and uses the
application of a high voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the new
VTRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
4
FN8127.4
November 12, 2015
X5083
VP = 15-18V
WP
CS
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
SCK
16 Bits
SI
06h
WREN
02h
Write
00h
Data
0001h
Address
FIGURE 1. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE)
VP = 15-18V
WP
CS
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
SCK
16 Bits
SI
06h
WREN
02h
Write
00h
Data
0003h
Address
FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15-18V)
4.7K
VP
Adjust
VTRIP
Adj.
Run
1
2
3
4
8
X5083
RESET
µC
7
6
SCK
5
SI
SO
CS
FIGURE 3. SAMPLE VTRIP RESET CIRCUIT
5
FN8127.4
November 12, 2015
X5083
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
New VCC Applied =
Old VCC Applied + Error
New VCC Applied =
Old VCC Applied - Error
Apply 5V to VCC
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC - 50mV)
NO
RESET pin
goes active?
YES
Error  –Emax
Measured VTRIP Desired VTRIP
Error  Emax
–Emax < Error < Emax
DONE
Emax = Maximum Desired Error
FIGURE 4. VTRIP PROGRAMMING SEQUENCE
6
FN8127.4
November 12, 2015
X5083
SPI Serial Memory
Write Enable Latch
The memory portion of the device is a CMOS serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x 8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.
The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 7). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
Status Register/Block Lock/WDT Byte
The device monitors the bus and asserts RESET output if the
watchdog timer is enabled and there is no bus activity within
the user selectable time out period or the supply voltage falls
below a preset minimum VTRIP.
7
6
5
4
3
2
1
0
0
0
0
WD1
WD0
BL2
BL1
BL0
Block Lock Memory
The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on the
rising edge of SCK. CS must be LOW during the entire
operation.
Intersil’s block lock memory provides a flexible mechanism to
store and lock system ID and parametric information. There
are seven distinct block lock memory areas within the array
which vary in size from one page to as much as half of the
entire array. These areas and associated address ranges are
block locked by writing the appropriate two byte block lock
instruction to the device as described in Table 1 and Figure 9.
Once a block lock instruction has been completed, that block
lock setup is held in the nonvolatile status register until the
next block lock instruction is issued. The sections of the
memory array that are block locked can be read but not
written until block lock is removed or changed.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
TABLE 1. INSTRUCTION SET AND BLOCK LOCK PROTECTION BYTE DEFINITION
INSTRUCTION FORMAT
INSTRUCTION NAME AND OPERATION
0000 0110
WREN: set the write enable latch (write enable operation)
0000 0100
WRDI: reset the write enable latch (write disable operation)
0000 0001
Write status instruction—followed by:
Block lock/WDT byte: (See Figure 1)
000WD1 WD2000 --->no block lock: 00h-00h--->none of the array
000WD1 WD2001 --->block lock Q1: 0000h-00FFh--->lower quadrant (Q1)
000WD1 WD2010 --->block lock Q2: 0100h-01FFh--->Q2
000WD1 WD2011 --->block lock Q3: 0200h-02FFh--->Q3
000WD1 WD2100 --->block lock Q4: 0300h-03FFh--->upper quadrant (Q4)
000WD1 WD2101 --->block lock H1: 0000h-01FFh--->lower half of the array (H1)
000WD1 WD2110 --->block lock P0: 0000h-000Fh--->lower page (P0)
000WD1 WD2111 --->block lock Pn: 03F0h-03FFh--->upper page (PN)
0000 0101
READ STATUS: reads status register & provides write in progress status on SO pin
0000 0010
WRITE: write operation followed by address and data
0000 0011
READ: read operation followed by address
7
FN8127.4
November 12, 2015
X5083
Watchdog Timer
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction. A change to the
Watchdog Timer, either setting a new time out period or
turning it off or on, takes effect, following either the next
command (read or write) or cycling the power to the device.
The recommended procedure for changing the Watch-dog
Timer settings is to do a WREN, followed by a write status
register command. Then execute a soft-ware loop to read
the status register until the MSB of the status byte is zero. A
valid alternative is to do a WREN, followed by a write status
register command. Then wait 10ms and do a read status
command.
TABLE 2. WATCHDOG TIMER DEFINITION
STATUS REGISTER BITS
WD1
WD0
WATCHDOG TIME OUT
(TYPICAL)
0
0
1.4s
0
1
600ms
1
0
200ms
1
1
disabled (factory default)
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter
rolls over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS high. Refer to the read EEPROM array sequence
(Figure 5).
To read the status register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction.
After the RDSR opcode is sent, the contents of the status
register are shifted out on the SO line. Refer to the read status
register sequence (Figure 6).
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the same page and overwrite any data that
may have been previously written.
For a write operation (byte or page write) to be completed,
CS can only be brought HIGH after bit 0 of the last data byte
to be written is clocked in. If it is brought HIGH at any other
time, the write operation will not be completed (Figure 8).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits 5, 6
and 7 must be “0”.
Read Status Operation
If there is not a nonvolatile write in progress, the read status
instruction returns the block lock setting from the status
register which contains the watchdog timer bits WD1, WD0,
and the block lock bits IDL2-IDL0 (Figure 6). The block lock
bits define the block lock condition (Table 1). The watchdog
timer bits set the operation of the watchdog timer (Table 2).
The other bits are reserved and will return ’0’ when read. See
Figure 6.
During an internal nonvolatile write operaiton, the Read
Status Instruction returns a HIGH on SO in the first bit
following the RDSR instruction (the MSB). The remaining
bits in the output status byte are undefined. Repeated Read
Status Instructions return the MSB as a ‘1’ until the
nonvolatile write cycle is complete. When the nonvolatile
write cycle is completed, the RDSR instruction returns a ‘0’
in the MSB position with the remaining bits of the status
register undefined. Subsequent RDSR instructions return
the Status Register Contents. See Figure 10.
RESET Operation
The RESET output is designed to go LOW whenever VCC
has dropped below the minimum trip point and/or the
watchdog timer has reached its programmable time out limit.
The RESET output is an open drain output and requires a
pull up resistor.
Operational Notes
The device powers-up in the following state:
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 7). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If
the user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write operation
will be ignored.
8
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• Reset signal is active for tPURST.
FN8127.4
November 12, 2015
X5083
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
• When VCC is below VTRIP, communications to the device
are inhibited.
CS
0
1
2
3
4
5
6
7
8
20 21 22 23 24 25 26 27 28 29 30
9
SCK
Read Instruction
(1 Byte)
Byte Address (2 Byte)
15 14
SI
SO
3
2
Data Out
1
0
High Impedance
7
6
5
4
3
2
1
0
FIGURE 5. READ OPERATION SEQUENCE
CS
0
1
2
3
4
5
6
...
7
SCK
Read Status
Instruction
...
SI
W
D
1
SO
W
D
0
B
L
2
B
L
1
B
L
0
...
SO = Status Reg When no Nonvolatile
Write Cycle
FIGURE 6. READ STATUS OPERATION SEQUENCE
9
FN8127.4
November 12, 2015
X5083
CS
0
1
2
3
4
5
6
7
SCK
Instruction
(1 Byte)
SI
High Impedance
SO
FIGURE 7. WREN/WRDI SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
SI
3
Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
SI
7
6
5
4
3
Data Byte 3
2
1
0
7
6
5
4
3
Data Byte N
2
1
6
0
5
4
3
2
1
0
FIGURE 8. EEPROM ARRAY WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
6
5
4
SCK
Data Byte
Instruction
SI
SO
High Impedance
3
2
1
0
W W
D D
1 0
B
L
2
B
L
1
B
L
0
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
10
FN8127.4
November 12, 2015
X5083
CS
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
READ STATUS
INSTRUCTION
READ STATUS
INSTRUCTION
SCK
SI
NONVOLATILE WRITE IN PROGRESS
SO
SO MSB HIGH while
in the Nonvolatile write cycle
SO MSB still HIGH indicates
Nonvolatile write cycle still in progress
CS
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
READ STATUS
INSTRUCTION
READ STATUS
INSTRUCTION
SCK
SI
NONVOLATILE
WRITE ENDS
BL0
BL1
BL2
WD1
WD0
4 3 2 1 0
SO
1st detected SO MSB LOW
indicates end of Nonvolatile write cycle
FIGURE 10. READ NONVOLATILE WRITE STATUS
11
FN8127.4
November 12, 2015
X5083
tWC
CS
0
1
2
3
4
5
6
7
SCK
NEXT
INSTRUCTION
SI
Non-volatile
Write
Operation
Wait tWC after a write for new operation,
if not using polling procedure
FIGURE 11. END OF NONVOLATILE WRITE (NO POLLING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
12
FN8127.4
November 12, 2015
X5083
Absolute Maximum Ratings
Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-65°C to 135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to 150°C
Voltage on Any Pin with Respect To Vss . . . . . . . . . . . . . -1.0V to 7V
D.C. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
VCC Range
-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Blank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
(Over the recommended operating conditions unless otherwise specified.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
VCC Write Current (Active)
SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,
SO = Open
5
mA
ICC2
VCC Read Current (Active)
SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,
SO = Open
0.4
mA
ISB1
VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC,
VCC = 5.5V
1
µA
ISB2
VCC Standby Current WDT = ON
CS = VCC, VIN = VSS or VCC,
VCC = 5.5V
50
µA
ISB3
VCC Standby Current WDT = ON
CS = VCC, VIN = VSS or VCC,
VCC = 3.6V
20
µA
ILI
Input Leakage Current
VIN = VSS to VCC
0.1
10
µA
ILO
Output Leakage Current
VOUT = VSS to VCC
0.1
10
µA
VIL (Note 1) Input LOW Voltage
-0.5
VCC x 0.3
V
VIH (Note 1) Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output LOW Voltage
VCC > 3.3V, IOL = 2.1mA
0.4
V
VOL2
Output LOW Voltage
2V < VCC  3.3V, IOL = 1mA
0.4
V
VOL3
Output LOW Voltage
VCC  2V, IOL = 0.5mA
0.4
V
VOH1
Output HIGH Voltage
VCC > 3.3V, IOH = -1.0mA
VCC - 0.8
V
VOH2
Output HIGH Voltage
2V < VCC  3.3V, IOH = -0.4mA
VCC - 0.4
V
VOH3
Output HIGH Voltage
VCC  2V, IOH = -0.25mA
VCC - 0.2
V
VOLRS
Reset Output LOW Voltage
IOL = 1mA
0.4
V
Power-Up Timing
SYMBOL
PARAMETER
MIN
MAX
UNIT
tPUR (Note 2)
Power-up to read operation
1
ms
tPUW (Note 2)
Power-up to write operation
5
ms
MAX
UNIT
CONDITIONS
8
pF
VOUT = 0V
6
pF
VIN = 0V
.
Capacitance TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL
TEST
COUT (Note 2) Output capacitance (SO, RESET, RESET)
CIN (Note 2)
Input capacitance (SCK, SI, CS, WP)
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
13
FN8127.4
November 12, 2015
X5083
Equivalent A.C. Load Circuit at 5V VCC
5V
5V
3.3k
1.64k
SO
OUTPUT
A.C. Test Conditions
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
RESET
1.64k
30pF
100pF
AC Electrical Specifications
(Over recommended operating conditions, unless otherwise specified)
2.7V-5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
0
3.3
MHz
DATA INPUT TIMING
fSCK
Clock frequency
tCYC
Cycle time
300
ns
tLEAD
CS lead time
150
ns
tLAG
CS lag time
150
ns
tWH
Clock HIGH time
130
ns
tWL
Clock LOW time
130
ns
tSU
Data setup time
20
ns
tH
Data hold time
20
ns
tRI (Note 3)
Input rise time
2
µs
tFI (Note 3)
Input fall time
2
µs
tCS
CS deselect time
tWC (Note 4)
Write cycle time
100
ns
10
ms
3.3
MHz
DATA OUTPUT TIMING
fSCK
Clock frequency
tDIS
Output disable time
150
ns
Output valid from clock low
130
ns
tV
0
tHO
Output hold time
0
ns
tRO (Note 3)
Output rise time
50
ns
tFO (Note 3)
Output fall time
50
ns
NOTES:
3. This parameter is periodically sampled and not 100% tested.
4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
14
FN8127.4
November 12, 2015
X5083
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
SO
tWL
tHO
MSB Out
tDIS
MSB–1 Out
LSB Out
ADDR
LSB IN
SI
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
SI
tRI
MSB IN
tFI
LSB IN
High Impedance
SO
Power-Up and Power-Down Timing
VCC
VTRIP
tPURST
tPURST
0 Volts
tR
VTRIP
tF
tRPD
RESET
15
FN8127.4
November 12, 2015
X5083
RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VTRIP
Reset trip point voltage, X5083PT-4.5A (Note 6)
Reset trip point voltage, X5083PT
Reset trip point voltage, X5083PT-2.7A
Reset trip point voltage, X5083PT-2.7
4.5
4.25
2.85
2.55
4.63
4.38
2.93
2.63
4.75
4.5
3.00
2.7
V
tPURST
Power-up reset time out
100
200
280
ms
500
ns
tRPD (Note 5)
VCC detect to reset/output
tF (Note 5)
VCC fall time
0.1
ns
tR (Note 5)
VCC rise time
0.1
ns
1
V
VRVALID
Reset valid VCC
NOTES:
5. This parameter is periodically sampled and not 100% tested.
6. PT = Package/Temperature
CS vs. RESET Timing
CS
tCST
RESET
tWDO
tRST
tWDO
tRST
RESET Output Timing
SYMBOL
MIN
TYP
MAX
UNIT
Watchdog time out period,
WD1 = 1, WD0 = 1(default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
OFF
200
600
1.4
300
800
2
ms
ms
sec
tCST
CS pulse width to reset the watchdog
400
tRST
Reset time out
100
tWDO
PARAMETER
16
ns
200
300
ms
FN8127.4
November 12, 2015
X5083
VTRIP Programming Timing Diagram
VCC
(VTRIP)
VTRIP
tTSU
tTHD
VP
VPE
tVPS
tVPH
tPCS
CS
tVPO
tRP
SCK
SI
06h
WREN
02h
Write
0001h (set)
0003h (reset)
Addr.
00
Data
VTRIP Programming Parameters
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tVPS
VTRIP program enable voltage setup time
1
µs
tVPH
VTRIP program enable voltage hold time
1
µs
tPCS
VTRIP programming CS inactive time
1
µs
tTSU
VTRIP setup time
1
µs
tTHD
VTRIP hold (stable) time
10
ms
tWC
VTRIP write cycle time
tVPO
VTRIP program enable voltage off time (between successive adjustments)
0
µs
tRP
VTRIP program recovery period (between successive adjustments)
10
ms
VP
Programming voltage
15
18
V
VTRIP programmed voltage range
2.0
5.0
V
VTRIP program variation after programming (0-75°C). (programmed at 25°C)
-25
+25
mV
VTRAN
Vtv
10
ms
NOTES:
7. VTRIP programming parameters are periodically sampled and are not 100% tested.
8. For custom VTRIP settings, Contact Factory.
17
FN8127.4
November 12, 2015
X5083
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
November 12, 2015
FN8127.4
CHANGE
Updated Ordering Information table on page 3.
Added Revision History and About Intersil sections.
Updated POD MDP0027 to POD M8.15E.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
18
FN8127.4
November 12, 2015
X5083
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
19
FN8127.4
November 12, 2015
X5083
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
20
FN8127.4
November 12, 2015
X5083
Thin Shrink Small Outline Plastic Packages (TSSOP)
M8.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-

e
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX

8
0o
8
7
8o
Rev. 1 12/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN8127.4
November 12, 2015
Similar pages