DATASHEET

X5163, X5165
Data Sheet
August 13, 2015
FN8128.4
CPU Supervisor with 16Kbit SPI EEPROM
Features
Description
• Selectable watchdog timer
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
• Low VCC detection and reset assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
• Determine watchdog or low voltage reset with a volatile
flag bit
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval, the
device activates the RESET/RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system when
VCC falls below the minimum VCC trip point. RESET/RESET is
asserted until VCC returns to proper operating level and
stabilizes. Five industry standard VTRIP thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom requirements
or to fine-tune the threshold for applications requiring higher
precision.
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 16kbits of EEPROM
• Built-in inadvertent write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock™ protection
- In-circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages: 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
Pinouts
14 Ld TSSOP
X5163, X5165
8 Ld SOIC/PDIP
X5163, X5165
CS/WDI
1
SO
2
WP
3
VSS
4
8
X5163, X5165
1
VCC
7
RESET/RESET
6
SCK
5
SI
CS/WDI
1
14
VCC
SO
2
13
RESET/RESET
NC
3
12
NC
NC
4
11
NC
NC
5
10
NC
WP
6
9
SCK
VSS
7
8
SI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2006, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X5163, X5165
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5163PZ (Note)
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
X5163P Z
X5165PZ (Note)
PART
MARKING
X5165P Z
(No longer available,
recommended
replacement:X5163S8Z)
(No longer available or
supported)
X5163PIZ (Note)
X5165PIZ (Note)
X5163P Z I
VCC RANGE
(V)
4.5-5.5
TEMP
VTRIP RANGE RANGE (°C)
4.25-4.5
X5165P Z I
(No longer available,
recommended
replacement:X5163S8IZ)
(No longer available or
supported)
X5163S8Z* (Note) X5163 Z
X5165S8Z*
(Note)
X5165 Z
PACKAGE
(RoHS
Compliant)
PKG.
DWG. #
0 to 70
8 Ld PDIP**
MDP0031
-40 to 85
8 Ld PDIP**
MDP0031
0 to 70
8 Ld SOIC
MDP0027
-40 to 85
8 Ld SOIC
MDP0027
0 to 70
14 Ld TSSOP
M14.173
0 to 70
8 Ld PDIP**
MDP0031
-40 to 85
8 Ld PDIP**
MDP0031
0 to 70
8 Ld SOIC
MDP0027
-40 to 85
8 Ld SOIC
MDP0027
0 to 70
8 Ld PDIP**
MDP0031
-40 to 85
8 Ld PDIP**
MDP0031
(No longer available or
supported)
X5163S8IZ*
(Note)
X5163 Z I
X5165S8IZ*
(Note)
X5165 Z I
(No longer available or
supported)
X5163V14*
X5163V
X5165V14*
X5165V
(No longer available or
supported)
(No longer available or
supported)
X5163PZ-2.7
(Note)
X5165PZ-2.7
(Note)
X5163P Z F
X5165P Z F
(No longer available,
recommended
replacement:X5163S8Z-2.7)
(No longer available or
supported)
X5163PIZ-2.7
(Note)
X5165PIZ-2.7
(Note)
X5163P Z G
2.55-2.7
X5165P Z G
(No longer available,
recommended
replacement:X5163S8IZ-2.7)
(No longer available or
supported)
X5163S8Z-2.7*
(Note)
X5165S8Z-2.7*
(Note)
X5163 Z F
2.7-5.5
X5165 Z F
(No longer available or
supported)
X5163S8IZ-2.7*
(Note)
X5163 Z G
X5165S8IZ-2.7*
(Note)
X5165 Z G
(No longer available or
supported)
X5163PZ-2.7A
(Note)
X5163P Z AN X5165PZ-2.7A
(Note)
X5163P Z AP X5165PIZ-2.7A
(Note)
2.85-3.0
X5165P Z AP
(No longer available or
supported)
(No longer available,
recommended
replacement:X5163S8IZ-2.7A)
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2.7-5.5
(No longer available or
supported)
(No longer available,
recommended
replacement:X5163S8Z-2.7A)
X5163PIZ-2.7A
(Note)
X5165P Z AN
2
FN8128.4
August 13, 2015
X5163, X5165
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X5163S8Z-2.7A*
(Note)
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
X5163 Z AN
X5165S8Z-2.7A
(Note)
PART
MARKING
X5165 Z AN
VCC RANGE
(V)
2.7-5.5
TEMP
VTRIP RANGE RANGE (°C)
2.85-3.0
PACKAGE
(RoHS
Compliant)
PKG.
DWG. #
0 to 70
8 Ld SOIC
MDP0027
-40 to 85
8 Ld SOIC
MDP0027
0 to 70
8 Ld PDIP**
MDP0031
-40 to 85
8 Ld PDIP**
MDP0031
0 to 70
8 Ld SOIC
MDP0027
-40 to 85
8 Ld SOIC
MDP0027
(No longer available or
supported)
X5163S8IZ-2.7A
(Note)
X5163 Z AP
X5165S8IZ-2.7A
(Note)
X5165 Z AP
(No longer available or
supported)
X5163PZ-4.5A
(Note)
X5163P Z AL X5165PZ-4.5A
(Note)
4.5-5.5
4.5-4.75
(No longer available or
supported)
(No longer available,
recommended
replacement:X5163S8Z-4.5A)
X5163PIZ-4.5A
(Note)
X5165P Z AL
X5163P Z AM X5165PIZ-4.5A
(Note)
X5165P Z AM
(No longer available,
recommended
replacement:X5163S8IZ-4.5A)
(No longer available or
supported)
X5163S8Z-4.5A
(Note)
X5165S8Z-4.5A
(Note)
X5163 Z AL
X5165 Z AL
(No longer available or
supported)
X5163S8IZ-4.5A
(Note)
X5163 Z AM
X5165S8IZ-4.5A
(Note)
X5165 Z AM
(No longer available or
supported)
*Add "T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN8128.4
August 13, 2015
X5163, X5165
Block Diagram
Watchdog Transition
Detector
WP
Watchdog
Timer Reset
Protect Logic
RESET/RESET
Data
Register
SO
Status
Register
Command
Decode &
Control
Logic
SCK
CS/WDI
4K Bits
4K Bits
VCC Threshold
Reset Logic
8K Bits
VCC
+
VTRIP
-
EEPROM Array
SI
Reset &
Watchdog
Timebase
X5163 = RESET
X5165 = RESET
Power-on and
Low Voltage
Reset
Generation
Pin Description
PIN
(SOIC/PDIP)
PIN TSSOP
NAME
FUNCTION
1
1
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any
operation after power-up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH
to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW
transition within the watchdog time out period results in RESET/RESET going active.
2
2
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
3
6
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
4
7
VSS
Ground
5
8
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
6
9
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
7
13
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the Watchdog Timer is
enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time out
period. A falling edge of CS will reset the Watchdog Timer. RESET/RESET goes active on powerup at 1V and remains active for 200ms after the power supply stabilizes.
8
14
VCC
Supply Voltage
3-5,10-12
NC
No internal connections
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FN8128.4
August 13, 2015
X5163, X5165
Principles Of Operation
Power-on Reset
Application of power to the X5163, X5165 activates a Poweron Reset Circuit. This circuit goes active at 1V and pulls the
RESET/RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. When VCC
exceeds the device VTRIP value for 200ms (nominal) the
circuit releases RESET/RESET, allowing the processor to
begin executing code.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS/WDI pin and the WP
pin HIGH. RESET and SO pins are left unconnected. Then
apply the programming voltage VP to both SCK and SI and
pulse CS/WDI LOW then HIGH. Remove VP and the
sequence is complete.
CS
VP
SCK
Low Voltage Monitoring
During operation, the X5163, X5165 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits, or
they may be “locked” by tying the WP pin LOW and setting
the WPEN bit HIGH.
VP
SI
FIGURE 1. SET VTRIP VOLTAGE
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage level. For
example, if the current VTRIP is 4.4V and the VTRIP is reset,
the new VTRIP is something less than 1.7V. This procedure
must be used to set the voltage to a lower value.
To reset the VTRIP voltage, apply a voltage between 2.7 and
5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, AND
THE SCK pin HIGH. RESET and SO pins are left
unconnected. Then apply the programming voltage VP to the
SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP
and the sequence is complete.
VCC Threshold Reset Procedure
The X5163, X5165 has a standard VCC threshold (VTRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or for higher precision in
the VTRIP value, the X5163, X5165 threshold may be
adjusted.
SCK
VCC
VP
SI
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage value. For
example, if the current VTRIP is 4.4V and the new VTRIP is
4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.
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CS
5
FIGURE 2. RESET VTRIP VOLTAGE
FN8128.4
August 13, 2015
X5163, X5165
VTRIP PROGRAMMING
EXECUTE
RESET VTRIP
SEQUENCE
SET VCC = VCC APPLIED =
DESIRED VTRIP
EXECUTE
SET VTRIP
SEQUENCE
NEW VCC APPLIED =
OLD VCC APPLIED + ERROR
NEW VCC APPLIED =
OLD VCC APPLIED - ERROR
EXECUTE
RESET VTRIP
SEQUENCE
APPLY 5V TO VCC
DECREMENT VCC
(VCC = VCC - 50MV)
NO
RESET PIN
GOES ACTIVE?
YES
ERROR > -EMAX
MEASURED VTRIP –
DESIRED VTRIP
ERROR > EMAX
ERROR < EMAX
DONE
EMAX = MAXIMUM DESIRED ERROR
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
VP
X5163, X5165
4.7K
NC
VTRIP
+
ADJ.
NC
1
8
2
7
3
6
4
5
4.7K
RESET
NC
PROGRAM
10K
10K
RESET VTRIP
TEST VTRIP
SET VTRIP
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
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FN8128.4
August 13, 2015
X5163, X5165
SPI Serial Memory
Write Enable Latch
The memory portion of the device is a CMOS Serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x 8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.
The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 7). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
7
6
5
4
3
2
1
0
WPEN
FLB
WD1
WD0
BL1
BL0
WEL
WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
INSTRUCTION FORMAT*
OPERATION
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
SFLB
0000 0000
Set Flag Bit
WRDI/RFLB
0000 0100
Reset the Write Enable Latch/Reset Flag Bit
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register (Watchdog,BlockLock,WPEN & Flag Bits)
READ
0000 0011
Read Data from Memory Array Beginning at Selected Address
WRITE
0000 0010
Write Data to Memory Array Beginning at Selected Address
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD
STATUS REGISTER
DEVICE PIN
BLOCK
BLOCK
STATUS REGISTER
WEL
WPEN
WP#
PROTECTED BLOCK
UNPROTECTED BLOCK
WPEN, BL0, BL1, WD0,
WD1
0
X
X
Protected
Protected
Protected
1
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
Writable
1
X
1
Protected
Writable
Writable
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FN8128.4
August 13, 2015
X5163, X5165
The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL = 1, the latch is set
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
STATUS REGISTER BITS
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.
STATUS
REGISTER BITS
WD1
WD0
WATCHDOG TIME OUT
(TYPICAL)
1
0
200 milliseconds
1
1
disabled
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The Flag bit is automatically reset upon powerup. This flag can be used by the system to determine
whether a reset occurs as a result of a watchdog time out or
power failure.
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
provide an In-Circuit Programmable ROM function (Table
2). WP is LOW and WPEN bit programmed HIGH disables
all Status Register Write Operations.
ARRAY ADDRESSES PROTECTED
BL1
BL0
X516X
0
0
None
0
1
$0600-$07FF
1
0
$0400-$07FF
In Circuit Programmable ROM Mode
1
1
$0000-$07FF
This mechanism protects the block lock and Watchdog bits
from inadvertent corruption.
In the locked state (Programmable ROM Mode) the WP pin
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s Status Register.
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.
STATUS REGISTER BITS
WD1
WD0
WATCHDOG TIME OUT
(TYPICAL)
0
0
1.4 seconds
0
1
600 milliseconds
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the Status Register.
CS
0
1
2
3
4
5
6
7
8
9
15
14
10
20
21
22
23
1
0
24
25
26
7
6
5
27
28
29
30
SCK
INSTRUCTION
SI
16 BIT ADDRESS
13
3
2
DATA OUT
HIGH IMPEDANCE
SO
4
3
2
1
0
MSB
FIGURE 5. READ EEPROM ARRAY SEQUENCE
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FN8128.4
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X5163, X5165
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting the
WPEN bit in the Status Register to “0” blocks the WP pin
function, allowing writes to the Status Register when WP is
HIGH or LOW. Setting the WPEN bit to “1” while the WP pin
is LOW activates the Programmable ROM mode, thus
requiring a change in the WP pin prior to subsequent Status
Register changes. This allows manufacturing to install the
device in a system with WP pin grounded and still be able
to program the Status Register. Manufacturing can then
load Configuration data, manufacturing time and other
parameters into the EEPROM, then set the portion of
memory to be protected by setting the block lock bits, and
finally set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address. After
the READ opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The address
is automatically incremented to the next higher address after
each byte of data is shifted out. When the highest address is
reached, the address counter rolls over to address $0000
allowing the read cycle to be continued indefinitely. The read
operation is terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 5).
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operation will not be completed
(Figure 8).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits 0 and
1 must be “0”.
While the write is in progress following a Status Register or
EEPROM Sequence, the Status Register may be read to
check the WIP bit. During this time the WIP bit will be high.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
To read the Status Register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction. After
the RDSR opcode is sent, the contents of the Status Register
are shifted out on the SO line. Refer to the Read Status
Register Sequence (Figure 6).
• The Write Enable Latch is reset.
Write Sequence
The following circuitry has been included to prevent
inadvertent writes:
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 7). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If the
user continues the Write Operation without taking CS HIGH
after issuing the WREN instruction, the Write Operation will be
ignored.
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• The Flag Bit is reset.
• Reset Signal is active for tPURST.
Data Protection
• A WREN instruction must be issued to set the Write Enable
Latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
FN8128.4
August 13, 2015
X5163, X5165
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11
12
13
14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
4
3
2
1
0
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
15
14
13
20
21
22
23
24
25
26
1
0
7
6
5
27
28
29
30
31
1
0
SCK
INSTRUCTION
16 BIT ADDRESS
SI
3
2
DATA BYTE 1
4
3
2
CS
32
33
34
7
6
5
35
36
37
38
39
40
41
42
1
0
7
6
5
43
44
45
46
47
1
0
SCK
DATA BYTE 2
SI
4
3
2
DATA BYTE 3
4
3
2
DATA BYTE N
6
5
4
3
2
1
0
FIGURE 8. WRITE SEQUENCE
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CS
0
1
2
3
4
5
6
7
8
9
10
11
7
6
5
4
12
13
14
15
SCK
INSTRUCTION
SI
SO
DATA BYTE
3
2
1
0
HIGH IMPEDANCE
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM LOW TO
HIGH
WILL CHANGE
FROM LOW TO
HIGH
MAY CHANGE
FROM HIGH TO
LOW
WILL CHANGE
FROM HIGH TO
LOW
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
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Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . .-65 to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150°C
Voltage on any pin with
respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C
Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Specifications Over operating conditions unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
VCC Write Current (Active)
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO =
Open
5
mA
ICC2
VCC Read Current (Active)
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO =
Open
0.4
mA
ISB1
VCC Standby Current WDT = OFF
CS = VCC, VIN = VSS or VCC, VCC = 5.5V
1
µA
ISB2
VCC Standby Current WDT = ON
CS = VCC, VIN = VSS or VCC, VCC = 5.5V
50
µA
ISB3
VCC Standby Current WDT = ON
CS = VCC, VIN = VSS or VCC, VCC = 3.6V
20
µA
ILI
Input Leakage Current
VIN = VSS to VCC
0.1
10
µA
ILO
Output Leakage Current
VOUT = VSS to VCC
0.1
10
µA
(1)
Input LOW Voltage
-0.5
VCC x 0.3
V
VIH(1)
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output LOW Voltage
VCC > 3.3V, IOL = 2.1mA
0.4
V
VOL2
Output LOW Voltage
2V < VCC  3.3V, IOL = 1mA
0.4
V
VOL3
Output LOW Voltage
VCC  2V, IOL = 0.5mA
0.4
V
VOH1
Output HIGH Voltage
VCC > 3.3V, IOH = –1.0mA
VCC - 0.8
V
VOH2
Output HIGH Voltage
2V < VCC  3.3V, IOH = –0.4mA
VCC - 0.4
V
VOH3
Output HIGH Voltage
VCC  2V, IOH = –0.25mA
VCC - 0.2
V
VOLS
Reset Output LOW Voltage
IOL = 1mA
VIL
0.4
V
Capacitance TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL
COUT
CIN
(2)
(2)
TEST
MAX.
UNIT
CONDITIONS
Output Capacitance (SO, RESET, RESET)
8
pF
VOUT = 0V
Input Capacitance (SCK, SI, CS, WP)
6
pF
VIN = 0V
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
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5V
A.C. Test Conditions
5V
3.3k
1.64k
OUTPUT
RESET/RESET
1.64k
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x0.5
30pF
100pF
FIGURE 10. EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
AC Electrical Specifications
Serial Input Timing (Over operating conditions unless otherwise specified.)
2.7-5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
0
2
MHz
fSCK
Clock Frequency
tCYC
Cycle Time
500
ns
tLEAD
CS Lead Time
250
ns
tLAG
CS Lag Time
250
ns
tWH
Clock HIGH Time
200
ns
tWL
Clock LOW Time
200
ns
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tRI(3)
Input Rise Time
100
ns
tFI(3)
Input Fall Time
100
ns
tCS
CS Deselect Time
tWC(4)
Write Cycle Time
500
ns
10
ms
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
SI
SO
tRI
MSB IN
tFI
LSB IN
HIGH IMPEDANCE
FIGURE 11. SERIAL INPUT TIMING
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AC Electrical Specifications
Serial Output Timing(Over operating conditions unless otherwise specified.)
2.7-5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
0
2
MHz
fSCK
Clock Frequency
tDIS
Output Disable Time
250
ns
Output Valid from Clock Low
200
ns
tV
tHO
0
ns
Output Rise Time
100
ns
(3)
Output Fall Time
100
ns
tRO
tFO
Output Hold Time
(3)
NOTES:
3. This parameter is periodically sampled and not 100% tested.
4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
CS
tCYC
tWH
tLAG
SCK
tV
SO
SI
tHO
MSB OUT
tWL
MSB–1 OUT
tDIS
LSB OUT
ADDR
LSB IN
TABLE 3. SERIAL OUTPUT TIMING
VTRIP
VTRIP
VCC
tPURST
0 Volts
tPURST
tR
tF
tRPD
RESET (X5163)
RESET (X5165)
TABLE 4. POWER-UP AND POWER-DOWN TIMING
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RESET Output Timing
SYMBOL
VTRIP
VTH
PARAMETER
Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A
Reset Trip Point Voltage, X5163, X5165
Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A
Reset Trip Point Voltage, X5163-2.7, X5165-2.7
MIN
TYP
MAX
UNIT
4.5
4.25
2.85
2.55
4.63
4.38
2.92
2.63
4.75
4.5
3.0
2.7
V
VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
tPURST
Power-up Reset Time Out
tRPD(5)
VCC Detect to Reset/Output
20
100
200
mV
280
ms
500
ns
tF(5)
VCC Fall Time
100
µs
tR(5)
VCC Rise Time
100
µs
VRVALID
Reset Valid VCC
1
V
NOTES:
5. This parameter is periodically sampled and not 100% tested.
6. Typical values not tested.
CS/WDI
tCST
RESET
tWDO
tWDO
tRST
tRST
RESET
FIGURE 12. CS/WDI VS. RESET/RESET TIMING
RESET/RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
200
600
1.4
300
800
2
ms
ms
sec
tWDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
tCST
CS Pulse Width to Reset the Watchdog
400
tRST
Reset Time Out
100
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15
ns
200
300
ms
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August 13, 2015
X5163, X5165
tTHD
VCC
VTRIP
tTSU
tVPS
CS
tRP
tP
tVPH
tVPH
tVPS
tVPO
VP
SCK
VP
tVPO
SI
FIGURE 13. VTRIP SET CONDITIONS
tTHD
VTRIP
VCC
tTSU
tVPS
CS
SCK
tVPS
tRP
tP
tVP1
tVPH
tVPO
VCC
VP
tVPO
SI
FIGURE 14. VTRIP RESET CONDITIONS
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VTRIP Programming Specifications: VCC = 1.7-5.5V; Temperature = 0°C to 70°C
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tVPS
SCK VTRIP Program Voltage Setup time
1
µs
tVPH
SCK VTRIP Program Voltage Hold time
1
µs
VTRIP Program Pulse Width
1
µs
tTSU
VTRIP Level Setup time
10
µs
tTHD
VTRIP Level Hold (stable) time
10
ms
tWC
VTRIP Write Cycle Time
tRP
VTRIP Program Cycle Recovery Period (Between successive programming cycles)
10
ms
tVPO
SCK VTRIP Program Voltage Off time before next cycle
0
ms
Programming Voltage
15
18
V
VTRIP Programed Voltage Range
1.7
5.0
V
Vta1
Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25°C.)
-0.1
+0.4
V
Vta2
Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP] (Programmed at 25°C.)
-25
+25
mV
Vtr
VTRIP Program Voltage repeatability (Successive program operations.) (Programmed at 25°C.)
-25
+25
mV
Vtv
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
-25
+25
mV
tP
VP
VTRAN
10
ms
VTRIP programming parameters are periodically sampled and are not 100% tested.
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18
1.9
WATCHDOG TIMER ON (VCC = 5V)
16
1.8
14
RESET (SECONDS)
1.7
ISB (µA)
12
WATCHDOG TIMER ON (VCC = 5V)
10
8
6
4
WATCHDOG TIMER OFF (VCC = 3V, 5V)
2
25
TEMP (°C)
90°C
1.4
1.3
1.2
1
90
1.7
2.4
3.1
4.5
5.2
FIGURE 16. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1)
5.025
0.8
VTRIP = 5V
5.000
0.75
RESET (SECONDS)
4.975
3.525
VTRIP = 3.5V
3.500
3.475
2.525
-40°C
0.7
25°C
0.65
90°C
0.6
0.55
0.5
VTRIP = 2.5V
2.500
0.45
2.475
0
25
1.7
85
2.4
3.1
FIGURE 17. VTRIP vs. Temperature (programmed at 25°C)
200
195
195
RESET (SECONDS)
205
200
190
185
180
175
170
175
170
160
DEGREES °C
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18
90°C
180
160
90
-40°C
185
165
FIGURE 19. tPURST VS. TEMPERATURE
5.2
25°C
190
165
25
4.5
FIGURE 18. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0)
205
-40
3.8
VOLTAGE
TEMPERATURE
TIME (MS)
3.8
VOLTAGE
FIGURE 15. VCC SUPPLY CURRENT VS. TEMPERATURE (ISB)
VOLTAGE
25°C
1.5
1.1
0
-40
-40°C
1.6
1.7
2.4
3.1
3.8
4.5
5.2
VOLTAGE
FIGURE 20. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)
FN8128.4
August 13, 2015
X5163, X5165
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
August 13, 2015
FN8128.4
CHANGE
- Ordering Information Table on page 2.
- Added Revision History beginning with Rev 1.
- Added About Intersil Verbiage.
- Updated POD MDP0027 to latest revision changes are as follow:
Added dimensions (INCHES) to table.
- Updated POD MDP0031 to latest revision changes are as follow:
Added dimensions (INCHES) to table.
- Updated POD M14.173 to most current version changes are as follow:
Updated drawing to remove table and added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8128.4
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X5163, X5165
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
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Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
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Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
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22
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
FN8128.4
August 13, 2015
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