DATASHEET

X5168, X5169
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June 15, 2006
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TERSIL
1-888-IN
X25268, X25169)
FN8130.2
CPU Supervisor with 16Kbit SPI EEPROM
Features
These devices combine three popular functions, Power-on
Reset Control, Supply Voltage Supervision, and Block Lock
Protect Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
• Low VCC Detection and Reset Assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions by holding
RESET/RESET active when VCC falls below a minimum VCC
trip point. RESET/RESET remains asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold in
applications requiring higher precision.
• 16Kbits of EEPROM
• Built-in Inadvertent Write Protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock™ protection
- In circuit programmable ROM mode
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply
Operation
• Available Packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Block Diagram
WP
Protect Logic
Data
Register
SO
Status
Register
Command
Decode &
Control
Logic
SCK
CS
4Kbits
4Kbits
8Kbits
EEPROM Array
SI
Reset
Timebase
VCC
+
VTRIP
1
-
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5168 = RESET
X5169 = RESET
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5168, X5169
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
X5169P-4.5A
PART
MARKING
X5168P-4.5A
X5168P AL
X5168PZ-4.5A
(Note)
X5168P Z AL X5169PZ-4.5A
(Note)
X5169P Z AL
X5168PI-4.5A
X5168P AM
X5169P AM
X5168PIZ-4.5A
(Note)
X5168P Z AM X5169PIZ-4.5A
(Note)
X5169P Z AM
X5168S8-4.5A
X5168 AL
X5169S8-4.5A
X5169 AL
X5168S8Z-4.5A
(Note)
X5168 Z AL
X5169S8Z-4.5A
(Note)
X5169 Z AL
X5168S8I-4.5A*
X5168 AM
X5169PI-4.5A
X5169P AL
VCC RANGE VTRIP RANGE
(V)
(V)
4.5-5.5
4.5-4.75
TEMP
RANGE (°C)
PACKAGE
PKG.
DWG #
0 to 70
8 Ld PDIP
MDP0031
0 to 70
8 Ld PDIP**
(Pb-free)
MDP0031
-40 to 85
8 Ld PDIP
MDP0031
-40 to 85
8 Ld PDIP**
(Pb-free)
MDP0031
0 to 70
8 Ld SOIC
MDP0027
0 to 70
8 Ld SOIC
(Pb-free)
MDP0027
X5169S8I-4.5A
X5169 AM
-40 to 85
8 Ld SOIC
MDP0027
X5168S8IZ-4.5A* X5168 Z AM
(Note)
X5169S8IZ-4.5A
(Note)
X5169 Z AM
-40 to 85
8 Ld SOIC
(Pb-free)
MDP0027
X5168V14-4.5A
X5169V14-4.5A
X5169V AL
0 to 70
14 Ld TSSOP M14.173
0 to 70
14 Ld TSSOP M14.173
(Pb-free)
-40 to 85
14 Ld TSSOP M14.173
-40 to 85
14 Ld TSSOP M14.173
(Pb-free)
X5168V AL
X5168V14Z-4.5A X5168V Z AL X5169V14Z-4.5A X5169V Z AL
(Note)
(Note)
X5168V14I-4.5A
X5168V AM
X5169V14I-4.5A
X5169V AM
X5168V14IZ-4.5A X5168V Z AM X5169V14IZ-4.5A X5169V Z AM
(Note)
(Note)
X5168P
X5168P
X5169P
X5169P
X5168PZ (Note)
X5168P Z
X5169PZ (Note)
X5168PI
X5168P I
X5169PI
4.5-5.5
4.25-4.5
0 to 70
8 Ld PDIP
MDP0031
X5169P Z
0 to 70
8 Ld PDIP**
(Pb-free)
MDP0031
X5169P I
-40 to 85
8 Ld PDIP
MDP0031
-40 to 85
8 Ld PDIP**
(Pb-free)
MDP0031
X5168PIZ (Note) X5168P Z I
X5169PIZ (Note) X5169P Z I
X5168S8*
X5168
X5169S8*
X5169
0 to 70
8 Ld SOIC
MDP0027
X5168S8Z*
(Note)
X5168 Z
X5169S8Z*
(Note)
X5169 Z
0 to 70
8 Ld SOIC
(Pb-free)
MDP0027
X5168S8I*
X5168 I
X5169S8I*
X5169 I
-40 to 85
8 Ld SOIC
MDP0027
X5168S8IZ*
(Note)
X5168 Z I
X5169S8IZ*
(Note)
X5169 Z I
-40 to 85
8 Ld SOIC
(Pb-free)
MDP0027
X5168V14*
X5168V
X5169V14*
X5169V
0 to 70
14 Ld TSSOP M14.173
X5168V14Z*
(Note)
X5168V Z
X5169V14Z*
(Note)
X5169V Z
0 to 70
14 Ld TSSOP M14.173
(Pb-free)
X5168V14I*
X5168V I
X5169V14I*
X5169V I
-40 to 85
14 Ld TSSOP M14.173
X5168V14IZ*
(Note)
X5168V Z I
X5169V14IZ*
(Note)
X5169V Z I
-40 to 85
14 Ld TSSOP M14.173
(Pb-free)
X5169P-2.7A
X5169P AN
X5168P-2.7A
X5168P AN
X5168PZ-2.7A
(Note)
X5168P Z AN X5169PZ-2.7A
(Note)
X5169P Z AN
X5168PI-2.7A
X5168P AP
X5169P AP
X5168PIZ-2.7A
(Note)
X5168P Z AP X5169PIZ-2.7A
(Note)
X5169P Z AP
X5168S8-2.7A*
X5168 AN
X5169PI-2.7A
2.7-5.5
2.85-3.0
0 to 70
8 Ld PDIP
MDP0031
0 to 70
8 Ld PDIP**
(Pb-free)
MDP0031
-40 to 85
8 Ld PDIP
MDP0031
-40 to 85
8 Ld PDIP**
(Pb-free)
MDP0031
X5169S8-2.7A
X5169 AN
0 to 70
8 Ld SOIC
MDP0027
X5168S8Z-2.7A* X5168 Z AN
(Note)
X5169S8Z-2.7A
(Note)
X5169 Z AN
0 to 70
8 Ld SOIC
(Pb-free)
MDP0027
X5168S8I-2.7A*
X5168 AP
X5169S8I-2.7A
X5169 AP
-40 to 85
8 Ld SOIC
MDP0027
X5168S8IZ-2.7A
(Note)
X5168 Z AP
X5169S8IZ-2.7A
(Note)
X5169 Z AP
-40 to 85
8 Ld SOIC
(Pb-free)
MDP0027
2
FN8130.2
June 15, 2006
X5168, X5169
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X5168V14-2.7A
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
X5168V AN
X5169V14-2.7A
PART
MARKING
X5168V AN
VCC RANGE VTRIP RANGE
(V)
(V)
2.7-5.5
2.85-3.0
X5168V14Z-2.7A X5168V Z AN X5169V14Z-2.7A X5169V Z AN
(Note)
(Note)
X5168V14I-2.7A
X5168V AP
X5169V14I-2.7A
X5169V AP
X5168V14IZ-2.7A X5168V Z AP X5169V14IZ-2.7A X5169V Z AP
(Note)
(Note)
2.55-2.7
PACKAGE
PKG.
DWG #
0 to 70
14 Ld TSSOP M14.173
0 to 70
14 Ld TSSOP M14.173
(Pb-free)
-40 to 85
14 Ld TSSOP M14.173
-40 to 85
14 Ld TSSOP M14.173
(Pb-free)
X5168P-2.7
X5168P F
X5169P-2.7
X5169P F
X5168PZ-2.7
(Note)
X5168P Z F
X5169PZ-2.7
(Note)
X5169P Z F
X5168PI-2.7
X5168P G
X5169PI-2.7
X5169P G
X5168PIZ-2.7
(Note)
X5168P Z G
X5169PIZ-2.7
(Note)
X5169P Z G
X5168S8-2.7*
X5168 F
X5169S8-2.7*
X5169 F
X5168S8Z-2.7*
(Note)
X5168 Z F
X5169S8Z-2.7*
(Note)
X5169 Z F
X5168S8I-2.7*
X5168 G
X5169S8I-2.7*
X5169 G
X5168S8IZ-2.7*
(Note)
X5168 Z G
X5169S8IZ-2.7*
(Note)
X5169 Z G
X5168V14-2.7*
X5168V F
X5169V14-2.7*
X5169V F
0 to 70
14 Ld TSSOP M14.173
X5168V14Z-2.7*
(Note)
X5168V Z F
X5169V14Z-2.7*
(Note)
X5169V Z F
0 to 70
14 Ld TSSOP M14.173
(Pb-free)
X5168V14I-2.7*
X5168V G
X5169V14I-2.7*
X5168V G
-40 to 85
14 Ld TSSOP M14.173
-40 to 85
14 Ld TSSOP M14.173
(Pb-free)
X5168V14IZ-2.7* X5168V Z G
(Note)
2.7-5.5
TEMP
RANGE (°C)
0 to 70
-40 to 85
0 to 70
-40 to 85
X5169V14IZ-2.7* X5168V Z G
(Note)
8 Ld PDIP
MDP0031
8 Ld PDIP**
(Pb-free)
MDP0031
8 Ld PDIP
MDP0031
8 Ld PDIP**
(Pb-free)
MDP0031
8 Ld SOIC
MDP0027
8 Ld SOIC
(Pb-free)
MDP0027
8 Ld SOIC
MDP0027
8 Ld SOIC
(Pb-free)
MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "-T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Configuration
14 LD TSSOP
8 LD SOIC/PDIP
CS
1
X5168/X5169 8
VCC
SO
2
7
RESET/RESET
WP
3
6
SCK
VSS
4
5
SI
CS
1
X5168/X5169
14
SO
2
13
RESET/RESET
NC
3
12
NC
NC
4
11
NC
NC
5
10
NC
WP
6
9
SCK
7
8
SI
VSS
3
VCC
FN8130.2
June 15, 2006
X5168, X5169
Pin Description
PIN
(SOIC/PDIP)
PIN TSSOP
NAME
FUNCTION
1
1
CS
Chip Select Input. CS HIGH, deselects the device and the SO output
pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be
in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior
to the start of any operation after power-up, a HIGH to LOW transition on CS is required.
2
2
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
5
8
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
6
9
SCK
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
3
6
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
4
7
VSS
Ground
8
14
VCC
Supply Voltage
7
13
RESET/
RESET
3-5,10-12
NC
4
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on powerup at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
FN8130.2
June 15, 2006
X5168, X5169
Principles of Operation
Power-on Reset
Application of power to the X5168, X5169 activates a poweron reset circuit. This circuit goes active at about 1V and pulls
the RESET/RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscillator.
When VCC exceeds the device VTRIP value for 200ms
(nominal) the circuit releases RESET/RESET, allowing the
processor to begin executing code.
Low Voltage Monitoring
During operation, the X5168, X5169 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
VCC Threshold Reset Procedure
The X5168, X5169 has a standard VCC threshold (VTRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or for higher precision in
the VTRIP value, the X5168, X5169 threshold may be
adjusted.
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage level. For
example, if the current VTRIP is 4.4V and the VTRIP is reset,
the new VTRIP is something less than 1.7V. This procedure
must be used to set the voltage to a lower value.
To reset the VTRIP voltage, apply a voltage between 2.7 and
5.5V to the VCC pin. Tie the CS pin, the WP pin, and the SCK
pin HIGH. RESET/RESET and SO pins are left unconnected.
Then apply the programming voltage VP to the SI pin ONLY
and pulse CS LOW then HIGH. Remove VP and the
sequence is complete.
CS
SCK
VCC
VP
SI
FIGURE 2. RESET VTRIP VOLTAGE
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage value. For
example, if the current VTRIP is 4.4V and the new VTRIP is
4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS pin and the WP pin
HIGH. RESET/RESET and SO pins are left unconnected.
Then apply the programming voltage VP to both SCK and SI
and pulse CS LOW then HIGH. Remove VP and the
sequence is complete.
CS
VP
SCK
VP
SI
FIGURE 1. SET VTRIP VOLTAGE
5
FN8130.2
June 15, 2006
X5168, X5169
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied + Error
Execute
Set VTRIP
Sequence
New VCC Applied =
Old VCC Applied - Error
Apply 5V to VCC
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC - 10mV)
NO
RESET pin
goes active?
YES
Error  Emax
Measured VTRIP Desired VTRIP
Error > Emax
Error = 0
Emax = Maximum Desired Error
DONE
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
VP
NC
4.7K
NC
VTRIP
Adj.
+
4.7K
RESET
1
8
2 X5168/ 7
3 X5169 6
4
5
NC
Program
10K
10K
Reset VTRIP
Test VTRIP
Set VTRIP
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
6
FN8130.2
June 15, 2006
X5168, X5169
SPI Serial Memory
Write Enable Latch
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid write cycle.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Status Register
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
7
6
5
4
3
2
1
0
WPEN
FLB
0
0
BL1
BL0
WEL
WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
INSTRUCTION FORMAT*
WREN
0000 0110
Set the write enable latch (enable write operations)
SFLB
0000 0000
Set flag bit
WRDI/RFLB
0000 0100
Reset the write enable latch/reset flag bit
RDSR
0000 0101
Read status register
WRSR
0000 0001
Write status register (watchdog, block lock, WPEN and flag bits)
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
Note:
OPERATION
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD
STATUS REGISTER
DEVICE PIN
BLOCK
BLOCK
STATUS REGISTER
WEL
WPEN
WP#
PROTECTED BLOCK
UNPROTECTED BLOCK
WPEN, BL0, BL1 WD0,
WD1
0
X
X
Protected
Protected
Protected
1
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
Writable
1
X
1
Protected
Writable
Writable
7
FN8130.2
June 15, 2006
X5168, X5169
WP is LOW and WPEN bit programmed HIGH disables all
status register write operations.
The Write Enable Latch (WEL) bit indicates the status of the
write enable latch. When WEL = 1, the latch is set HIGH and
when WEL = 0 the latch is reset LOW. The WEL bit is a
volatile, read only bit. It can be set by the WREN instruction
and can be reset by the WRDS instruction.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog bits
from inadvertent corruption.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.
STATUS
REGISTER BITS
In the locked state (programmable ROM mode) the WP pin
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s status register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the status register.
When WP is HIGH, all functions, including nonvolatile writes
to the status register operate normally. Setting the WPEN bit
in the status register to “0” blocks the WP pin function,
allowing writes to the status register when WP is HIGH or
LOW. Setting the WPEN bit to “1” while the WP pin is LOW
activates the programmable ROM mode, thus requiring a
change in the WP pin prior to subsequent status register
changes. This allows manufacturing to install the device in a
system with WP pin grounded and still be able to program
the status register. Manufacturing can then load
configuration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to be
protected by setting the block lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes now
require a hardware change.
ARRAY ADDRESSES PROTECTED
BL1
BL0
X5168/X5169
0
0
None
0
1
$0600-$07FF
1
0
$0400-$07FF
1
1
$0000-$07FF
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The flag bit is automatically reset upon
power-up.
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
provide an in-circuit programmable ROM function (Table 2).
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
SCK
Instruction
SI
SO
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
MSB
FIGURE 5. READ EEPROM ARRAY SEQUENCE
8
FN8130.2
June 15, 2006
X5168, X5169
Read Sequence
Operational Notes
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter
rolls over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS high. Refer to the read EEPROM array sequence
(Figure 1).
The device powers-up in the following state:
To read the status register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction.
After the RDSR opcode is sent, the contents of the status
register are shifted out on the SO line. Refer to the read status
register sequence (Figure 2).
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
• Reset signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 3). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If
the user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write operation
will be ignored.
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operation will not be completed
(Figure 4).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0 and
1 must be “0”.
While the write is in progress following a status register or
EEPROM sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.
9
FN8130.2
June 15, 2006
X5168, X5169
CS
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
10
SCK
Instruction
16 Bit Address
15 14 13
SI
3
Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
SI
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
1
0
FIGURE 8. WRITE SEQUENCE
10
FN8130.2
June 15, 2006
X5168, X5169
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11 12 13 14 15
SCK
Instruction
SI
Data Byte
4
3
2
1
0
High Impedance
SO
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
11
FN8130.2
June 15, 2006
X5168, X5169
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to VSS . . . . . . . . . . . . -1.0V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Limits
-2.7 or -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Blank or -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V-5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
DC Electrical Specifications
Over the recommended operating conditions unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
VCC write current (active)
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
5
mA
ICC2
VCC read current (active)
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
0.4
mA
ISB
VCC standby current WDT = OFF
CS = VCC, VIN = VSS or VCC,
VCC = 5.5V
1
µA
ILI
Input leakage current
VIN = VSS to VCC
0.1
10
µA
ILO
Output leakage current
VOUT = VSS to VCC
0.1
10
µA
VIL
(NOTE 1)
Input LOW voltage
-0.5
VCC x 0.3
V
VIH
(NOTE 1)
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output LOW voltage
VCC > 3.3V, IOL = 2.1mA
0.4
V
VOL2
Output LOW voltage
2V < VCC  3.3V, IOL = 1mA
0.4
V
VOL3
Output LOW voltage
VCC  2V, IOL = 0.5mA
0.4
V
VOH1
Output HIGH voltage
VCC > 3.3V, IOH = -1.0mA
VCC - 0.8
V
VOH2
Output HIGH voltage
2V < VCC  3.3V, IOH = -0.4mA
VCC - 0.4
V
VOH3
Output HIGH voltage
VCC 2V, IOH = -0.25mA
VCC - 0.2
V
VOLS
Reset output LOW voltage
IOL = 1mA
Capacitance
V
TA = +25°C, f = 1MHz, VCC = 5V.
SYMBOL
COUT
(NOTE 2)
0.4
TEST
Output capacitance (SO, RESET/RESET)
CIN (NOTE 2) Input capacitance (SCK, SI, CS, WP)
CONDITIONS
MAX.
UNIT
VOUT = 0V
8
pF
VIN = 0V
6
pF
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
12
FN8130.2
June 15, 2006
X5168, X5169
A.C. Test Conditions
Equivalent A.C. Load Circuit at 5V VCC
5V
5V
4.6k
2.06k
Output
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
RESET/RESET
3.03k
30pF
100pF
AC Electrical Specifications
(Over recommended operating conditions, unless otherwise specified.)
2.7-5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
0
2
MHz
SERIAL INPUT TIMING
fSCK
Clock frequency
tCYC
Cycle time
500
ns
tLEAD
CS lead time
250
ns
tLAG
CS lag time
250
ns
tWH
Clock HIGH time
200
ns
tWL
Clock LOW time
200
ns
tSU
Data setup time
50
ns
tH
Data hold time
50
ns
tRI(3)
Input rise time
100
ns
tFI(3)
Input fall time
100
ns
tCS
CS deselect time
tWC(4)
Write cycle time
13
500
ns
10
ms
FN8130.2
June 15, 2006
X5168, X5169
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
SI
SO
tRI
tFI
MSB IN
LSB IN
High Impedance
Serial Output Timing
2.7-5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
0
2
MHz
fSCK
Clock frequency
tDIS
Output disable time
250
ns
Output valid from clock low
200
ns
tV
tHO
Output hold time
0
ns
tRO(3)
Output rise time
100
ns
tFO(3)
Output fall time
100
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
SO
SI
MSB Out
tHO
MSB–1 Out
tWL
tDIS
LSB Out
ADDR
LSB IN
14
FN8130.2
June 15, 2006
X5168, X5169
Power-Up and Power-Down Timing
VCC
VTRIP
VTRIP
tPURST
0 Volts
tPURST
tF
tRPD
tR
RESET (X5168)
RESET (X5169)
RESET Output Timing
SYMBOL
PARAMETER
VTRIP
Reset trip point voltage, X5168-4.5A, X5168-4.5A
Reset trip point voltage, X5168, X5169
Reset trip point voltage, X5168-2.7A, X5169-2.7A
Reset trip point voltage, X5168-2.7, X5169-2.7
VTH
tF
MAX
UNIT
4.5
4.25
2.85
2.55
4.63
4.38
2.93
2.63
4.75
4.5
3.0
2.7
V
20
Power-up reset time out
(5)
100
VCC detect to reset/output
200
mV
280
ms
500
ns
(5)
VCC fall time
100
µs
(5)
VCC rise time
100
µs
1
V
tR
VRVALID
Note:
TYP
VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
tPURST
tRPD
MIN
Reset valid VCC
(5) This parameter is periodically sampled and not 100% tested.
VTRIP Set Conditions
tTHD
VCC
VTRIP
tTSU
tVPS
CS
tVPS
tRP
tP
tVPH
tVPH
tVPO
VP
SCK
VP
tVPO
SI
15
FN8130.2
June 15, 2006
X5168, X5169
VTRIP Reset Conditions
VCC*
tRP
tP
tVPS
CS
tVPS
tVP1
tVPH
tVPO
VCC
SCK
VP
tVPO
SI
*VCC > Programmed VTRIP
VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tVPS
SCK VTRIP program voltage setup time
1
µs
tVPH
SCK VTRIP program voltage hold time
1
µs
VTRIP program pulse width
1
µs
tTSU
VTRIP level setup time
10
µs
tTHD
VTRIP level hold (stable) time
10
ms
tWC
VTRIP write cycle time
tRP
VTRIP program cycle recovery period (between successive programming cycles)
10
ms
tVPO
SCK VTRIP program voltage off time before next cycle
0
ms
Programming voltage
15
18
V
VTRIP programmed voltage range
1.7
5.0
V
Vta1
Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C)
-0.1
+0.4
V
Vta2
Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C)
-25
+25
mV
Vtr
VTRIP program voltage repeatability (successive program operations) (programmed at 25°C)
-25
+25
mV
Vtv
VTRIP Program variation after programming (0-75°C). (programmed at 25°C)
-25
+25
mV
tP
VP
VTRAN
10
ms
VTRIP programming parameters are periodically sampled and are not 100% tested.
16
FN8130.2
June 15, 2006
X5168, X5169
Typical Performance
tPURST vs. Temperature
VCC Supply Current vs. Temperature (ISB)
205
18
Watchdog Timer On (VCC = 5V)
16
200
195
14
Isb (µA)
Time (ms)
190
12
Watchdog Timer On (VCC = 5V)
10
8
6
185
180
175
170
4
165
Watchdog Timer Off (VCC = 3V, 5V)
2
0
-40C
25C
Temp (°C)
160
-40
90C
25
90
Degrees °C
VTRIP vs. Temperature (programmed at 25°C)
5.025
VTRIP = 5V
5.000
4.975
Voltage
3.525
VTRIP = 3.5V
3.500
3.475
2.525
VTRIP = 2.5V
2.500
2.475
0
25
Temperature
17
85
FN8130.2
June 15, 2006
X5168, X5169
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
18
FN8130.2
June 15, 2006
X5168, X5169
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
19
FN8130.2
June 15, 2006
X5168, X5169
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-

e
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX

14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN8130.2
June 15, 2006
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