DATASHEET

X5328, X5329
(Replaces X25328, X25329)
Data Sheet
October 16, 2015
CPU Supervisor with 32Kbit SPI EEPROM
FEATURES
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Long battery life with low power consumption
—<1µA max standby current
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock™ protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
FN8132.2
DESCRIPTION
These devices combine three popular functions, Poweron Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions by holding
RESET/RESET active when VCC falls below a minimum VCC trip point. RESET/RESET remains asserted
until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold in applications requiring higher precision.
BLOCK DIAGRAM
WP
Protect Logic
Data
Register
SO
Status
Register
Command
Decode &
Control
Logic
SCK
CS
8Kbits
8Kbits
16Kbits
EEPROM Array
SI
Reset
Timebase
VCC
+
VTRIP
1
-
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5328 = RESET
X5329 = RESET
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2005, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5328, X5329
Ordering Information
PART NUMBER
PART MARKING
VCC RANGE
(V)
VTRIP
RANGE
4.5-5.5
4.5-4.75
TEMP
PACKAGE
RANGE (°C) (RoHS Compliant)
RESET ACTIVE LOW
X5328PZ-4.5A (Note) (No longer available, recommended
replacement: X5328S8Z-4.5A)
X5328P Z AL
0 to 70
8 Ld PDIP
X5328PIZ-4.5A (Note) (No longer available, recommended
replacement: X5328S8IZ-4.5A)
X5328P Z AM
-40 to 85
8 Ld PDIP
X5328S8Z-4.5A (Note)
X5328 Z AL
0 to 70
8 Ld SOIC
X5328S8IZ-4.5A (Note)
X5328 Z AM
-40 to 85
8 Ld SOIC
X5328V14Z-4.5A (Note)
X5328V Z AL
0 to 70
14 Ld TSSOP
X5328PZ (Note) (No longer available, recommended
replacement: X5328S8Z)
X5328P Z
0 to 70
8 Ld PDIP
X5328PIZ (Note) (No longer available, recommended
replacement: X5328S8IZ)
X5328P Z I
-40 to 85
8 Ld PDIP
X5328S8Z* (Note)
X5328 Z
0 to 70
8 Ld SOIC
X5328S8IZ* (Note)
X5328 Z I
-40 to 85
8 Ld SOIC
X5328PZ-2.7A (Note) (No longer available, recommended
replacement: X5328S8Z-2.7A)
X5328P Z AN
0 to 70
8 Ld PDIP
X5328PIZ-2.7A (Note) (No longer available, recommended
replacement: X5328S8IZ-2.7A)
X5328P Z AP
-40 to 85
8 Ld PDIP
X5328S8Z-2.7A (Note)
X5328 Z AN
0 to 70
8 Ld SOIC
X5328S8IZ-2.7A (Note)
X5328 Z AP
-40 to 85
8 Ld SOIC
X5328PZ-2.7 (Note) (No longer available, recommended
replacement: X5328S8Z-2.7)
X5328P Z F
0 to 70
8 Ld PDIP
X5328PIZ-2.7 (Note) (No longer available, recommended
replacement: X5328S8IZ-2.7)
X5328P Z G
-40 to 85
8 Ld PDIP
X5328S8Z-2.7* (Note)
X5328 Z F
0 to 70
8 Ld SOIC
X5328S8IZ-2.7* (Note)
X5328 Z G
-40 to 85
8 Ld SOIC
0 to 70
8 Ld SOIC
8 Ld SOIC
4.5-5.5
2.7-5.5
2.7-5.5
4.25-4.5
2.85-3.0
2.55-2.7
RESET ACTIVE HIGH
X5329S8Z-4.5A (Note)
X5329 Z AL
4.5-5.5
X5329S8IZ-4.5A (Note)
X5329 Z AM
-40 to 85
X5329V14Z-4.5A (Note)
X5329V Z AL
0 to 70
14 Ld TSSOP
X5329S8Z* (Note)
X5329 Z
0 to 70
8 Ld SOIC
X5329S8IZ* (Note)
X5329 Z I
-40 to 85
8 Ld SOIC
X5329S8Z-2.7A (Note)
X5329 Z AN
0 to 70
8 Ld SOIC
-40 to 85
8 Ld SOIC
0 to 70
8 Ld SOIC
-40 to 85
8 Ld SOIC
4.5-5.5
2.7-5.5
4.5-4.75
4.25-4.5
2.85-3.0
X5329S8IZ-2.7A (Note) (No longer available, recommended X5329 Z AP
replacement: X5329S8Z-2.7A)
X5329S8Z-2.7* (Note)
X5329 Z F
X5329S8IZ-2.7* (Note) (No longer available, recommended X5329 Z G
replacement: X5329S8Z-2.7)
2.7-5.5
2.55-2.7
*Add “T1” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8132.2
October 16, 2015
X5328, X5329
PIN DESCRIPTION
Pin
(SOIC/PDIP)
Pin TSSOP
Name
Function
1
1
CS
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a
high impedance state. Unless a nonvolatile write cycle is underway, the device will
be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
2
2
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
5
8
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
9
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
3
6
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
4
7
VSS
Ground
8
14
VCC
Supply Voltage
7
13
RESET/
RESET
3-5,10-12
NC
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active on power-up at about 1V and remains active for 200ms after the
power supply stabilizes.
No internal connections
PIN CONFIGURATION
14 Ld TSSOP
CS
8 Ld SOIC/PDIP
CS
1
14
1
SO
2
13
RESET/RESET
NC
3
12
NC
NC
4 X5328/29 11
NC
NC
5
10
NC
WP
6
9
SCK
VSS
7
8
SI
SO
2
WP
3
VCC
4
8
X5328/29
3
VCC
7
RESET/RESET
6
SCK
5
SI
VCC
FN8132.2
October 16, 2015
X5328, X5329
PRINCIPLES OF OPERATION
Figure 1. Set VTRIP Voltage
Power-On Reset
Application of power to the X5328/X5329 activates a
Power-on Reset Circuit. This circuit goes active at
about 1V and pulls the RESET/RESET pin active. This
signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device
VTRIP value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin executing code.
CS
VP
SCK
VP
SI
Resetting the VTRIP Voltage
Low Voltage Monitoring
During operation, the X5328/X5329 monitors the VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
VCC Threshold Reset Procedure
The X5328/X5329 has a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or
for higher precision in the VTRIP value, the
X5328/X5329 threshold may be adjusted.
This procedure sets the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the
VTRIP is reset, the new VTRIP is something less than
1.7V. This procedure must be used to set the voltage
to a lower value.
To reset the VTRIP voltage, apply a voltage between
2.7 and 5.5V to the VCC pin. Tie the CS pin, the WP
pin, and the SCK pin HIGH. RESET/RESET and SO
pins are left unconnected. Then apply the programming voltage VP to the SI pin ONLY and pulse CS
LOW then HIGH. Remove VP and the sequence is
complete.
Figure 2. Reset VTRIP Voltage
CS
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and
the new VTRIP is 4.6V, this procedure directly makes
the change. If the new setting is lower than the current
setting, then it is necessary to reset the trip point
before setting the new value.
SCK
VCC
VP
SI
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS pin and the WP
pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to
both SCK and SI and pulse CS LOW then HIGH.
Remove VP and the sequence is complete.
4
FN8132.2
October 16, 2015
X5328, X5329
Figure 3. VTRIP Programming Sequence Flow Chart
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied + Error
Execute
Set VTRIP
Sequence
New VCC Applied =
Old VCC Applied - Error
Apply 5V to VCC
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC - 10mV)
NO
RESET pin
goes active?
YES
Error  Emax
Measured VTRIP Desired VTRIP
Error > Emax
Error < Emax
Emax = Maximum Desired Error
DONE
Figure 4. Sample VTRIP Reset Circuit
VP
NC
4.7K
NC
VTRIP
Adj.
+
4.7K
RESET
1
8
2
7
X5328/29
3
6
4
5
NC
Program
10K
5
10K
Reset VTRIP
Test VTRIP
Set VTRIP
FN8132.2
October 16, 2015
X5328, X5329
SPI SERIAL MEMORY
Write Enable Latch
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
The device utilizes Intersil’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any
time, even during a Write Cycle. The Status Register is
formatted as follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
7
6
5
4
3
2
1
0
WPEN
FLB
1*
1*
BL1
BL0
WEL
WIP
*Bits (5,4) should be written as ‘1’ only.
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name
Instruction Format*
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
SFLB
0000 0000
Set Flag Bit
WRDI/RFLB
0000 0100
Reset the Write Enable Latch/Reset Flag Bit
RSDR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register (Block Lock, WPEN & Flag Bits)
READ
0000 0011
Read Data from Memory Array Beginning at Selected Address
WRITE
0000 0010
Write Data to Memory Array Beginning at Selected Address
Note:
Operation
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD
Status Register
Device Pin
Block
Block
Status Register
WEL
WPEN
WP#
Protected Block
Unprotected Block
WPEN, BL0, BL1,
WD0, WD1
0
X
X
Protected
Protected
Protected
1
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
Writable
1
X
1
Protected
Writable
Writable
6
FN8132.2
October 16, 2015
X5328, X5329
function (Table 2). WP is LOW and WPEN bit programmed HIGH disables all Status Register Write Operations.
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
In the locked state (Programmable ROM Mode) the WP
pin is LOW and the nonvolatile bit WPEN is “1”. This
mode disables nonvolatile writes to the device’s Status
Register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation disables subsequent write attempts to the Status Register.
Status Register Bits Array Addresses Protected
BL1
BL0
X5328/X5329
0
0
None
0
1
$0C00-$0FFF
1
0
$0800-$0FFF
1
1
$0000-$0FFF
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally.
Setting the WPEN bit in the Status Register to “0”
blocks the WP pin function, allowing writes to the Status
Register when WP is HIGH or LOW. Setting the WPEN
bit to “1” while the WP pin is LOW activates the Programmable ROM mode, thus requiring a change in the
WP pin prior to subsequent Status Register changes.
This allows manufacturing to install the device in a system with WP pin grounded and still be able to program
the Status Register. Manufacturing can then load Configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory
to be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB and
RFLB instructions. The Flag bit is automatically reset
upon power-up.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an In-Circuit Programmable ROM
Figure 5. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
SCK
Instruction
SI
SO
16 Bit Address
15 14 13
High Impedance
3
2
1
0
Data Out
7
6
5
4
3
2
1
0
MSB
7
FN8132.2
October 16, 2015
X5328, X5329
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation
is terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).
For the Page Write Operation (byte or page write) to
be completed, CS can only be brought HIGH after bit 0
of the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation
will not be completed (Figure 4).
To write to the Status Register, the WRSR instruction
is followed by the data to be written (Figure 5). Data
bits 0 and 1 must be “0”.
While the write is in progress following a Status Register or EEPROM Sequence, the Status Register may
be read to check the WIP bit. During this time the WIP
bit will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the Write Operation without taking CS HIGH
after issuing the WREN instruction, the Write Operation will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the
16-bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to
the first address of the page and overwrite any data
that may have been previously written.
8
– The Flag Bit is reset.
– Reset Signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the Write
Enable Latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
FN8132.2
October 16, 2015
X5328, X5329
Figure 6. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
4
3
2
1
0
MSB
Figure 7. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Figure 8. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
10
SCK
Instruction
16 Bit Address
15 14 13
SI
3
2
1
0
7
Data Byte 1
5 4 3 2
6
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
SI
7
6
5
4
9
3
2
Data Byte 3
1
0
7
6
5
4
3
Data Byte N
2
1
0
6
5
4
3
2
1
0
FN8132.2
October 16, 2015
X5328, X5329
Figure 9. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11 12 13 14 15
SCK
Instruction
SI
Data Byte
4
3
2
1
0
High Impedance
SO
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
10
FN8132.2
October 16, 2015
X5328, X5329
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
respect to VSS ...................................... -1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10s) .................... 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
-40°C
Max.
70°C
+85°C
Voltage Option
-2.7 or -2.7A
BLank or -4.5A
Supply Voltage
2.7V to 5.5V
4.5V-5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
ICC1
VCC Write Current (Active)
5
mA
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
ICC2
VCC Read Current (Active)
0.4
mA
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
ISB
VCC Standby Current
1
µA
CS = VCC, VIN = VSS or VCC,
VCC = 5.5V
ILI
Input Leakage Current
0.1
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
0.1
10
µA
VOUT = VSS to VCC
VIL(1)
VIH(1)
Input LOW Voltage
-0.5
VCC x 0.3
V
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output LOW Voltage
0.4
V
VOL2
Output LOW Voltage
0.4
V
VOL3
Output LOW Voltage
0.4
V
VCC  2V, IOL = 0.5mA
VOH1
Output HIGH Voltage
VCC - 0.8
V
VCC > 3.3V, IOH = -1.0mA
VOH2
Output HIGH Voltage
VCC - 0.4
V
VOH3
Output HIGH Voltage
VCC - 0.2
V
VCC  2V, IOH = -0.25mA
VOLS
Reset Output LOW Voltage
V
IOL = 1mA
0.4
VCC > 3.3V, IOL = 2.1mA
2V < VCC  3.3V, IOL = 1mA
2V < VCC  3.3V, IOH = -0.4mA
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
COUT(2)
CIN
(2)
Test
Max.
Unit
Conditions
Output Capacitance (SO, RESET, RESET)
8
pF
VOUT = 0V
Input Capacitance (SCK, SI, CS, WP)
6
pF
VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
11
FN8132.2
October 16, 2015
X5328, X5329
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
5V
5V
4.6k
2.06k
Output
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x0.5
RESET/RESET
3.03k
100pF
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
2.7-5.5V
Symbol
Parameter
Min.
Max.
Unit
0
2
MHz
fSCK
Clock Frequency
tCYC
Cycle Time
500
ns
tLEAD
CS Lead Time
250
ns
tLAG
CS Lag Time
250
ns
tWH
Clock HIGH Time
200
ns
tWL
Clock LOW Time
250
ns
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tRI(3)
tFI(3)
Input Rise Time
100
ns
Input Fall Time
100
ns
tCS
tWC
(4)
CS Deselect Time
Write Cycle Time
12
500
ns
10
ms
FN8132.2
October 16, 2015
X5328, X5329
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
SI
SO
tRI
tFI
MSB IN
LSB IN
High Impedance
Serial Output Timing
2.7-5.5V
Symbol
Parameter
Min.
Max.
Unit
0
2
MHz
Output Disable Time
250
ns
Output Valid from Clock Low
250
ns
fSCK
Clock Frequency
tDIS
tV
tHO
0
ns
Output Rise Time
100
ns
(3)
Output Fall Time
100
ns
tRO
tFO
Output Hold Time
(3)
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
SO
SI
MSB Out
tHO
MSB–1 Out
tWL
tDIS
LSB Out
ADDR
LSB IN
13
FN8132.2
October 16, 2015
X5328, X5329
Power-Up and Power-Down Timing
VCC
VTRIP
VTRIP
tPURST
0 Volts
tF
tPURST
tRPD
tR
RESET (X5328)
RESET (X5329)
RESET Output Timing
Symbol
VTRIP
VTH
Parameter
Reset Trip Point Voltage, X5328-4.5A, X5328-4.5A
Reset Trip Point Voltage, X5328, X5329
Reset Trip Point Voltage, X5328-2.7A, X5329-2.7A
Reset Trip Point Voltage, X5328-2.7, X5329-2.7
Power-up Reset Time Out
tRPD(5)
VCC Detect to Reset/Output
tR
(5)
VRVALID
Note:
Typ.
Max.
Unit
4.5
4.25
2.85
2.55
4.63
4.38
2.93
2.63
4.75
4.5
3.0
2.7
V
VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
tPURST
tF(5)
Min.
20
100
200
mV
280
ms
500
ns
VCC Fall Time
100
µs
VCC Rise Time
100
µs
1
V
Reset Valid VCC
(5) This parameter is periodically sampled and not 100% tested.
14
FN8132.2
October 16, 2015
X5328, X5329
VTRIP Set Conditions
tTHD
VCC
VTRIP
tTSU
tVPS
CS
tRP
tP
tVPH
tVPH
tVPS
tVPO
VP
SCK
VP
tVPO
SI
VTRIP Reset Conditions
VCC*
tRP
tVPS
CS
tVPS
tP
tVP1
tVPH
tVPO
VCC
SCK
VP
tVPO
SI
*VCC > Programmed VTRIP
15
FN8132.2
October 16, 2015
X5328, X5329
VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C
Parameter
Description
Min.
Max.
Unit
tVPS
SCK VTRIP Program Voltage Setup time
1
µs
tVPH
SCK VTRIP Program Voltage Hold time
1
µs
VTRIP Program Pulse Width
1
µs
tTSU
VTRIP Level Setup time
10
µs
tTHD
VTRIP Level Hold (stable) time
10
ms
tWC
VTRIP Write Cycle Time
tRP
VTRIP Program Cycle Recovery Period (Between successive programming cycles)
10
ms
tVPO
SCK VTRIP Program Voltage Off time before next cycle
0
ms
tP
VP
10
ms
Programming Voltage
15
18
V
VTRIP Programed Voltage Range
1.7
5.0
V
Vta1
Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25°C.)
-0.1
+0.4
V
Vta2
Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP]
(Programmed at 25°C.)
-25
+25
mV
Vtr
VTRIP Program Voltage repeatability (Successive program operations.) (programmed at
25°C)
-25
+25
mV
Vtv
VTRIP Program variation after programming (0-75°C). (programmed at 25°C)
-25
+25
mV
VTRAN
VTRIP programming parameters are periodically sampled and are not 100% tested.
16
FN8132.2
October 16, 2015
X5328, X5329
TYPICAL PERFORMANCE
tPURST vs. Temperature
VCC Supply Current vs. Temperature (ISB)
205
2
200
195
Time (ms)
Isb (µA)
190
(VCC = 3V, 5V)
1
185
180
175
170
165
160
-40
0
-40C
25C
Temp°C
90C
25
Degrees °C
90
VTRIP vs. Temperature (programmed at 25°C)
5.025
VTRIP = 5V
5.000
4.975
Voltage
3.525
VTRIP = 3.5V
3.500
3.475
2.525
VTRIP = 2.5V
2.500
2.475
0
25
Temperature
17
85
FN8132.2
October 16, 2015
X5328, X5329
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
October 16, 2015
FN8132.2
CHANGE
Updated the Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Replaced all Package Outline drawings with the most recent versions.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
18
FN8132.2
October 16, 2015
X5328, X5329
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
19
FN8132.2
October 16, 2015
X5328, X5329
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
20
FN8132.2
October 16, 2015
X5328, X5329
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
21
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
FN8132.2
October 16, 2015
Similar pages