DATASHEET

HIP6500B
TM
Data Sheet
May 2000
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6500B complements either an HIP6020 or an HIP6021
in ACPI-compliant designs for microprocessor and computer
applications. The IC integrates two linear controllers and two
regulators, switching, monitoring and control functions into a
20-pin SOIC package. One linear controller generates the
3.3VDUAL voltage plane from the ATX supply’s 5VSB output,
powering the PCI slots through an external pass transistor
during sleep states (S3, S4/S5). A second transistor is used to
switch in the ATX 3.3V output for operation during S0 and
S1/S2 (active) operating states. The second linear controller
supplies the computer system’s 2.5V/3.3V memory power
through an external pass transistor in active states. During S3
state, an integrated pass transistor supplies the 2.5V/3.3V
sleep power. A third controller powers up the 5VDUAL plane by
switching in the ATX 5V output in active states, and the ATX
5VSB in sleep states. The two internal regulators consist of a
low current 3.3V sleep output and a dedicated, noise-free 2.5V
clock chip supply. The HIP6500B’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Further control of the logic governing
activation of different power states is offered through two
configuration pins, EN3VDL and EN5VDL. In active state, the
3.3VDUAL linear regulator uses an external N-Channel pass
MOSFET to connect the output directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, for minimal
losses. In sleep state, power delivery on the 3.3VDUAL output is
transferred to an NPN transistor, also external to the controller.
Active state power delivery for the 2.5/3.3VMEM output is
performed through an external NPN transistor, or an NMOS
switch for the 3.3V setting. In sleep state, conduction on this
output is transferred to an internal pass transistor. The 5VDUAL
output is powered through two external MOS transistors. In
sleep states, a PMOS (or PNP) transistor conducts the current
from the ATX 5VSB output; while in active state, current flow is
transferred to an NMOS transistor connected to the ATX 5V
output. Similar to the 3.3VDUAL output, the operation of the
5VDUAL output is dictated not only by the status of the S3 and
S5 pins, but that of the EN5VDL pin as well. The 3.3VSB
internal regulator is active for as long as the ATX 5VSB voltage
is applied to the chip, and derives its output current from the
5VSB pin. The 2.5VCLK output is only active during S0 and S1,
and uses the 3V3 pin as input source for its internal pass
element.
File Number
4870
Features
• Provides 5 ACPI-Controlled Voltages
- 5V Active/Sleep (5VDUAL)
- 3.3V Active/Sleep (3.3VDUAL)
- 2.5V/3.3V Active/Sleep (2.5/3.3VMEM)
- 3.3V Always Present (3.3VSB)
- 2.5V Clock (Active Only) (2.5VCLK)
• Excellent Output Voltage Regulation
- 3.3VDUAL Output: ±2% Over Temperature; Sleep State
Only
- 2.5V/3.3VMEM Output: ±2% Over Temperature; Both
Operational States (3.3V setting in sleep only)
- 2.5VCLK and 3.3VSB Output: ±2% Over Temperature
• Small Size
- Very Low External Component Count
• Selectable Memory Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
• Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6500B
(SOIC)
TOP VIEW
VSEN2
1
5VSB 2
3V3SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
20 EN3VDL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
EN5VDL
8
13 DLA
S3
9
12 FAULT/MSEL
S5 10
11 GND
Ordering Information
PART NUMBER
HIP6500BCB
HIP6500BEVAL1
TEMP.
RANGE (oC)
0 to 70
PACKAGE
20 Ld SOIC
PKG.
NO.
M20.3
Evaluation Board
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
Block Diagram
12V
5V 3V3
3V3DL
3V3DLSB
5VDLSB DLA
5VSB
EA4
-
5VSB POR
+
TEMPERATURE
MONITOR
(TMON)
4.4V/3.2V
2
12V MONITOR
3V3 MONITOR
2.97V/2.8V
5V MONITOR
10.8V/9.8V
4.5V/4.25V
TO 5VSB
EA3
+
TO 3V3
MONITOR AND CONTROL
+
TO
UV DETECTOR
EA3
VCLK
FAULT/MSEL
UV DETECTOR
+
TO 5V
1.265V
-
DRV2
TO 5VSB
TO
UV DETECTOR
10µA
40µA
EA2
-
+
+
+
3.75V
UV COMPARATOR
VSEN2
-
5VDL
GND
SS
S3
S5
EN3VDL EN5VDL
FIGURE 1.
HIP6500B
TO
UV
DETECTOR
3V3SB
HIP6500B
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
3.3VSB
3.3V
Q1
LINEAR
CONTROLLER
LINEAR
REGULATOR
VMEM
2.5V/3.3V
Q2
LINEAR
CONTROLLER
Q3
3.3VDUAL
VCLK
LINEAR
REGULATOR
2.5V
Q4
3.3V
FAULT/MSEL
HIP6500B
Q5
CONTROL
LOGIC
5VDUAL
5V
SHUTDOWN
SX
2
ENXVDL
2
FIGURE 2.
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
12V
VOUT1
5VSB
3V3
3V3SB
3.3VSB
Q1
DRV2
COUT1
5V
VSEN2
3V3DLSB
Q2
2.5/3.3VMEM
Q3
VOUT3
VOUT2
COUT2
3V3DL
3.3VDUAL
COUT3
VOUT4
VCLK
FAULT/MSEL
HIP6500B
2.5VCLK
COUT4
Q4
RSEL
FAULT
5VDLSB
S3
SLP_S3
DLA
Q5
S5
SLP_S5
EN3VDL
EN3VDL
COUT5
SS
CSS
SHUTDOWN
FIGURE 3.
3
VOUT5
5VDL
EN5VDL
EN5VDL
GND
5VDUAL
HIP6500B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ± 5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSX, VEN5VDL, VEN3VDL . . . . . . . . . . . . . 0 to +5.5V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
30
-
mA
-
14
-
mA
Rising 5VSB POR Threshold
-
-
4.5
V
5VSB POR Hysteresis
-
1.0
-
V
Rising 12V Threshold
-
-
10.8
V
12V Hysteresis
-
1.0
-
V
Rising 3V3 and 5V Thresholds
-
90
-
%
3V3 and 5V Hysteresis
-
5
-
%
VCC SUPPLY CURRENT
Nominal Supply Current
I5VSB
Shutdown Supply Current
I5VSB(OFF)
VSS = 0.8V
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
Soft-Start Current
ISS
-
10
-
µA
Shutdown Voltage Threshold
VSD
-
-
0.8
V
-
-
2.0
%
-
3.3
-
V
3V3SB Undervoltage Rising Threshold
-
2.739
-
V
3V3SB Undervoltage Hysteresis
-
99
-
mV
250
300
-
mA
-
-
2.0
%
3.3VSB LINEAR REGULATOR (VOUT1)
Regulation
3V3SB Nominal Voltage Level
V3V3SB
3V3SB Output Current
I3V3SB
5VSB = 5V
2.5/3.3VMEM LINEAR REGULATOR (VOUT2)
Regulation (Note 2)
VSEN2 Nominal Voltage Level
VVSEN2
RSEL = 1kΩ
-
2.5
-
V
VSEN2 Nominal Voltage Level
VVSEN2
RSEL = 10kΩ
-
3.3
-
V
VSEN2 Undervoltage Rising Threshold
-
83
-
%
VSEN2 Undervoltage Hysteresis (Note 3)
-
3
-
%
250
300
-
mA
VSEN2 Output Current
IVSEN2
4
5VSB = 5V
HIP6500B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
220
-
-
mA
-
200
-
Ω
-
-
2.0
%
-
3.3
-
V
3V3DL Undervoltage Rising Threshold
-
2.739
-
V
3V3DL Undervoltage Hysteresis
-
99
-
mV
5
10
-
mA
-
90
-
Ω
-
-
2.0
%
-
2.5
-
V
VCLK Undervoltage Rising Threshold
-
2.075
-
V
VCLK Undervoltage Hysteresis
-
75
-
mV
500
800
-
mA
5VDL Undervoltage Rising Threshold
-
4.150
-
V
5VDL Undervoltage Hysteresis
-
150
-
mV
-20
-
-40
mA
-
350
-
Ω
20
25
30
ms
-
200
-
µs
High Level Input Threshold
-
-
2.2
V
Low Level Input Threshold
0.8
-
-
V
-
50
-
kΩ
-
100
-
Ω
125
-
-
oC
-
155
-
oC
DRV2 Output Drive Current
IDRV2
DRV2 Output Impedance
TEST CONDITIONS
5VSB = 5V, RSEL = 1kΩ
RSEL = 10kΩ
3.3VDUAL LINEAR REGULATOR (VOUT3)
Sleep State Regulation
3V3DL Nominal Voltage Level
V3V3DL
3V3DLSB Output Drive Current
I3V3DLSB
5VSB = 5V
DLA Output Impedance
2.5VCLK LINEAR REGULATOR (VOUT4)
Regulation
VCLK Nominal Voltage Level
VVCLK
VCLK Output Current (Note 4)
IVCLK
V3V3 = 3.3V
5VDUAL SWITCH CONTROLLER (VOUT5)
5VDLSB Output Drive Current
I5VDLSB
5VDLSB = 4V, 5VSB = 5V
5VDLSB Pull-up Impedance to 5VSB
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 5)
Active-to-Sleep Control Input Delay
CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT/MSEL)
S3, S5 Internal Pull-Up Impedance to 5VSB
FAULT Output Impedance
FAULT = high
TEMPERATURE MONITOR
Fault-Level Threshold (Note 6)
Shutdown-Level Threshold (Note 6)
NOTES:
2. Sleep state only f9or 3.3V setting
3. Valid for 3.3V setting only.
4. At ambient temperatures less than 50oC.
5. Guaranteed by correlation.
6. Guaranteed by design.
5
HIP6500B
Functional Pin Descriptions
3V3 (Pin 7)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 2V5CLK pin, and is monitored for
power quality.
5VSB (Pin 2)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides the output current for the 3V3SB and VSEN2 pins,
as well as the base current for Q2. The voltage at this pin is
monitored for power-on reset (POR) purposes.
5V (Pin 18)
Connect this pin to the ATX 5V output. This pin provides the
base bias current for Q1, and is monitored for power quality.
12V (Pin 17)
Connect this pin to the ATX 12V output. This pin provides the
gate bias voltage for Q3 and Q5, and is monitored for power
quality.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
S3 and S5 (Pins 9 and 10)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50kΩ (typical) resistor pull-ups to
5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2µs (typically). Additional
circuitry blocks any illegal state transitions (such as S3 to
S4/S5 or vice versa). Respectively, connect S3 and S5 to the
computer system’s SLP_S3 and SLP_S5 signals.
SS (Pin 16)
Connect this pin to a small ceramic capacitor (no less than 5nF;
0.1µF recommended). The internal soft-start (SS) current
source along with the external capacitor creates a voltage ramp
used to control the ramp-up of the output voltages. Pulling this
pin low with an open-drain device shuts down all the outputs as
well as force the FAULT pin low. The CSS capacitor is also used
to provide a controlled voltage slew rate during active-to-sleep
transitions on the 3.3VDUAL, and VMEM outputs.
VSEN2 (Pin 1)
Connect this pin to the memory output (VOUT2). In sleep
states, this pin is regulated to 2.5V or 3.3V (based on RSEL)
through an internal pass transistor capable of delivering
300mA (typically). When VOUT2 is programmed to 2.5V, the
active-state voltage at this pin is regulated through an
external NPN transistor connected at the DRV2 pin. For the
3.3V setting, the ATX 3.3V is passed to this pin through a
fully on N-MOS transistor. During all operating states, the
voltage at this pin is monitored for under-voltage events.
DRV2 (Pin 19)
For the 2.5V RDRAM systems connect this pin to the base of
a suitable NPN transistor. This pass transistor regulates the
2.5V output from the ATX 3.3V during active states
operation. For 3.3V SDRAM systems connect this pin to the
gate of a suitable N-MOS transistor; this transistor is used to
switch in the ATX 3.3V output.
3V3DL (Pin 5)
Connect this pin to the 3.3V dual output (VOUT3). In sleep
states, the voltage at this pin is regulated to 3.3V; in active
states, ATX 3.3V output is delivered to this node through a
fully on N-MOS transistor. During all operating states, this
pin is monitored for under-voltage events.
EN3VDL and EN5VDL (Pins 20 and 8)
3V3DLSB (Pin 4)
These pins control the logic governing the dual outputs’
behavior in response to S3 and S4/S5 requests. These are
digital inputs whose status can only be changed during
active states operation or during chip shutdown (SS pin
grounded by external open-drain device or chip bias below
POR level). The input information is latched-in when
entering a sleep state, as well as following 5VSB POR
release or exit from shutdown. EN3VDL features an internal
50kΩ pull-down resistor, while EN5VDL is internally pulled
high through a similar resistor.
Connect this pin to the base of a suitable NPN transistor. In
sleep state, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
FAULT/MSEL (Pin 12)
This is a multiplexed function pin allowing the setting of the
memory output voltage to either 2.5V or 3.3V (for RDRAM or
SDRAM memory systems). In case of an undervoltage on
any of the outputs or on any of the monitored ATX outputs, or
in case of an overtemperature event, this pin is used to
report the fault condition by being pulled to 5VSB.
6
DLA (Pin 13)
Connect this pin to the gates of suitable N-MOSFETs, which
in active state, switch in the ATX 3.3V and 5V outputs into
the 3.3VDUAL and 5VDUAL outputs, respectively.
5VDL (Pin 15)
Connect this pin to the 5VDUAL output (VOUT5). In either
operating state, the voltage at this pin is provided through a
fully on MOS transistor. This pin is also monitored for
undervoltage events.
5VDLSB (Pin 14)
Connect this pin to the gate of a suitable P-MOSFET or
bipolar PNP. In sleep state, this transistor is switched on,
connecting the ATX 5VSB output to the 5VDUAL regulator
output.
HIP6500B
3V3SB (Pin 3)
This pin is the output of the internal 3.3VSB regulator
(VOUT1). This internal regulator operates continuously for as
long as the 5VSB bias voltage is applied to the HIP6500B.
This pin is monitored for under-voltage events.
As seen in Table 1, EN3VDL simply controls whether the
3.3VDUAL plane remains powered up during S4/S5 sleep
state.
TABLE 2. 5VDUAL OUTPUT (VOUT5) TRUTH TABLE
EN5VDL
S5
S3
5VDL
0
1
1
5V
S0, S1 States (Active)
0
1
0
0V
S3
0
0
1
Note
0
0
0
0V
S4/S5
1
1
1
5V
S0, S1 States (Active)
Description
1
1
0
5V
S3
Operation
1
0
1
Note
The HIP6500B controls 5 output voltages (Refer to Figures
1, 2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of two linear
controllers supplying the PCI slots’ 3.3VAUX power (VOUT3)
and the 2.5V RDRAM or 3.3V SDRAM memory power
(VOUT2), two linear regulators providing an always-present
3.3VSB (VOUT1), and a dedicated 2.5V clock chip supply
(VOUT4), a dual switch controller supplying the 5VDUAL
voltage (VOUT5), as well as all the control and monitoring
functions necessary for complete ACPI implementation.
1
0
0
5V
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator
(VOUT4). This internal regulator operates only in active
states (S0, S1) and is shut off during any sleep state,
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Initialization
The HIP6500B automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating 3.3VSB
soft-start operation after exceeding POR threshold. At 3ms
(typically) after 3.3VSB finishes its ramp-up, the ENxVDL
status and the memory voltage (VMEM) setting are latched in
and the chip proceeds to ramp up the remainder of the
voltages, as required.
Operational Truth Tables
COMMENTS
Maintains Previous State
Maintains Previous State
S4/S5
NOTE: Combination Not Allowed.
Very similarly, Table 2 details the fact that EN5VDL status
controls whether the 5VDUAL plane supports the S3-S5
sleep states.
TABLE 3. 2.5/3.3VMEM OUTPUT (VOUT2) TRUTH TABLE
RSEL
S5
S3
2.5/3.3VMEM
1kΩ
1
1
2.5V
S0, S1 States (Active)
1kΩ
1
0
2.5V
S3
1kΩ
0
1
Note
Maintains Previous State
1kΩ
0
0
0V
10kΩ
1
1
3.3V
S0, S1 States (Active)
10kΩ
1
0
3.3V
S3
10kΩ
0
1
Note
Maintains Previous State
10kΩ
0
0
0V
COMMENTS
S5
S5
NOTE: Combination Not Allowed.
The EN3VDL and EN5VDL pins offer a choice of 4
configurations in terms of the overall system architecture
and supported features. Tables 1-3 describe the truth
combinations pertaining to each of the three outputs.
TABLE 1. 3.3VDUAL OUTPUT (VOUT3) TRUTH TABLE
EN3VDL
S5
S3
3V3DL
0
1
1
3.3V
S0, S1 States (Active)
0
1
0
3.3V
S3
0
0
1
Note
Maintains Previous State
0
0
0
3.3V
S4/S5
1
1
1
3.3V
S0, S1 States (Active)
1
1
0
3.3V
S3
1
0
1
Note
Maintains Previous State
1
0
0
0V
NOTE: Combination Not Allowed.
7
COMMENTS
S4/S5
As seen in Table 3, 2.5/3.3VMEM output is maintained in S3
(suspend to RAM) sleep state only. The dual-voltage support
accommodates both SDRAM as well as RDRAM type
memories.
Not shown in any of the tables are the 3.3VSB and the
2.5VCLK outputs. The 3.3VSB output powers up as soon as
the 5VSB ATX output is available. The 2.5VCLK output
operation is restricted by the chip’s POR and is only
available in active state (S0, S1). For additional information,
see the soft-start sequence diagrams.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S5) and vice versa.
HIP6500B
Functional Timing Diagrams
Figures 4 through 8 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN3VDL, EN5VDL) and sleep-state
pins (S3, S5), as well as the status of the ATX supply.
The status of the EN3VDL and EN5VDL pins can only be
changed while in active (S0, S1) states, when the bias
supply (5VSB pin) is below POR level, or during chip
shutdown (SS pin shorted to GND); a status change of these
two pins while in a sleep state is ignored.
Not shown in these diagrams is the deglitching feature used
to protect against false sleep state tripping. Both S3 and S5
pins are protected against noise by a 2µs filter (typically 1 4µs). This feature is useful in noisy computer environments if
the control signals have to travel over significant distances.
Additionally, the S3 pin features a 200µs delay in
transitioning to sleep states. Once the S3 pin goes low, an
internal timer is activated. At the end of the 200µs interval, if
the S5 pin is low, the HIP6502 switches into S5 sleep state; if
the S5 pin is high, the HIP6502 goes into S3 sleep state.
5VSB
5VSB
S3
S3
S5
S5
12V
12V
3V3DLSB
3V3DLSB
DLA
DLA
3V3DL
3V3DL
5VDLSB
5VDLSB
5VDL
5VDL
FIGURE 4. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 1
FIGURE 6. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR
EN3VDL = 0, EN5VDL = 1
5VSB
5VSB
S3
S3
S5
S5
12V
12V
3V3DLSB
3V3DLSB
DLA
DLA
3V3DL
3V3DL
5VDLSB
5VDLSB
5VDL
5VDL
FIGURE 5. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 0
8
FIGURE 7. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR
EN3VDL = 0, EN5VDL = 0
HIP6500B
5VSB
S3
S5
12V
INTERNAL
VSEN2
DEVICE
DRV2
VSEN2
3V3SB
VCLK
FIGURE 8. 2.5/3.3VMEM, 3.3VSB AND VCLK TIMING DIAGRAM
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10µA current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
Figure 9 shows the soft-start sequence for the typical
application start-up in sleep state with all output voltages
enabled. At time T0 5VSB (bias) is applied to the circuit. At
time T1 the 5VSB surpasses POR level. An internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10µA current source continues
the charging. The soft-start capacitor voltage reaches
approximately 1.25V at time T2, at which point the 3.3VSB
error amplifiers’ reference input starts its transition, causing
the output voltage to ramp up proportionally. The ramp-up
continues until time T3 when the 3.3VSB voltage reaches the
set value. After the 3.3VSB reached its set value, as the softstart capacitor voltage reaches approximately 2.75V, the
under-voltage monitoring circuit of this output is activated
and the soft-start capacitor is quickly discharged to
approximately 1.25V. Following the 3ms (typical) time-out
between T3 and T4, the memory and enabling pins’
selection are latched in, and the soft-start capacitor
commences a second ramp-up designed to smoothly bring
up the remainder of the voltages required by the system. At
time T5 all voltages are within regulation limits, and as the
SS voltage reaches 2.75V, all the UV monitors are activated
and the SS capacitor is quickly discharged to 1.25V, where it
remains until the next transition.
+12VIN
DLA PIN
(2V/DIV)
INPUT VOLTAGES
(2V/DIV)
+5VIN
+5VSB
5VSB
(1V/DIV)
+3.3VIN
SOFT-START
(1V/DIV)
SOFT-START
(1V/DIV)
0V
OUTPUT
VOLTAGES
(1V/DIV)
0V
VOUT5 (5VDUAL)
VOUT1 (3.3VSB)
VOUT5 (5VDUAL)
VOUT1 (3.3VSB)
VOUT3 (3.3VDUAL)
VOUT3 (3.3VDUAL)
OUTPUT
VOLTAGES
(1V/DIV)
VOUT2
(2.5VMEM)
VOUT2, 4
(2.5VMEM, 2.5VCLK)
0V
VOUT4
(2.5VCLK)
T0
T1
T2
TIME
T3
0V
T0 T1 T2
T3
T4
TIME
T5
FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE
(ALL OUTPUTS ENABLED)
9
FIGURE 10. SOFT-START INTERVAL IN ACTIVE STATE
(2.5/3.3VMEM OUTPUT SHOWN IN 2.5V SETTING)
HIP6500B
SOFT-START INTO ACTIVE STATES (S0, S1)
If both S3 and S5 are logic high at the time the 5VSB is
applied, the HIP6500B will assume active state wake-up and
keep off the controlled external transistors and the VCLK
output until some time (typically 25ms) after the ATX’s main
outputs used by the application (3.3V, 5V, and 12V) exceed
the set thresholds. This time-out feature is necessary in order
to insure the main ATX outputs are stabilized. The time-out
also assures smooth transitions from sleep into active when
sleep states are being supported. 3.3VSB output, whose
operation is only dependent on 5VSB presence, will come up
right as bias voltage reaches POR level.
During sleep to active state transitions from conditions
where the outputs are initially 0V (such as S5 to S0 transition
with EN3VDL = 1 and EN5VDL = 0, or simple power-up
sequence directly into active state), the 3VDUAL and
5VDUAL outputs go through a quasi soft-start by being pulled
high through the body diodes of the N-Channel MOSFETs
connected between these outputs and the 3.3V and 5V ATX
outputs. Figure 10 shows this start-up.
5VSB is already present when the main ATX outputs are
turned on at time T0. As a result of +3.3VIN and +5VIN
ramping up, the 3.3VDUAL and 5VDUAL output capacitors
charge up through the body diodes of Q3 and Q5,
respectively (see Figure 3). At time T1, all main ATX outputs
exceed the HIP6500B’s undervoltage thresholds, and the
internal 25ms (typical) timer is initiated. At T2 the time-out
initiates a soft-start, and the memory and clock outputs are
ramped-up, reaching regulation limits at time T3.
Simultaneous with the beginning of the memory and clock
voltage ramp-up, at time T2, the DLA pin is pulled high,
turning on Q3 and Q5 in the process, and bringing the
3.3VDUAL and 5VDUAL outputs in regulation. Shortly after
time T3, as the SS voltage reaches 2.75V, the soft-start
capacitor is quickly discharged down to approximately 2.45V,
where it remains until a valid sleep state request is received
from the system.
controlled through an internal pass transistor, will set off the
FAULT flag, and it will shut off the faulting regulator only. If
shutdown or latch off of the entire circuit is desired in case of
a fault, regardless of the cause, this can be achieved by
externally pulling or latching the SS pin low. Pulling the SS
pin low will also force the FAULT pin to go low and reset an
internally latched-off output.
Special consideration is given to the initial start-up sequence.
If, following a 5VSB POR event, the 3.3VSB output is ramped
up and is subject to an undervoltage event before the
remainder of the controlled voltages have been brought up,
then the FAULT output goes high and the entire IC latches off.
Latch-off condition can be reset by cycling the bias power
(5VSB). Undervoltage events on the 3.3VSB output at any
other times are handled according to the description found in
the second paragraph under the current heading.
Another condition that could set off the FAULT flag is chip
over-temperature. If the HIP6500B reaches an internal
temperature of 140oC (typical), the FAULT flag is set off, but
the chip continues to operate until the temperature reaches
155oC (typical), when unconditional shutdown of all outputs
takes place. Operation resumes at 140oC and the
temperature cycling occurs until the fault-causing condition
is removed.
In HIP6500B applications, loss of any one active ATX output
(3.3VIN, 5VIN, or 12VIN; as detected by the on-board voltage
monitors) during active state operation causes the chip to
switch to S5 sleep state, in addition to reporting the input UV
condition on the FAULT/MSEL pin. Exiting from this forcedS5 state can only be achieved by returning the faulting input
voltage above its UV threshold, by resetting the chip through
removal of 5VSB bias voltage, or by bringing the SS pin at a
potential lower than 0.8V.
Output Voltages
The output voltages are internally set and do not require any
external components. Selection of the VMEM memory
Fault Protection
All the outputs are monitored against undervoltage events. A
severe overcurrent caused by a failed load on any of the
outputs, would, in turn, cause that specific output to
suddenly drop. If any of the output voltages drop below 80%
(typical) of their set value, such event is reported by having
the FAULT/MSEL pin pulled to 5V. Additionally, exceeding
the maximum current rating of an integrated regulator
(output with pass regulator on chip) can lead to output
voltage drooping; if excessive, this droop can ultimately trip
the undervoltage detector and send a FAULT signal to the
computer system.
A FAULT condition occurring on an output when controlled
through an external pass transistor will only set off the
FAULT flag, and it will not shut off or latch off any part of the
circuit. A FAULT condition occurring on an output when
10
RSEL
VMEM
1kΩ
10kΩ
2.5V
3.3V
FAULT/MSEL
5VSB
40µA
MEM VOLTAGE
SELECT COMP
+
RSEL
+
-
0.2V
FIGURE 11. 2.5/3.3VMEM OUTPUT VOLTAGE SELECTION
CIRCUITRY DETAILS
HIP6500B
Soft-Start Interval
The 5VSB output of a typical ATX supply is capable of
725mA. During power-up in a sleep state, it needs to provide
sufficient current to charge up all the output capacitors and
simultaneously provide some amount of current to the output
loads. Drawing excessive amounts of current from the 5VSB
output of the ATX can lead to voltage collapse and induce a
pattern of consecutive restarts with unknown effects on the
system’s behavior or health.
The built-in soft-start circuitry allows tight control of the slewup speed of the output voltages controlled by the HIP6500B,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
current dedicated to charging the output capacitors can be
calculated with the following formula:
The typical application employing a HIP6500B is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
load if possible, but not excessively far from the clock chip or
the processor. Insure the VSEN2 connection is properly
sized to carry 250mA without significant resistive losses;
similar guideline applies to the VCLK output, which can
deliver as much as 800mA (typical). As the current for the
VCLK output is provided from the ATX 3.3V, the connection
from the 3V3 pin to the 3.3V plane should be sized to carry
the maximum clock output current while exhibiting negligible
voltage losses. Similarly, the current for the 3.3VSB output is
provided from the 5VSB pin, and the output current on pin
DRV2 from the 5V pin - for best results, insure these pins are
connected to their respective sources through adequate
traces. The pass transistors should be placed on pads
capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
+12VIN
+5VSB
I SS
I COUT = ------------------------------ × Σ ( C OUT × V OUT ) , where
C SS × V BG
ISS - soft-start current (typically 10µA)
5VSB
12V
SS
CSS - soft-start capacitor
VBG - bandgap voltage (typically 1.26V)
3V3SB
LOAD
Q2
CHF5
CBULK5
3V3DLSB
CHF3
HIP6500B
VOUT3
3V3DL
LOAD
CBULK3
Q5
DLA
+5VIN
5V
VOUT2
VCLK
Q3
3V3
CHF2
VSEN2
GND DRV2
Q1
CBULK4
CBULK2
CHF4
+3.3VIN
LOAD
In case of a FAULT condition that might endanger the
computer system, or at any other time, all the HIP6500B
outputs can be shut down by pulling the SS pin below the
specified shutdown level (typically 0.8V) with an open drain
or open collector device capable of sinking a minimum of
2mA. Pulling the SS pin low effectively shuts down all the
pass elements. Upon release of the SS pin, the HIP6500B
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control pins
status.
5VDL
VOUT1
Due to the various system timing events, it is recommended
that the soft-start interval not be set to exceed 30ms.
Shutdown
VOUT5
CBULK1
Σ(COUT x VOUT) - sum of the products between the
capacitance and the voltage of an output (total charge
delivered to all outputs).
Q4
5VDLSB
CSS
CHF1
CIN
C5VSB
C12V
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 12. PRINTED CIRCUIT BOARD ISLANDS
11
LOAD
Application Guidelines
Layout Considerations
LOAD
voltage is done by means of an external resistor connected
between the FAULT/MSEL pin and ground. An internal 40µA
(typical) current source creates a voltage drop across this
resistor. Following every 3.3VSB ramp-up or chip reset (see
Soft-Start Circuit), this voltage is compared with an internal
reference and the setting is latched in. Based on this
comparison, the output voltage is set at either 2.5V
(RSEL = 1kΩ), or 3.3V (RSEL = 10kΩ). It is very important
that no capacitor is connected to the FAULT/MSEL pin; the
presence of a capacitive element at this pin can lead to false
memory voltage selection. See Figure 11 for details.
HIP6500B
Placement of the decoupling and bulk capacitors should
follow a placement reflecting their purpose. As such, the
high-frequency decoupling capacitors should be placed as
close as possible to the load they are decoupling; the ones
decoupling the controller close to the controller pins, the
ones decoupling the load close to the load connector or the
load itself (if embedded). Even though bulk capacitance
(aluminum electrolytics or tantalum capacitors) placement is
not as critical as the high-frequency capacitor placement,
having these capacitors close to the load they serve is
preferable.
The only critical small signal component is the soft-start
capacitor, CSS . Locate this component close to SS pin of the
control IC and connect to ground through a via placed close
to the capacitor’s ground pad. Minimize any leakage current
paths from SS node, since the internal current source is only
10µA.
A multi-layer printed circuit board is recommended. Figure
12 shows the connections of most of the components in the
converter. Note that the individual capacitors each could
represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections through vias placed as close to the
component terminal as possible. Dedicate another solid
layer as a power plane and break this plane into smaller
islands of common voltage levels. Ideally, the power plane
should support both the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers to create power islands connecting the filtering
components (output capacitors) and the loads. Use the
remaining printed circuit layers for small signal wiring.
IOUT - output current during transition
COUT - output capacitor bank capacitance
tt - active-to-sleep or sleep-to-active transition time (10µs typ).
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
VCLK (VOUT4) Output Capacitors Selection
The output capacitor for the VCLK linear regulator provides
loop stability. Figure 13 outlines a capacitance vs. equivalent
series resistance envelope. For stable operation and
optimized performance, select a COUT4 capacitor or
combination of capacitors with characteristics within the
shown envelope.
10
d
Component Selection Guidelines
Output Capacitors Selection
The output capacitors for all outputs should be selected to
allow the output voltage to meet the dynamic regulation
requirements of active state operation (S0, S1). The load
transient for the various microprocessor system’s
components may require high quality capacitors to supply
the high slew rate (di/dt) current demands. Thus, it is
recommended that the output capacitors be selected for
transient load regulation, paying attention to their parasitic
components (ESR, ESL).
Also, during the transition between active and sleep states,
there is a short interval of time during which none of the
power pass elements are conducting - during this time the
output capacitors have to supply all the output current. The
output voltage drop during this brief period of time can be
easily approximated with the following formula:
tt 

∆V OUT = I OUT ×  ESR OUT + ---------------- , where
C

OUT
∆VOUT - output voltage drop
ESROUT - output capacitor bank ESR
12
ESR (Ω)
1.0
0.1
0.01
10
100
1000
CAPACITANCE (µF)
FIGURE 13. COUT4 OUTPUT CAPACITOR
Input Capacitors Selection
The input capacitors for an HIP6500B application have to
have a sufficiently low ESR as to not allow the input voltage
to dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the HIP6500B’s regulation levels could have as
a result a brisk transfer of energy from the input capacitors to
the supplied outputs. At the transition between active and
sleep states, this phenomena could result in the 5VSB
voltage dropping below the POR level (typically 4.1V) and
temporarily disabling the HIP6500B. The solution to a
potential problem such as this is using larger input
capacitors with a lower total combined ESR.
HIP6500B
Transistor Selection/Considerations
Q5
The HIP6500B usually requires one P-Channel (or bipolar
PNP), two N-Channel MOSFETs and two bipolar NPN
transistors.
If a P-Channel MOSFET is used to switch the 5VSB output
of the ATX supply into the 5VDUAL output during S3 and S5
states (as dictated by EN5VDL status), then, similar to the
situation where Q1 is a MOSFET, the selection criteria of this
device is also proper voltage budgeting. The maximum
rDS(ON) , however, has to be achieved with only 4.5V of VGS ,
so a logic level MOSFET needs to be selected. If a PNP
device is chosen to perform this function, it has to have a low
saturation voltage while providing the maximum sleep
current and have a current gain sufficiently high to be
saturated using the minimum drive current (typically 20mA).
One important criteria for selection of transistors for all the
linear regulators/switching elements is package selection for
efficient removal of heat. The power dissipated in a linear
regulator/switching element is
P LINEAR = I O × ( V IN – V OUT )
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q1
The active element on the 2.5V/3.3VMEM output has
different requirements for each of the two voltage settings. In
2.5V systems utilizing RDRAM (or voltage-compatible)
memory, Q1 has to be a bipolar NPN capable of conducting
up to 7.5A and exhibit a current gain (hfe) of minimum 40 at
this current and 0.7V VCE; in such systems the 2.5V output
is actively regulated while in active state. In 3.3V systems
(SDRAM or compatible) Q1 has to be an N-Channel
MOSFET; in such systems the MOSFET is switched on
during active state (S0, S1). The main criteria for the
selection of this transistor is output voltage budgeting. The
maximum rDS(ON) allowed at highest junction temperature
can be expressed with the following equation:
V INmin – V OUTmin
r DS ( ON )max = --------------------------------------------------- , where
I OUTmax
VINmin - minimum input voltage
VOUTmin - minimum output voltage allowed
IOUTmax - maximum output current
The gate bias available for this MOSFET is of the order of 8V.
13
Q3, Q4
The two N-Channel MOSFETs are used to switch the 3.3V
and 5V inputs provided by the ATX supply into the
3.3VDUAL and 5VDUAL outputs, respectively, while in active
(S0, S1) state. Similar rDS(ON) criteria apply in these cases
as well. Unlike the PMOS, however, these NMOS transistors
get the benefit of an increased VGS drive (approximately 8V
and 7V, respectively).
Q2
The NPN transistor used as sleep state pass element (Q2)
on the 3.3VDUAL output has to have a minimum current gain
of 100 at 1.5V VCE and 500mA ICE throughout the in-circuit
operating temperature range.
HIP6500B
HIP6500B Application Circuit
Figure 14 shows an application circuit of an ACPIsanctioned power management system for a microprocessor
computer system. The power supply provides the 3.3VSB
voltage (VOUT1), the PCI 3.3VDUAL voltage (VOUT3), the
RDRAM 2.5VMEM memory voltage (VOUT2), the 2.5VCLK
clock voltage (VOUT4), and the 5VDUAL voltage (VOUT5)
from +3.3V, +5VSB, and +12VDC ATX supply outputs. For
systems employing SDRAM memory, replace R1 with 10kΩ
and Q1 with an HUF76113SK8. Q4 can also be a PNP, such
as an MMBT2907AL. For detailed information on the circuit,
including a Bill-of-Materials and circuit board description,
see Application Note AN9862.
Also see Intersil Corporation’s web page (www.intersil.com)
or Intersil AnswerFAX
(321-724-7800) for the latest information.
+5VIN
+12VIN
+3.3VIN
+5VSB
+
C1
1µF
C3
1µF
12V
3V3
5VSB
C2
220µF
C4
1µF
VOUT1
3.3VSB
+
3V3SB
DRV2
5V
VSEN2
VOUT2
3V3DLSB
Q2
2SD1802
VOUT3
Q1
2SD1802
C5
10µF
C6,7 +
2X150µF
2.5VMEM
C8
1µF
Q3
1/2 HUF76113DK8
VOUT4
3V3DL
VCLK
3.3VDUAL
+
C9
1µF
C10
220µF
U1
HIP6500B
2.5VCLK
C11 +
150µF
C12
1µF
FAULT/MSEL
Q4
FDV304P
5VDLSB
R1
1K
EN5VDL
CONFIGURATION
HARDWARE
DLA
EN3VDL
S3
SLP_S3
Q5
1/2
HUF76113DK8
5VDL
VOUT5
S5
SLP_S5
+
SS
C13
0.1µF
GND
SHUTDOWN
(FROM OPEN-DRAIN N-MOS)
FIGURE 14. TYPICAL HIP6500B APPLICATION DIAGRAM
14
C14
150µF
C15
1µF
5VDUAL
HIP6500B
Small Outline Plastic Packages (SOIC)
M20.3-P
N
INDEX
AREA
1
2
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
H
INCHES
E
3
L
SEATING PLANE
D
A
h x 45o
e
A1
B
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.092
0.105
2.34
2.67
-
A1
0.004
0.012
0.102
0.302
-
B
0.013
0.020
0.330
0.508
-
C
0.009
0.011
D
0.496
0.512
12.60
13.00
1
E
0.291
0.299
7.39
7.59
2
e
α
C
0.10(0.004)
0.25(0.010) M
0.050 BSC
0.229
0.401
0.411
h
0.010
0.029
0.254
L
0.016
0.050
0.41
α
10.18
20
0o
0.279
-
1.27 BSC
H
N
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate burrs.
2. Dimension “E” does not include interlead flash or protrusions.
3. “L” is the length of terminal for soldering to a substrate.
4. “N” is the number of terminal positions.
5. Terminal numbers are shown for reference only.
6. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
MILLIMETERS
-
10.44
-
0.737
-
1.27
3
20
8o
0o
4
8o
Rev. 0 5/96
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
15
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Similar pages