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INTERSIL o
Data
April 13, 2004
1-888-Sheet
ISL6504, ISL6504A
Multiple Linear Power Controller with
ACPI Control Interface
FN9062.2
Features
The ISL6504 and ISL6504A complement other power
building blocks (voltage regulators) in ACPI-compliant
designs for microprocessor and computer applications. The
IC integrates three linear controllers/regulators, switching,
monitoring and control functions into a 16-pin wide-body
SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A
operating mode (active outputs or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3VDUAL/3.3VSB
voltage plane from the ATX supply’s 5VSB output, powering
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3VDUAL/3.3VSB linear
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses.
A controller powers up the 5VDUAL plane by switching in the
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5VSB through a PMOS (or PNP)
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6504 5VDUAL output is shut down. In the ISL6504A, the
5VDUAL output stays on during S4/S5 sleep states. This is
the only difference between the two parts; see Table 1.
• Provides four ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
- 1.2VVID Processor VID Circuitry
- 1.5VSB ICH4 Resume Well
• Excellent Output Voltage Regulation
- All Outputs: 2.0% over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Near Chip Scale Package Footprint; Improved PCB
Efficiency; Thinner profile
• Pb-Free Available (RoHS Compliant)
Applications
• ACPI-Compliant Power Regulation for Motherboards
- ISL6504: 5VDUAL is shut down in S4/S5 sleep states
- ISL6504A: 5VDUAL stays on in S4/S5 sleep states
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element. Another internal regulator outputs a 1.5VSB
chip-set standby supply, which uses the 3V3DL pin as input
source for its internal pass element. The 3.3VDUAL/3.3VSB
and 1.5VSB outputs are active for as long as the ATX 5VSB
voltage is applied to the chip.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas LLC
Copyright © Intersil Americas LLC 2003, 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6504, ISL6504A
Pinouts
ISL6504/A (WIDE BODY SOIC)
TOP VIEW
16 5VSB
1
1V5SB
3V3DLSB 2
15 VID_CT
3V3DL 3
14 VID_PG
13 SS
1V2VID 4
12 5VDL
3V3 5
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
DWG. #
ISL6504CB
0 to 70
16 Ld SOIC
M16.3
ISL6504CBZ
(Note)
0 to 70
16 Ld SOIC
(Pb-free)
M16.3
S3
6
11 5VDLSB
ISL6504CBN
0 to 70
16 Ld SOIC
M16.15
S5
7
10 DLA
ISL6504CBNZ
(Note)
0 to 70
16 Ld SOIC
(Pb-free)
M16.15
ISL6504CR
0 to 70
20 Ld 6x6 QFN
L20.6x6
ISL6504CRZ
(Note)
0 to 70
20 Ld 6x6 QFN
(Pb-free)
L20.6x6
9
GND 8
FAULT
NOTE: SOIC layout should accomodate both wide and narrow footprints.
3V3DLSB
1V5SB
NC
5VSB
VID_CT
ISL6504/A (6X6 QFN)
TOP VIEW
20
19
18
17
16
ISL6504EVAL1
Evaluation Board
ISL6504ACB
0 to 70
16 Ld SOIC
M16.3
ISL6504ACBZ
(Note)
0 to 70
16 Ld SOIC
(Pb-free)
M16.3
3V3DL
1
15 VID_PG
ISL6504ACBN
0 to 70
16 Ld SOIC
M16.15
NC
2
14 SS
0 to 70
3
13 NC
16 Ld SOIC
(Pb-free)
M16.15
1V2VID
ISL6504ACBNZ
(Note)
ISL6504ACR
0 to 70
20 Ld 6x6 QFN
L20.6x6
3V3
4
12 5VDL
11 5VDLSB
20 Ld 6x6 QFN
(Pb-free)
L20.6x6
5
ISL6504ACRZ
(Note)
0 to 70
S3
10
DLA
9
FAULT
8
GND
7
S5
NC
6
NOTE: The QFN bottom pad is electrically connected to the IC substrate, at
GND potential. It can be left unconnected, or connected to GND; do NOT
connect to another potential.
2
ISL6504AEVAL1
Evaluation Board
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9062.2
April 13, 2004
Block Diagram
3V3DL
3V3DLSB
3V3
5VSB
DLA
5VDLSB
EA4
+
-
5VSB POR
4.4V/3.4V
3
3V3 MONITOR
TEMPERATURE
MONITOR
(TMON)
2.75V/2.60V
EA3
TO UV
DETECTOR
MONITOR AND CONTROL
TO 3V3
FAULT
TO
UV DETECTOR
UV DETECTOR
+
-
EA3
1V2VID
+
10mA
1.265V
-
+ -
UV COMP
+
-
VID_PG
+
4.10V
5VDL
10mA
-
GND
SS
S3
S5
VID_CT
FN9062.2
April 13, 2004
FIGURE 1.
ISL6504, ISL6504A
1V5SB
+
-
ISL6504, ISL6504A
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
1.5VSB
LINEAR
REGULATOR
1.5V
1.2VVID
LINEAR
REGULATOR
1.2V
Q2
LINEAR
CONTROLLER
Q3
3.3VDUAL /3.3VSB
VID_PG
Q4
3.3V
FAULT
Q5
CONTROL
ISL6504/A
5VDUAL
LOGIC
5V
SHUTDOWN
SX
2
FIGURE 2.
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
5VSB
3V3
VOUT1
1V5SB
1.5VSB
VOUT2
1V2VID
COUT1
1.2VVID
RDLA
VID_CT
CCT_VID
3V3DLSB
Q1
Q2
VOUT3
COUT2
VID_PG
3V3DL
3.3VDUAL/3.3VSB
VID PGOOD
ISL6504/A
COUT3
Q3
5VDLSB
FAULT
FAULT
DLA
S3
SLP_S3
Q4
S5
SLP_S5
VOUT4
5VDL
SS
COUT4
5VDUAL
CSS
SHUTDOWN
GND
FIGURE 3.
4
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V
ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV
Thermal Resistance (Typical)
JA (oC/W) JC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . .
70
N/A
QFN Package (Note 2) . . . . . . . . . . . .
32
4.0
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. JC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
17
-
mA
-
4
-
mA
Rising 5VSB POR Threshold
-
-
4.5
V
5VSB POR Hysteresis
-
0.9
-
V
Rising 3V3 Threshold
-
2.75
-
V
3V3 Hysteresis
-
150
-
mV
Falling Threshold Timeout (All Monitors)
-
10
-
s
VCC SUPPLY CURRENT
Nominal Supply Current
I5VSB
Shutdown Supply Current
I5VSB(OFF)
VSS = 0.8V
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
Soft-Start Current
ISS
-
10
-
A
Shutdown Voltage Threshold
VSD
-
-
0.8
V
VID_PG Rising Threshold
-
1.02
-
V
VID_PG Hysteresis
-
56
-
mV
-
-
2.0
%
-
1.5
-
V
1V5SB Undervoltage Rising Threshold
-
1.25
-
V
1V5SB Undervoltage Hysteresis
-
75
-
mV
85
-
-
mA
-
-
2.0
%
-
1.2
-
V
1V2VID Undervoltage Rising Threshold
-
0.96
-
V
1V2VID Undervoltage Hysteresis
-
60
-
mV
40
-
-
mA
1.5VSB LINEAR REGULATOR (VOUT1)
Regulation
1V5SB Nominal Voltage Level
V1V5SB
1V5SB Output Current
I1V5SB
V3V3DL = 3.3V
1.2VVID LINEAR REGULATOR (VOUT2)
Regulation
1V2VID Nominal Voltage Level
V1V2VID
1V2VID Output Current
I1V2VID
5
V3V3 = 3.3V
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
2.0
%
-
3.3
-
V
3V3DL Undervoltage Rising Threshold
-
2.75
-
V
3V3DL Undervoltage Hysteresis
-
150
-
mV
5
8
-
mA
5VDL Undervoltage Rising Threshold
-
4.10
-
V
5VDL Undervoltage Hysteresis
-
200
-
mV
-20
-
-40
mA
20
25
30
ms
-
200
-
s
-
10
-
A
High Level Input Threshold
-
-
2.2
V
Low Level Input Threshold
0.8
-
-
V
-
50
-
k
-
100
-

125
-
-
oC
-
155
-
oC
3.3VDUAL/3.3VSB LINEAR REGULATOR (VOUT3)
Sleep State Regulation
3V3DL Nominal Voltage Level
V3V3DL
3V3DLSB Output Drive Current
I3V3DLSB
V5VSB = 5V
5VDUAL SWITCH CONTROLLER (VOUT4)
5VDLSB Output Drive Current
I5VDLSB
V5VDLSB = 4V, V5VSB = 5V
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 3)
Active-to-Sleep Control Input Delay
VID_CT Charging Current
IVID_CT
VVID_CT = 0V
CONTROL I/O (S3, S5, FAULT)
S3, S5 Internal Pull-up Impedance to 5VSB
FAULT Output Impedance
FAULT = high
TEMPERATURE MONITOR
Fault-Level Threshold (Note 4)
Shutdown-Level Threshold (Note 4)
NOTES:
3. Guaranteed by Correlation.
4. Guaranteed by Design.
6
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Functional Pin Description (SOIC pinout)
3V3 (Pin 5)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 1V2VID pin, and is monitored for
power quality.
DLA (Pin 10)
This pin is an open-collector output. Connect a 1k resistor
from this pin to the ATX 12V output. This resistor is used to
pull the gates of suitable N-MOSFETs to 12V, which in active
state, switch in the ATX 3.3V and 5V outputs into the
3.3VDUAL/3.3VSB and 5VDUAL outputs, respectively.
5VSB (Pin 16)
5VDL (Pin 12)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides all the chip’s bias as well as the base current for Q2
(see typical application diagram). The voltage at this pin is
monitored for power-on reset (POR) purposes.
Connect this pin to the 5VDUAL output (VOUT4). In either
operating state (when on), the voltage at this pin is provided
through a fully-on MOS transistor. This pin is also monitored
for undervoltage events.
5VDLSB (Pin 11)
GND (Pin 8)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
S3 and S5 (Pins 6 and 7)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50k (typical) resistor pull-ups to
5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2s (typically). Additional
circuitry blocks any illegal state transitions (such as S3 to
S4/S5 or vice versa). Respectively, connect S3 and S5 to the
computer system’s SLP_S3 and SLP_S5 signals.
Connect this pin to the gate of a suitable P-MOSFET or
bipolar PNP. ISL6504: In S3 sleep state, this transistor is
switched on, connecting the ATX 5VSB output to the 5VDUAL
regulator output. ISL6504A: In S3 and S4/S5 sleep state,
this transistor is switched on, connecting the ATX 5VSB
output to the 5VDUAL regulator output.
1V5SB (Pin 1)
This pin is the output of the internal 1.5V regulator (VOUT1).
This internal regulator operates for as long as 5VSB is
applied to the IC and draws its output current from the
3V3DL pin. This pin is monitored for undervoltage events.
1V2VID (Pin 4)
FAULT (Pin 9)
In case of an undervoltage on any of the controlled outputs,
on any of the monitored ATX voltages, or in case of an
overtemperature event, this pin is used to report the fault
condition by being pulled to 5VSB. Connect a 1k resistor
from this pin to GND.
This pin is the output of the internal 1.2V voltage
identification (VID) regulator (VOUT2). This internal regulator
operates only in active states (S0, S1/S2) and is shut off
during any sleep state. This regulator draws its output
current from the 3V3 pin. This pin is monitored for
undervoltage events.
SS (Pin 13)
VID_PG (Pin 14)
Connect this pin to a small ceramic capacitor (no less than
5nF; 0.1F recommended). The internal soft-start (SS)
current source along with the external capacitor creates a
voltage ramp used to control the ramp-up of the output
voltages. Pulling this pin low with an open-drain device shuts
down all the outputs as well as force the FAULT pin low. The
CSS capacitor is also used to provide a controlled voltage
slew rate during active-to-sleep transitions on the
3.3VDUAL/3.3VSB output.
This pin is the open collector output of the 1V2VID power
good comparator. Connect a 10kpull-up resistor from this
pin to the 1V2VID output. As long as the 1V2VID output is
below its UV threshold, this pin is pulled low.
3V3DL (Pin 3)
Description
Connect this pin to the 3.3V dual/stand-by output (VOUT3).
In sleep states, the voltage at this pin is regulated to 3.3V; in
active states, ATX 3.3V output is delivered to this node
through a fully-on N-MOS transistor. During all operating
states, this pin is monitored for undervoltage events. This pin
provides all the output current delivered by the 1V5SB pin.
3V3DLSB (Pin 2)
Connect this pin to the base of a suitable NPN transistor. In
sleep state, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
7
VID_CT (Pin 15)
Connect a small capacitor from this pin to ground. The
capacitor is used to delay the VID_PG reporting the 1V2VID
has reached power good limits.
Operation
The ISL6504/A controls 4 output voltages (Refer to Figures
1, 2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of three linear
controllers/regulators supplying the computer system’s
1.5VSB (VOUT1), 3.3VSB and PCI slots’ 3.3VAUX power
(VOUT3), the 1.2V VID circuitry power (VOUT2), a dual
switch controller supplying the 5VDUAL voltage (VOUT4), as
FN9062.2
April 13, 2004
ISL6504, ISL6504A
well as all the control and monitoring functions necessary for
complete ACPI implementation.
Initialization
The ISL6504/A automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating
3.3VDUAL/3.3VSB and 1.5VSB soft-start operation shortly
after exceeding POR threshold.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
3.3VDUAL/SB and 5VDUAL outputs. The last two lines
highlight the only difference between the ISL6504 and
ISL6504A. The internal circuitry does not allow the transition
from an S3 (suspend to RAM) state to an S4/S5 (suspend to
disk/soft off) state or vice versa. The only ‘legal’ transitions
are from an active state (S0, S1) to a sleep state (S3, S5)
and vice versa.
5VSB
S3
S5
3.3V, 5V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 4. 5VDUAL AND 3.3VDUAL/3.3VSB TIMING
DIAGRAM; ISL6504
TABLE 1. 5VDUAL OUTPUT (VOUT4) TRUTH TABLE
S5
S3
3.3VDL/SB
5VDL
COMMENTS
1
1
3.3V
5V
S0/S1/S2 States (Active)
1
0
3.3V
5V
S3
0
1
0
0
3.3V
0V
S4/S5 (ISL6504)
0
0
3.3V
5V
S4/S5 (ISL6504A)
Note
5VSB
S3
Maintains Previous State
NOTE: Combination Not Allowed.
Functional Timing Diagrams
Figures 4 (ISL6504), 5 (ISL6504A), and 6 are timing diagrams,
detailing the power up/down sequences of all the outputs in
response to the status of the sleep-state pins (S3, S5), as well
as the status of the input ATX supply. Not shown in these
diagrams is the deglitching feature used to protect against false
sleep state tripping. Both S3 and S5 pins are protected against
noise by a 2s filter (typically 1–4s). This feature is useful in
noisy computer environments if the control signals have to
travel over significant distances. Additionally, the S3 pin
features a 200s delay in transitioning to sleep states. Once the
S3 pin goes low, an internal timer is activated. At the end of
the 200s interval, if the S5 pin is low, the ISL6504/A
switches into S5 sleep state; if the S5 pin is high, the
ISL6504/A goes into S3 sleep state.
S5
3.3V, 5V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 5. 5VDUAL AND 3.3VDUAL/3.3VSB TIMING
DIAGRAM; ISL6504A
5VSB
S3
S5
3.3V,
5V, 12V
DLA
1V5SB
1V2VID
FIGURE 6. 1.5VSB, AND 1.2VVID TIMING DIAGRAM
8
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Soft-Start into Sleep States (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10A current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
Figures 7 (ISL6504) and 8 (ISL6504A) show the soft-start
sequence for the typical application start-up into a sleep
state. At time T0 5VSB (bias) is applied to the circuit. At time
T1, the 5VSB surpasses POR level. An internal fast charge
circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10A current source continues
the charging.
5VSB
(1V/DIV)
SOFT-START
(1V/DIV)
0V
VOUT4 (5VDUAL)
VOUT3 (3.3VDUAL/3.3VSB)
OUTPUT
VOLTAGES
(1V/DIV)
VOUT1 (1.5VSB)
VOUT2
(1.2VVID)
0V
5VSB
(1V/DIV)
T0
SOFT-START
(1V/DIV)
T1 T2
T4
T3
T5
TIME
FIGURE 8. SOFT-START INTERVAL IN A SLEEP
STATE; ISL6054A
0V
VOUT4 (5VDUAL) IF S3
VOUT3 (3.3VDUAL/3.3VSB)
OUTPUT
VOLTAGES
(1V/DIV)
VOUT1 (1.5VSB)
VOUT2
(1.2VVID)
0V
VOUT4 (5VDUAL) if S5
T0
T1 T2
T3
T4
T5
TIME
FIGURE 7. SOFT-START INTERVAL IN A SLEEP
STATE; ISL6504
The soft-start capacitor voltage reaches approximately
1.25V at time T2, at which point the 3.3VDUAL/3.3VSB and
1.5VSB error amplifiers’ reference inputs start their
transition, resulting in the output voltages ramping up
proportionally. The ramp-up continues until time T3 when the
two voltages reach the set value. As the soft-start capacitor
voltage reaches approximately 2.75V, the undervoltage
monitoring circuit of this output is activated and the soft-start
capacitor is quickly discharged to approximately 1.25V.
Following the 3ms (typical) time-out between T3 and T4, the
soft-start capacitor commences a second ramp-up designed
to smoothly bring up the remainder of the voltages required
by the system. At time T5, voltages are within regulation
limits, and as the SS voltage reaches 2.75V, all the
remaining UV monitors are activated and the SS capacitor is
quickly discharged to 1.25V, where it remains until the next
transition. As the 1.2VVID output is only active while in an
active state, it does not come up, but rather waits until the
main ATX outputs come up within regulation limits.
Soft-Start into Active States (S0, S1)
If both S3 and S5 are logic high at the time the 5VSB is
applied, the ISL6504/A will assume active state wake-up and
keep off the required outputs until some time (typically 25ms)
after the monitored main ATX output (3.3V) exceeds the set
threshold. This time-out feature is necessary in order to
ensure the main ATX outputs are stabilized. The time-out
also assures smooth transitions from sleep into active when
sleep states are being supported. 3.3VDUAL/3.3VSB and
1.5VSB outputs will come up right after bias voltage
surpasses POR level.
9
FN9062.2
April 13, 2004
ISL6504, ISL6504A
the maximum current rating of an integrated regulator
(output with pass regulator on chip) can lead to output
voltage drooping; if excessive, this droop can ultimately trip
the undervoltage detector and send a FAULT signal to the
computer system.
+12VIN
DLA PIN
(2V/DIV)
INPUT VOLTAGES
(2V/DIV)
+5VIN
+5VSB
+3.3VIN
SOFT-START
(1V/DIV)
0V
OUTPUT
VOLTAGES
(1V/DIV)
VOUT4 (5VDUAL)
VOUT3 (3.3VDUAL/3.3VSB)
VOUT1 (1.5VSB)
VOUT2 (1.2VVID)
0V
T0
T1
T2
T3
TIME
FIGURE 9. SOFT-START INTERVAL IN ACTIVE STATE
During sleep-to-active state transitions from conditions
where the 5VDUAL output is initially 0V (such as S5 to S0
transition, or simple power-up sequence directly into active
state), the circuit goes through a quasi soft-start, the 5VDUAL
output being pulled high through the body diode of the NChannel MOSFET connected between it and the 5V ATX.
Figure 9 exemplifies this start-up case. 5VSB is already
present when the main ATX outputs are turned on, at time
T0. As a result of +5VIN ramping up, the 5VDUAL output
capacitors charge up through the body diode of Q4 (see
Typical Application). At time T1, all main ATX outputs exceed
the ISL6504/A’s undervoltage thresholds, and the internal
25ms (typical) timer is initiated. At T2, the time-out initiates a
soft-start, and the 1.2V voltage ID output is ramped-up,
reaching regulation limits at time T3. Simultaneous with the
beginning of this ramp-up, at time T2, the DLA pin is
released, allowing the pull-up resistor to turn on Q2 and Q4,
and bring the 5VDUAL output in regulation. Shortly after time
T3, as the SS voltage reaches 2.75V, the soft-start capacitor
is quickly discharged down to approximately 2.45V, where it
remains until a valid sleep state request is received from the
system.
A FAULT condition occurring on an output when controlled
through an external pass transistor will only set off the
FAULT flag, and it will not shut off or latch off any part of the
circuit. A FAULT condition occurring on an output controlled
through an internal pass transistor, will set off the FAULT
flag, and it will shut off the respective faulting regulator only.
If shutdown or latch off of the entire circuit is desired in case
of a fault, regardless of the cause, this can be achieved by
externally pulling or latching the SS pin low. Pulling the SS
pin low will also force the FAULT pin to go low and reset any
internally latched-off output.
Special consideration is given to the initial start-up
sequence. If, following a 5VSB POR event, any of the
1.5VSB or 3.3VDUAL/3.3VSB outputs is ramped up and is
subject to an undervoltage event before the end of the
second soft-start ramp, then the FAULT output goes high
and the entire IC latches off. Latch-off condition can be reset
by cycling the bias power (5VSB). Undervoltage events on
the 1.5VSB and the 3.3VDUAL/3.3VSB outputs at any other
times are handled according to the description found in the
second paragraph under the current heading.
Another condition that could set off the FAULT flag is chip
overtemperature. If the ISL6504/A reaches an internal
temperature of 140oC (typical), the FAULT flag is set, but the
chip continues to operate until the temperature reaches
155oC (typical), when unconditional shutdown of all outputs
takes place. Operation resumes only after powering down
the IC (to create a 5VSB POR event) and a start-up
(assuming the cause of the fault has been removed; if not,
as it heats up again, it will repeat the FAULT cycle).
In ISL6504/A applications, loss of the active ATX output
(3.3VIN; as detected by the on-board voltage monitor) during
active state operation causes the chip to switch to S5 sleep
state, in addition to reporting the input UV condition on the
FAULT pin. Exiting from this forced S5 state can only be
achieved by returning the faulting input voltage above its UV
threshold, by resetting the chip through removal of 5VSB
bias voltage, or by bringing the SS pin at a potential lower
than 0.8V.
Application Guidelines
Fault Protection
Soft-Start Interval
All the outputs are monitored against undervoltage events. A
severe overcurrent caused by a failed load on any of the
outputs, would, in turn, cause that specific output to
suddenly drop. If any of the output voltages drops below
80% (typical) of their set value, such event is reported by
having the FAULT pin pulled to 5V. Additionally, exceeding
The 5VSB output of a typical ATX supply is capable of
725mA, with newer models rated for 1.0A, and even 2.0A.
During power-up in a sleep state, the 5VSB ATX output
needs to provide sufficient current to charge up all the
applicable output capacitors and, simultaneously, provide
some amount of current to the output loads. Drawing
10
FN9062.2
April 13, 2004
ISL6504, ISL6504A
excessive amounts of current from the 5VSB output of the
ATX can lead to voltage collapse and induce a pattern of
consecutive restarts with unknown effects on the system’s
behavior or health.
I SS
I COUT = ------------------------------    C OUT  V OUT  , where
C SS  V BG
ISS - soft-start current (typically 10A)
CSS - soft-start capacitor
60
50
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
10
VID_PG Delay (ms)
VBG - bandgap voltage (typically 1.26V)
COUT x VOUT) - sum of the products between the
capacitance and the voltage of an output (total charge
delivered to all outputs)
Due to the various system timing events and their
interaction, it is recommended that the soft-start interval not
be set to exceed 30ms. For most applications, a 0.1F
capacitor is recommended.
Shutdown
In case of a FAULT condition that might endanger the
computer system, or at any other time, all the ISL6504/A
outputs can be shut down by pulling the SS pin below the
specified shutdown level (typically 0.8V) with an open drain
or open collector device capable of sinking a minimum of
2mA. Pulling the SS pin low effectively shuts down all the
pass elements. Upon release of the SS pin, the ISL6504
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control pins
status.
VID_PG Delay
During power-up and initial soft-start, the VID_PG and
VID_CT pins are held low. As the 1V2VID output exceeds its
rising power-good threshold, the capacitor connected at the
VID_CT pin starts to charge up through the internal 10A
current source. As the voltage on this capacitor exceeds
1.25V, the open-collector VID_PG pin is released and VID
POWER GOOD status is thus reported.
The value of the VID_CT capacitor to be used to obtain a
given VID_PG delay can be determined from the graph in
Figure 10. For extended delays exceeding the range of the
graph, use the following formula:
t DELAY
C = -------------------125000
70
C (nF)
The built-in soft-start circuitry allows tight control of the slewup speed of the output voltages controlled by the ISL6504,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
current dedicated to charging the output capacitors can be
calculated with the following formula:
80
, where
tDELAY - desired delay time (s)
C - VID_CT capacitor to obtain desired delay time (F)
11
FIGURE 10. VID_PG DELAY DEPENDENCE ON VID_CT
CAPACITOR
Layout Considerations
The typical application employing an ISL6504/A is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
controller chip and processor, but not excessively far from
the 3.3VDUAL island or the I/O circuitry. Ensure the 1V5SB,
1V2VID, 3V3, and 3V3DL connections are properly sized to
carry 100mA without exhibiting significant resistive losses at
the load end. Similarly, the input bias supply (5VSB) can
carry a significant level of current - for best results, ensure it
is connected to its respective source through an adequately
sized trace. The pass transistors should be placed on pads
capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
Placement of the decoupling and bulk capacitors should
follow a placement reflecting their purpose. As such, the
high-frequency decoupling capacitors should be placed as
close as possible to the load they are decoupling; the ones
decoupling the controller close to the controller pins, the
ones decoupling the load close to the load connector or the
load itself (if embedded). Even though bulk capacitance
(aluminum electrolytics or tantalum capacitors) placement is
not as critical as the high-frequency capacitor placement,
having these capacitors close to the load they serve is
preferable.
The critical small signal components include the soft-start
capacitor, CSS, as well as all the high-frequency decoupling
capacitors. Locate these components close to the respective
FN9062.2
April 13, 2004
ISL6504, ISL6504A
pins of the control IC, and connect them to ground through a
via placed close to the ground pad. Minimize any leakage
current paths from the SS node, as the internal current
source is only 10A (typical).
+12VIN
Also, during the transition between active and sleep states
on the 3.3VDUAL/3.3VSB and 5VDUAL outputs, there is a
short interval of time during which none of the power pass
elements are conducting - during this time the output
capacitors have to supply all the output current. The output
voltage drop during this brief period of time can be easily
approximated with the following formula:
+5VSB
CIN
C5VSB
5VSB
SS
CSS
1V5SB
CBULK4
LOAD
VOUT1
3V3DLSB
CHF3
Q4
DLA
VOUT3
+5VIN
3V3
CBULK2
VOUT2
GND
CHF2
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 11. PRINTED CIRCUIT BOARD ISLANDS
A multi-layer printed circuit board is recommended.
Figure 11 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. Ideally, the power
plane should support both the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers to create power islands connecting the filtering
components (output capacitors) and the loads. Use the
remaining printed circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0, S1). The load transient for the
various microprocessor system’s components may require
12
VOUT - output voltage drop
IOUT - output current during transition
COUT - output capacitor bank capacitance
ISL6504/A
1V2VID
Q2
tt 

V OUT = I OUT   ESR OUT + ---------------- , where
C

OUT
ESROUT - output capacitor bank ESR
3V3DL
CBULK3
LOAD
CHF4
LOAD
CBULK1
Q1
VOUT4
5VDL
LOAD
CHF1
Q3
5VDLSB
high quality capacitors to supply the high slew rate (di/dt)
current demands. Thus, it is recommended that the output
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
tt - active-to-sleep or sleep-to-active transition time (10s typ.)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
Input Capacitors Selection
The input capacitors for an ISL6504/A application must have
a sufficiently low ESR so as not to allow the input voltage to
dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the ISL6504/A’s regulation levels could have as
a result a brisk transfer of energy from the input capacitors to
the supplied outputs. At the transition between active and
sleep states, such phenomena could be responsible for the
5VSB voltage drooping excessively and affecting the output
regulation. The solution to such a potential problem is using
larger input capacitors with a lower total combined ESR.
Transistor Selection/Considerations
The ISL6504/A usually requires one P-Channel (or bipolar
PNP), two N-Channel MOSFETs, and one bipolar NPN
transistors.
One important criteria for selection of transistors for all the
linear regulators/switching elements is package selection for
efficient removal of heat. The power dissipated in a linear
regulator or an ON/OFF switching element is
P LINEAR = I O   V IN – V OUT 
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Q1
Q3
The NPN transistor used as sleep state pass element on the
3.3VDUAL output has to have a minimum current gain of 100
at 1.5V VCE and 650mA ICE throughout the in-circuit
operating temperature range. For larger current ratings on
the 3.3VDUAL output (providing the ATX 5VSB output rating
is equally extended), selection criteria for Q1 include an
appropriate current gain (hfe) and saturation characteristics.
If a P-Channel MOSFET is used to switch the 5VSB output of
the ATX supply into the 5VDUAL output during sleep states,
then the selection criteria of this device is proper voltage
budgeting. The maximum rDS(ON) , however, has to be
achieved with only 4.5V of gate-to-source voltage, so a logic
level MOSFET needs to be selected. If a PNP device is
chosen to perform this function, it has to have a lowsaturation voltage while providing the maximum sleep
current and have a current gain sufficiently high to be
saturated using the minimum drive current (typically 20mA).
Q2, Q4
These N-Channel MOSFETs are used to switch the 3.3V
and 5V inputs provided by the ATX supply into the
3.3VDUAL/3.3VSB and 5VDUAL outputs while in active (S0,
S1) state. The main criteria for the selection of these
transistors is output voltage budgeting. The maximum
rDS(ON) allowed at highest junction temperature can be
expressed with the following equation:
ISL6504 Application Circuit
Figure 12 shows a typical application circuit for the
ISL6504/A. The circuit provides the 3.3VDUAL/3.3VSB
voltage, the ICH4 resume well 1.5VSB voltage, the 1.2VVID
voltage identification output, and the 5VDUAL
keyboard/mouse voltage from +3.3V, +5VSB, +5V, and
+12VDC ATX supply outputs. Q3 can also be a PNP
transistor, such as an MMBT2907AL. For additional, more
detailed information on the circuit, including a Bill-ofMaterials and circuit board description, see Application Note
AN1001. Also see Intersil Corporation’s web page
(www.intersil.com).
V INmin – V OUTmin
r DS  ON max = --------------------------------------------------- , where
I OUTmax
VINmin - minimum input voltage
VOUTmin - minimum output voltage allowed
IOUTmax - maximum output current
+5VIN
R1
+12VIN
1k
+3.3VIN
+5VSB
C1
1mF
5VSB
16
3V3
5
14
15
Q2
HUF76113T3S
+3.3VDUAL/3.3VSB
+
3V3DLSB
2
Q1
2SD1802
3V3DL
4
3
C4
330mF
VID_PG
‘VID PGOOD’
VID_CT
C2
0.1mF
R2
10k
+1.2VVID
1V2VID
C3 +
10mF
U1
ISL6504/A
‘FAULT’
FAULT
+1.5VSB
1V5SB
+
C5
10mF
9
11
10
S3
S5
S5
SS
C7
0.1mF
Q3
FDV304P
1
R3
1k
S3
5VDLSB
6
12
+5VDUAL
5VDL
+
7
13
Q4
HUF76113T3S
DLA
C6
220mF
8
GND
FIGURE 12. TYPICAL ISL6504/A APPLICATION DIAGRAM
13
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
INDEX
AREA
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
0.25(0.010) M
H
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
µ
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N

NOTES:
MILLIMETERS
16
0o
16
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
14
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.6x6
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
b
0.20 REF
0.28
D
0.40
5, 8
6.00 BSC
D1
D2
0.33
9
-
5.75 BSC
3.55
3.70
9
3.85
7, 8
E
6.00 BSC
-
E1
5.75 BSC
9
E2
3.55
e
3.70
3.85
7, 8
0.80 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
20
2
Nd
5
3
Ne
5
3
P
-
-
0.60
9

-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
15
FN9062.2
April 13, 2004
ISL6504, ISL6504A
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Small Outline Plastic Packages (SOIC)
N
INCHES
INDEX
AREA
H
0.25(0.010) M
B M
SYMBOL
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
B
0.014
0.019
0.35
0.49
9
C
0.007
0.010
0.19
0.25
-
D
0.386
0.394
9.80
10.00
3
E
0.150
0.157
3.80
4.00
4
e
µ
A1
MIN
0.050 BSC
1.27 BSC
-
H
0.228
0.244
5.80
6.20
-
h
0.010
0.020
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N

16
0o
16
7
8o
Rev. 1 02/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN9062.2
April 13, 2004
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