an1055

Embedded ACPI Compliant DDR Power
Generation Using the ISL6532
®
Application Note
October 2003
AN1055
Author: Douglas Mattingly
Introduction
Recommended Test Equipment
The ISL6532 provides a complete ACPI compliant power
solution for dual channel DDRI and DDRII Memory systems.
Included are both a synchronous buck controller and
integrated LDO to supply VDDQ with high current during
S0/S1 (Run) states and standby current during S3
(Suspend-To-RAM = STR) state. During Run mode, a fully
integrated sink-source regulator generates an accurate
(VDDQ/2) high current VTT voltage. A buffered version of
the VDDQ/2 reference is provided as VREF.
To test the full functionality of the ISL6532, the following
equipment is recommended:
• An ATX power supply
• Two electronic loads
• Four channel oscilloscope with probes
• Precision digital multimeters
The ISL6532 contains high performance error amplifiers, a
high accuracy reference, an internal 50% tracking reference,
a fixed 250kHz internal oscillator and Power Good
indication. All these features are packaged in a 20-Lead
6x6mm QFN. A more complete description of the IC can be
found in the datasheet[1].
If individual power supplies are to be utilized in place of the
ATX power supply, then the 5V power supply should be
capable of producing 15A of continuous current. The supply
for the 5VSBY rail should be capable of producing up to 1A.
A single 5V supply may be used for both VCC5 and 5VSBY.
The 12V supply should be capable of producing at least 1A
of continuous current.
Reference Design
Power and Load Connections
The ISL6532EVAL1 is an evaluation board that highlights
the operation of the ISL6532 in an embedded DDR DRAM
Memory Power application. The VDDQ supply has been
designed to supply 2.5V with a designed load capacity of
20A. This load capacity is based on the characteristics of the
MOSFETs as there is no overcurrent protection on the
VDDQ supply. The VTT termination supply will track the
VDDQ supply at 50% while sourcing or sinking current. The
schematic, Bill of Materials, and Board Layouts for the
ISL6532EVAL1 can be found in the Appendix.
Input Voltages
Quick Start Evaluation
The ISL6532EVAL1 board is shipped ‘ready to use’ right
from the box. The ISL6532EVAL1 supports testing with
standard laboratory equipment or with an ATX power supply.
Both outputs can be exercised through external loads. Both
the VDDQ and VTT regulators have the ability to source or
sink current.
There are auxiliary posts available on the board for
introducing power to the board if an ATX supply is not
available. If an ATX supply is used, these posts may be used
to monitor the voltages supplied by the ATX supply. There
are also posts available on each regulated output rail for
drawing a load and/or monitoring the voltages. Eight
individually labeled probe points are also available for use.
These probe points provide Kelvin connections to signals
which may be of interest to the designer.
Three switches have been placed on the board to
accommodate ACPI signal simulation. The ATX switch will
enable or disable the ATX power supply, while the other two
switches will send S5 or S3 signals to the ISL6532.
1
Simply plug the 20 pin connector from the ATX power supply
into the 20 pin receptacle, J1, on the evaluation board. If
laboratory supplies are to be used, then connect the 5V
supplies to the VCC5 and 5VSBY posts. Connect the 12V
supply to the 12V post. Connect the ground leads of all
supplies to the corresponding GND post directly to the left of
each supply post.
Loading VDDQ
Connect the positive terminal of the first electronic load to
the VDDQ post. Connect the return terminal of the same
load to the corresponding GND post.
Loading VTT - Sourcing Current
To test VTT while the regulator sources current, connect the
positive terminal of the second electronic load to the VTT
post. Connect the return terminal of the same load to the
corresponding GND post.
Loading VTT - Sinking Current
To test VTT while the regulator sinks current, connect the
positive terminal of the second electronic load to the VDDQ
post. Connect the return terminal of the same load to the
VTT post.
CAUTION: The return terminal of the load must float for
this to work properly.
Power Up and State Transitions
There are several distinct state transitions that the ISL6532
supports. These include a Cold/Mechanical Start (S5 to S0
state transition), Active to Sleep (S0 to S3 transition), Sleep
to Active (S3 to S0 transition) and finally Active to Shutdown
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Application Note 1055
(S0 to S5 transition). Table 1 shows the switch positions and
the corresponding ACPI states.
S3
TABLE 1. ISL6532EVAL1 STATES
5VATX
ATX
S3
S5
STATE
On
Active
Active
Active (S0)
On
S3
Active
Sleep (S3)
On
Active
S5
Shutdown (S5)
12VATX
VDDQ
VTT
If the ATX switch toggled to OFF while the system is in either
Active of Sleep state, the ISL6532 will revert to an S3
(Sleep) state. When either the S3 or S5 switch is toggled
from ACTIVE to the corresponding sleep state, there is
circuitry on the evaluation board that will force the ATX
supply OFF.
PGOOD
2ms/DIV
VDDQ @ 1V/DIV
5VATX @ 1V/DIV
VTT @ 1V/DIV
12VATX @ 3V/DIV
PGOOD @ 5V/DIV
Initial Power Up - Cold Start
There are two ways to initiate a Cold Start on the
ISL6532EVAL1. Prior to applying power to the ATX supply,
the S5 and S3 switch toggles should be pointing to “ACTIVE”
while the ATX switch toggle is pointing to “OFF”. After
applying power to the ATX supply, the ISL6532 can be Cold
Started be engaging the ATX switch to “ON”. The second
method requires the system to be in Shutdown state, with
the ATX switch “ON”, the S3 switch “ACTIVE” and the S5
switch in “S5”. After engaging the S5 switch to “ACTIVE”, the
system will Cold Start. Figure 1 shows a Cold Start.
FIGURE 2. ACTIVE TO SLEEP TRANSITION
Sleep to Active State Transition
Figure 3 shows the transition from Sleep to Active State.
S3
5VATX
12VATX
VDDQ
S5
S3
VTT
5VSBY
12VATX
VDDQ
5VATX
VTT
PGOOD
PGOOD
5ms/DIV
VDDQ @ 1V/DIV
5VATX @ 1V/DIV
12VATX @ 3V/DIV
VTT @ 1V/DIV
PGOOD @ 5V/DIV
FIGURE 3. SLEEP TO ACTIVE TRANSITION
5VSBY @ 1V/DIV
5VATX @ 1V/DIV
12VATX @ 3V/DIV
VDDQ @ 1V/DIV
VTT @ 1V/DIV
PGOOD @ 5V/DIV
FIGURE 1. COLD/MECHANICAL START
Refer to Table 1 for proper switch positions to achieve this
state transition. Once the PGOOD signal has been asserted,
the VDDQ rail can then be loaded beyond the S3 load
limitations of the standby LDO.
Active to Sleep State Transition
Shutdown to Active State Transition
Figure 2 shows the transition from Active to Sleep. Refer to
Table 1 for proper switch positions to achieve this state
transition. When transitioning from Active State to Sleep
State, it is important that the load on the VDDQ rail be
reduced to levels that the standby LDO is capable of
supporting. If the load on VDDQ is excessive, VDDQ voltage
will collapse.
Figure 4 shows the transition from Shutdown to Active. Refer
to Table 1 for proper switch positions to achieve this state
transition.
2
VDDQ Ripple Voltage
Figure 5 shows the ripple voltage on the VDDQ output.
Application Note 1055
VDDQ
50mV/DIV
S5
2.480V
5VATX
VTT
50mV/DIV
12VATX
VDDQ
1.230V
VTT
VDDQ Load
10A/DIV
PGOOD
200µs/DIV
10ms/DIV
FIGURE 6. TRANSIENT ON VDDQ
VDDQ @ 1V/DIV
VTT @ 1V/DIV
5VATX @ 1V/DIV
12VATX @ 3V/DIV
PGOOD @ 5V/DIV
FIGURE 4. SHUTDOWN TO ACTIVE TRANSITION
VDDQ
10mV/DIV
2.480V
VDDQ
1.230V
VTT
10mV/DIV
10mV/DIV
VTT Load
1A/DIV
200µs/DIV
FIGURE 7. SOURCING TRANSIENT ON VTT
2µs/DIV
FIGURE 5. VDDQ RIPPLE VOLTAGE
VDDQ
50mV/DIV
Transient Performance
Figures 6 through 10 show the response of the outputs when
subjected to a variety of transient loads while in the Active
(S0) State. Figure 6 shows VDDQ under transient loading.
Figure 7 shows VTT under a transient loading that causes
VTT to source current. Figure 8 shows VTT under a transient
that causes VTT to sink current. Figure 9 shows both VDDQ
and VTT under simultaneous transient loading. Finally,
Figure 10 shows the 1.5V AGP rail under transient loading.
2.480V
VTT
20mV/DIV
1.230V
VTT Load
1A/DIV
500µs/DIV
FIGURE 8. SINKING TRANSIENT ON VTT
3
Application Note 1055
ISL6532EVAL1 Customization
There are numerous ways in which a designer might modify
the ISL6532EVAL1 evaluation board for differing
requirements. Some of the changes which are possible
include:
VDDQ
50mV/DIV
2.480V
VTT
50mV/DIV
• The input and output inductors, L1 and L2
1.230V
• The input and output capacitance for any of the three
regulators.
• By changing the value of C19, the soft start profile of the
VTT rail, when transitioning from Sleep to Active State
VDDQ Load
10A/DIV
VTT Load
2A/DIV
• All MOSFET footprints on the evaluation board allow for
either SO8 or PowerPak packaged MOSFETs to be
utilized
200µs/DIV
FIGURE 9. SOURCING TRANSIENTS ON VDDQ AND VTT
Efficiency
Figure 10 shows the efficiency of the VDDQ regulator while
in Active (S0) State. As the other regulated outputs are all
derived through linear regulation, their efficiencies are not
shown.
96%
• The 3.3VSBY LDO, Ux1, may be circumvented by
shorting pins 2 and 3 together. This will provide the VDDQ
standby LDO with 5V while in Sleep state, which allows
the load to be increased by 100mA.
Conclusion
The ISL6532EVAL1 is a versatile platform that allows
designers to gain a full understanding of the functionality of
the ISL6532 in a DDR Memory System. The board is also
flexible enough to allow the designer to modify the board for
differing requirements.
94%
References
92%
For Intersil documents available on the web, see
http://www.intersil.com/
90%
[1] ISL6532 Data Sheet, Intersil Corporation, File No.
FN9112.
88%
86%
84%
82%
0
5
10
15
LO A D C UR R E N T [ A ]
FIGURE 10. VDDQ EFFICIENCY
4
20
Application Note 1055
ISL6532EVAL1 Schematic
J1
ATX
SWITCH
PSON
S3#
S5#
14
4
6
19
20
ATX CONNECTOR
3
5 15
7 16
13 17
10
9
GND
+5VIN
+12VIN
+5VSB
VCC5
5VSBY
VREF
S5#
SLP_S5#
S3#
SLP_S3#
C4,5
1µF
VREF_OUT
UGATE
C19
0.47µF
2.5V
ISL6532
Q2,4
+ C6-8
1800µF
VDDQ
VDDQ
VTT
VTT
+
C1-3
2200µF
VDDQ
L2
2.1µH
LGATE
C20 +
220µF
+
Q1,3
VREF_IN
VDDQ
R4
1.74kΩ
C21
220µF
FB
GND
VTT_SENSE
GND
1.25V
L1
2.1µH
NCH
C26
0.1µF
C27
0.1µF
VTT
Q5
C16
1µF
P12V
PGOOD
VDDQ
R1
1.74kΩ
P5VSBY
PGOOD
VCC12
C18
1µF
5VSBY
R2
10.0kΩ
C17
1µF
3V3SBY
COMP
C15
1000pF
C14
R3
6.8nF 19.1kΩ
C13
56nF
R5
22.6Ω
R6
825Ω
5VSBY
S3#
3V3SBY
3.3V SBY LDO
SIGNAL CONDITIONING
S5#
S3
S5
SWITCH SWITCH
5
C9-12
22µF
Application Note 1055
ISL6532EVAL1 Bill of Material
REF DES
C4, 5, 16-18
DESCRIPTION
PKG
VENDOR
VENDOR P/N
QTY
-
5
1µF, X5R Capacitor
0603
Various
C1, 2, 3
2200µF 6.3V MBZ Capacitor
10x20
Rubycon
6.3MBZ2200M10X20
3
C6, 7, 8
1800µF 16V MBZ Capacitor
10x23
Rubycon
16MBZ1800M10X23
2
C20, 21
220µF, 25V
8x11.5
Panasonic
EEU-FCIE221
3
C9-12
22µF Capacitor
1206
Various
-
4
C13
56nF Capacitor
0603
Vishay
VJ0603Y563KXXA
1
C14
6.8nF Capacitor
0603
Vishay
VJ0603Y682KXBA
1
C15
1000pF Capacitor
0603
Vishay
VJ0603Y102KXB
1
C19
0.047µF, 10V, X5R MLC Capacitor
0603
TDK
C1608X5R1A474K
1
0.1µF Capacitor
0603
Vishay
VJ0603Y104KXXA
2
-
CoEv
C9616
2
C26, 27
L1, 2
2.1µH, 7T 14AWG on T50-52B Core
Q1-4
30V N-Channel MOSFET
PowerPak
Vishay
Si7840DP
4
Q5
30V N-Channel MOSFET
DPAK
Vishay
SUD50N03-07
1
R1, 4
1.74kΩ, 1% Resistor
0603
Vishay
CRCW06031741F
1
R2
10.0kΩ, 1% Resistor
0603
Vishay
CRCW06031002F
1
R3
19.1kΩ, 1% Resistor
0603
Vishay
CRCW06031912F
1
R5
22.6Ω, 1% Resistor
0603
Vishay
CRCW060322R6F
1
R6
825Ω, 1% Resistor
0603
Vishay
CRCW0603825RF
1
U1
ACPI Compliant DDR Power Regulator
20ld 6x6mm
QFN
Intersil
ISL6532CR
1
ISL6532EVAL1 Layout
FIGURE 11. TOP SILK SCREEN
6
Application Note 1055
ISL6532EVAL1 Layout (Continued)
FIGURE 12. TOP
FIGURE 13. INTERNAL 1 GROUND
7
Application Note 1055
ISL6532EVAL1 Layout (Continued)
FIGURE 14. INTERNAL 2 POWER
FIGURE 15. BOTTOM
8
Application Note 1055
ISL6532EVAL1 Layout (Continued)
FIGURE 16. BOTTOM SILK SCREEN
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