an1077

ISL6244EVAL1 Multi-phase Evaluation Board
Setup Procedure
1. Refer to our website for updated information, the ISL6207 data
sheet, and the ISL6244 data sheet: www.intersil.com.
1
PART NUMBER TEMP. (oC)
PACKAGE
PKG. DWG. #
ISL6244CR
0 to 70
32 Ld QFN
L32.5X5
ISL6244CRZ
0 to 70
32 Lead-Free QFN
L32.5X5
ISL6244HR
-10 to 100 32 Ld QFN
L32.5X5
ISL6244HRZ
-10 to 100 32 Lead-Free QFN
L32.5X5
NOTE: Add “-T” suffix for 32 QFN 5x5 Tape and Reel packages.
Pinout
GND
EN
FS
PGOOD
ISL6244CR
(32 LEAD QFN 5X5)
TOP VIEW
32
31
30
29
28
27
26
25
24 PWM4
VID1
2
23 ISEN4
VID0
3
22 ISEN1
NC
4
21 PWM1
OFS
5
20 PWM2
COMP
6
19 GND
FB
7
18 ISEN2
NC
8
17 ISEN3
9
10
11
12
13
14
15
16
PWM3
1
VCC
VID2
GND
The Intersil multi-phase family driver portfolio continues to
expand with new selections to better fit our customer’s
needs.
Ordering Information
GND
The ISL6207 driver is chosen to drive two N-Channel power
MOSFETs in a synchronous-rectified buck converter
channel. Each channel has a single logic input which
controls the upper and lower MOSFETs. Dead time is
optimized on both switching edges to provide shoot-thru
protection. Internal bootstrap circuitry only requires an
external capacitor and provides better enhancement of the
upper MOSFET. For a more detailed description of the
ISL6207, refer to the data sheet [1].
• Excellent Dynamic Response
- Combined Input Voltage Feed-Forward and Pulse-byPulse Average Current Mode
VFF
The ISL6244 regulates output voltage and balances load
currents for two to four synchronous buck converter
channels. The controller features a 5-bit DAC which provides
a digital interface for accurate step down conversion over
the entire Hammer Family range of 0.800V to 1.550V. New
multi-phase family features include differential remote output
voltage sensing to improve regulation tolerance, pinadjustable reference offset for ease of implementation, VIDon-the-Fly to respond to DAC changes during operation, and
optional load line regulation. For a more detailed description
of the ISL6244 functionality, refer to the data sheet [1].
• Programmable Droop Voltage
RGND
The ISL6244EVAL1 Rev B is a versatile voltage regulatordown (VRD) design. The evaluation board comes configured
for 3-phase multi-phase buck operation, designed to meet
AMD Hammer Family Desktop Processor specifications. The
board layout supports removal or addition of the third and
fourth phases to support multiple applications. The ISL6244
controller features are specifically designed to compliment
and support the Hammer Family processors. Interfaced with
ISL6207 drivers, the chipset forms a highly integrated
solution for AMD Hammer processor applications.
• Precision CORE Voltage Regulation
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
- ± 1% System Accuracy
VID4
Intersil ISL6244 and ISL6207
• Precision rDS(ON) Current Sharing
- Lossless
- Low Cost
VSEN
The AMD Hammer family microprocessors feature higher
clock speeds and greater device density than previous
product families. The power management solution for this
next generation family of microprocessors must contend with
lower core voltages, tighter transient specifications, and
higher peak current demands. Responding to the changing
power management needs of its customers, Intersil
introduces the ISL6244 controller to power the AMD
Hammer family microprocessors.
• Multi-Phase Power Conversion
- 2, 3 or 4 Phase Operation
NC
Description
AN1077
Features
VDIFF
This document describes the setup procedure for the
ISL6244EVAL1 Rev B board for AMD Mobile K8 Processors.
September 2003
VID3
Application Note
IOUT
®
NC = NO CONNECT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1077
What’s Inside
Step 5:
Set the 0-12V power supply to +12V and place in
the “STANDBY” or “OFF” position. Connect the
positive terminal (+) of the supply to the +12V
terminal J6 and the negative terminal (-) of the
supply to GND J8.
Step 6:
Connect the positive terminal (+) of a DMM to the
+5V terminal J5 and the negative terminal (-) to the
GND terminal J7.
Step 7:
Connect the positive terminal (+) of the electronic
load to the VOUT terminal J1. Connect the
negative terminal (-) of the electronic load to the
GND terminal J2. Make sure the electronic load is
set to the 0A condition.
Step 8:
Connect the positive terminal (+) of a DMM to the
VOUT test point TP13 and the negative terminal (-)
to the GND test point TP14.
Step 9:
Check to ensure all jumpers and switches are in
their default positions prior to application of power
(refer to“Detailed Description of Jumper Settings”
and “Detailed Description of Switch Settings” ).
Step 10:
Set all power supplies to the “ON” position. LED
CR1 should show Red. Check all DMM displays for
correct voltage levels. Adjust if necessary.
Step 11:
Turn the ENABLE switch SW2 to the “ON” position.
LED CR1 should show Green. The VOUT DMM
should read 1.60V (±1%).
The Evaluation Board Kit contains the following materials:
• The ISL6244 EVAL Board
• The ISL6244 Evaluation Board document
What is Needed
The following materials will be needed to perform testing:
• 1 to 2 electronic loads [see note]
– 0-25V @ 15A (+VDC)
– 0-5V @ 5A (+5V)
– 0-12V @ 1A (+12V)
• precision digital multi-meters
NOTE: amperage rating of power supplies are determined by
maximum expected loading plus a percentage margin of error
Quick Setup Guide
Step 1:
Set the 0-5V power supply to +5V and place in the
“STANDBY” or “OFF” position. Connect the
positive terminal (+) of the supply to the +5V
terminal J5 and the negative terminal (-) of the
supply to GND J7.
Step 2:
Connect the positive terminal (+) of a DMM to the
+5V terminal J5 and the negative terminal (-) to the
GND terminal J7.
Step 3:
Set the +VDC power supply to +19V and place in
the “STANDBY” or “OFF” position. Connect the
positive terminal (+) of the supply to the +VDC
terminal J3 and the negative terminal (-) of the
supply to GND J4.Connect the load
Step 4:
Connect the positive terminal (+) of a DMM to the
+VDC terminal J3 and the negative terminal (-) to
the GND terminal J4.
At this point the board has been properly powered up.
Normal testing can begin.
NOTE: If you need technical assistance, or other assistance, with
the ISL6244 Evaluation Board, call 1-888-INTERSIL (468-3774).
Detailed Description of Jumper Settings
JUMPER
POSITION
JP1
Shunted
FUNCTION
Berg Jumper for VCORE Set Point
Detailed Description of Switch Settings
JUMPER
POSITION
FUNCTION
SW1
On
ENABLE On-Board Load Transient
Off (default)
DISABLE On-Board Load Transient
SW2
2
On
ENABLE ISL6244 and ISL6207
Off(default)
DISABLE ISL6244 and ISL6207
Application Note 1077
SW2 (ENABLE SWITCH) = OFF
ISL6244
CONTROLLER
JP1
5 BIT VID
JUMPERS =
SHUNTED
SW1 (LOAD TRANSIENT SWITCH) = OFF
FIGURE 1. ISL6244 EVAL BOARD INITIAL JUMPER AND SWITCH SETTINGS
3
Application Note 1077
+5V
VCC INPUT
SOURCE
GND
VCC INPUT
RETURN
J3
+VDC
J4
GND
TEST POINT FOR
ENABLE SENSE
TEST POINT FOR
PGOOD SENSE
SPECTRUM ANALYZER
INPUT FOR LOOP
GAIN/PHASE
MEASUREMENT
SCOPE JACK
FOR PHASE4
MONITORING
SCOPE JACK
FOR PHASE2
MONITORING
TEST POINT
FOR PWM1
TEST POINT
FOR PWM1
TEST POINT
FOR PWM2
TEST POINT
FOR PWM2
SCOPE JACK
FOR PHASE4
MONITORING
SCOPE JACK
FOR PHASE3
MONITORING
TEST POINT
FOR VCORE
REMOTE SENSE
TEST POINT
FOR VCORE
REMOTE SENSE
SCOPE JACK
FOR ON-BOARD
LOAD TRANSIENT
CURRENT
MEASUREMENT
SCOPE JACK
FOR VOUT
MONITORING
–
NEGATIVE CONNECTION
FOR ELECTRONIC LOAD
+
POSITIVE CONNECTION
FOR ELECTRONIC LOAD
FIGURE 2. ISL6244 EVAL BOARD TEST POINTS
4
J6
+12V
INPUT
SOURCE
J8
+12V
INPUT
RETURN
Board Layout Information
5
4
3
2
1
+VDC
R1
90K
+5V
D
D
C1
0.1uF
R2
10K
R36
10k
5
0
TP1
R3
107k
11
ENABLE
PGOOD
TP2
0
32
31
30
29
28
27
26
25
R41
0.0
33
B
PAD
24
23
22
21
20
19
18
17
PWM4
ISEN4
1
U1
ISL6244CR
PWM4
ISEN4
ISEN1
PWM1
PWM2
GND
ISEN2
ISEN3
nopop
ISEN1
PWM1
Use to switch between
3 & 4-phase operation:
TP5
TP4
1
4-phase: pop R42 (0-ohm)
nopop R41
PWM2
ISEN2
3-phase: nopop R42
pop R41 (0-ohm)
ISEN3
PWM3
1
0
VID2
VID1
VID0
NC
OFS
COMP
FB
NC
C
R42
1
1
2
3
4
5
6
7
8
VID3
NC
VID4
VFF
GND
EN
FS
PGOOD
VID4
VID3
VID2
VID1
VID0
IOUT
9
10 VDIFF
11 VSEN
12 RGND
GND
13
GND
14
VCC
15
16 PWM3
R4
2.5k
TP3
B
R35
0
TP6
0.0
R6
R7
12nF
2.43k
C3
715
1
R5
1
C2
20.0
R8
C4
603
6.8nF
TP7
+5V
TP8
VCORE+
R9
VCOREnopop
10.0
C5
1uF
A
Steve Laur
0
Size
A
Date:
5
4
3
FIGURE 3. SCHEMATIC 1
A
4020 Stirrup Creek Drive
Durham, NC 27703
Title
Rev
B
ISL6244 EVAL 1 for AMD Hammer
Tuesday, June 17, 2003
2
Sheet
1
1
of
5
Application Note 1077
C
Board Layout Information (Continued)
5
4
3
2
1
+VDC
+5V
R10
0.0
PHASE1
Q1
D
Q2 - nopop
C6
0.1uF
0
U2
6
1
2
3
4
PWM1
R37
nopop
TP9
UGATE PHASE
BOOT
EN
PWM
VCC
GND
LGATE
8
7
6
5
D
L1
1
0.56uH
2
VOUT
3
Q3
Q4
C7
1uF
ISL6207
0
0
R11
0
0
C
820PTC
+5V
ENABLE
+VDC
R12
0.0
PHASE2
Q5
C8
0.1uF
0
U3
1
2
3
4
B
PWM2
R38
nopop
TP10
Q6 - nopop
UGATE PHASE
BOOT
EN
PWM
VCC
GND
LGATE
8
7
6
5
L2
1
0.56uH
2
B
3
Q7
Q8
ISL6207
0
C9
1uF
0
R13
0
0
ISEN2
820PTC
Steve Laur
A
A
4020 Stirrup Creek Drive
Durham, NC 27703
Size
A
Date:
5
4
3
FIGURE 4. SCHEMATIC 2
Title
Rev
B
ISL6244 EVAL 1 for AMD Hammer
Wednesday, June 11, 2003
2
Sheet
2
1
of
5
Application Note 1077
C
ISEN1
Board Layout Information (Continued)
5
4
3
2
1
+VDC
+5V
R14
PHASE3
0.0
Q9
D
C10
0.1uF
7
PWM3
R39
nopop
D
0
U4
1
2
3
4
TP11
Q10 - nopop
UGATE PHASE
BOOT
EN
PWM
VCC
GND
LGATE
8
7
6
5
L3
1
0.56uH
2
VOUT
3
Q11
Q12
C11
1uF
ISL6207
0
0
R15
0
C
820PTC
+5V
ENABLE
+VDC
R16
0.0
PHASE4
TP12
Q13
Q14 - nopop
C12
0.1uF
0
U5
1
2
3
4
B
PWM4
R40
nopop
UGATE PHASE
BOOT
EN
PWM
VCC
GND
LGATE
L4
1
8
7
6
5
0.56uH
2
B
3
Q15
Q16
ISL6207
0
C13
1uF
0
R17
0
0
ISEN4
nopop
A
Use to switch between
3 & 4-phase operation:
Steve Laur
4-phase: pop R17 (820-PTC)
Size
A
3-phase: nopop R17
Date:
5
4
A
4020 Stirrup Creek Drive
Durham, NC 27703
3
FIGURE 5. SCHEMATIC 3
Title
Rev
B
ISL6244 EVAL 1 for AMD Hammer
Tuesday, June 17, 2003
2
Sheet
3
1
of
5
Application Note 1077
C
0
ISEN3
Board Layout Information (Continued)
5
4
3
2
1
TP13
1
VOUT
C14
nopop
C15
nopop
C16
nopop
C17
nopop
C18
nopop
C19
330uF
C20
330uF
C21
330uF
C22
330uF
C23
330uF
C24
330uF
C25
nopop
C26
nopop
C27
nopop
C28
nopop
C29
nopop
D
D
C30
22uF
C31
22uF
C32
nopop
C33
nopop
C34
22uF
C35
22uF
C36
22uF
C37
22uF
C38
22uF
C39
22uF
J1
VOUT
8
Output Capacitance
C40
22uF
C41
22uF
C42
nopop
C43
nopop
C44
22uF
TP14
C45
22uF
1
0
J2
GND
C
+VDC
Input Capacitance
J3
+VDC2
C46
10uF
J4
C47
10uF
C48
10uF
C49
10uF
C50
10uF
C51
10uF
C52
10uF
C53
10uF
C54
10uF
C65
10uF
C66
10uF
C67
10uF
GND
B
B
0
J6
+12V
J5
+5V
+12V
+5V
+5V decoupling
+12V decoupling
(locate by power terminals)
A
C55
10uF
C56
1uF
(locate by power terminals)
C57
10uF
J7
C58
1uF
J8
Steve Laur
A
4020 Stirrup Creek Drive
Durham, NC 27703
GND
0
0
GND
Size
A
Date:
5
4
3
FIGURE 6. SCHEMATIC 4
Title
Rev
B
ISL6244 EVAL 1 for AMD Hammer
Monday, July 14, 2003
2
Sheet
4
1
of
5
Application Note 1077
C
Application Note 1077
Board Layout Information (Continued)
5
4
VCC_CORE
TP15
Transient Load Generator
VOUT
+12V
VDD
HB
HO
HS
LO
VSS
LI
HI
D1
C60
no pop
Q17
HUF76129D3S
1
R19 324_1%
HIP2100
0
0
0
0
R20 357_1%
2
C62
1uF
C59
no pop
3
D
R18 357_1%
8
7
6
5
2
U6
1
2
3
4
D2
Q18
HUF76129D3S
1
3
R21 324_1%
+12V
LOAD CURRENT
TP16
R22
46.4k_1%
SW1
Top Side
ON
R23 402_1%
3
TRANSIENT
R25
nopop
R26
nopop
R27
nopop
R28
.100
OFF
Q19
2N7002
Top Side
C63
10uF
2
1
R24
.100
0
0
0
0
+5V
C
JP1
1
3
5
7
9
2
4
6
8
10
PGOOD
VID4
VID3
VID2
VID1
VID0
R29
2.43k
CR1
R30
10k
2
RED
VID4
VID3
VID2
VID1
VID0
1
R31
2.43k
0
3
Q20
2n7002
GREEN
4
VID CODE
3
POWER GOOD
INDICATOR
2
1
0
R32
0.0
ENABLE
+5V
VCORE0
VCORE+
VOUT
B
SW2
3
0.0
R33
R34
10k
Q21
2n7002
2
REMOTE SENSE LINES
connect at output caps
OFF
1
ENABLE VR
ON
C64
1n
0
0
0
ENABLE SIGNAL
FIGURE 7. SCHEMATIC 5
9
C61
no pop
Application Note 1077
TABLE 1. BILL OF MATERIALS
ITEM
QTY
REFERENCE
1
1
CR1
2
18
3
1
C4
4
1
5
VALUE
Dual LED2
TYPE
FOOTPRINT
VOLTAGE*
DIGIKEY 67-1372-1-ND
smdp_led_gw
-
-
-
-
7.4nF
-
-
-
C2
12nF
-
0805
10V
7
C5, C7, C9, C11, C56, C58, C13
1µF
-
0805
16V
6
4
C32, C33, C42, C43
nopop
-
1210
10V
7
1
C62
1µF
-
1206
16V
8
4
C1, C6, C8, C10, C12
0.1µF
-
0805
10V
9
16
C19, C20, C21, C22, C23, C24
330µF
Panasonic EEFSE0E331R
7343
-
10
12
C30, C31, C34-C41, C44, C45
22µF
Panasonic: ECJ3YB0J226M
1206
6.3V
11
14
Taiyo Yuden TMK325F106ZH
1210
25V
12
1
C63
10µF
Taiyo Yuden TMK325F106ZH
1812
25V
13
1
C64
1n
-
0805
10V
14
2
D1, D2
BAV99LT1
BAV99LT1
SOT23
-
15
1
JP1
Jumper - 5Pos
BERG 2x5 100MIL Header
jumper10
-
16
1
J1
VOUT
BURNDY KPA8CTP
kpa8ctp
-
17
1
J2
GND
BURNDY KPA8CTP
kpa8ctp
-
18
1
J3
+VDC
NEWARK 111-0702-001 RED
pad-170
-
19
1
J4
GND
NEWARK 111-0703-001 BLK
pad-170
-
20
1
J5
+5V
DIGIKEY 1514-2K-ND
tp-150c100p
-
21
1
J6
+12V
DIGIKEY 1514-2K-ND
tp-150c100p
-
22
2
J7, J8
GND
DIGIKEY 1514-2K-ND
tp-150c100p
-
23
3
L1, L2, L3, L4
0.56µH
Panasonic PCC-M104L Series
pcc-nx1_nx2_j
-
24
4
Q1, Q5, Q9, Q13
IRF7811W
-
pwrpak_so8_single
-
25
8
Q3, Q4, Q7, Q8, Q11, Q12, Q15
SI4362
-
pwrpak_so8_single
-
-
-
-
-
HUF76129D3S
-
TO-252AA
-
2N7002
-
SOT23
-
C3, C59, C60, C61, C14-C18, Q2, Q6, nopop
Q10, Q14, C25-C29, R25, R26, R27,
R37, R38, R39, R40, R42, R17
C46, C47, C48, C49, C50, C51, C52, 10µF
C53, C54, C55, C57, C65, C66, C67
Q16
26
2
Q18, Q17
27
3
Q19, Q20, Q21
28
1
R1
90K
-
0603
-
29
4
R2, R30, R34, R36
10K
-
0603
-
30
1
R3
107K
-
0603
-
31
1
R4
2.5K
-
0603
-
32
1
R5
2.43K
-
0603
-
33
1
R6
710
-
0603
-
34
1
R7
20
-
0603
-
35
1
R8
603
-
-
-
36
1
R9
10
-
0603
-
10
Application Note 1077
TABLE 1. BILL OF MATERIALS (Continued)
ITEM
QTY
REFERENCE
37
7
38
3
R11, R13, R15
39
2
40
VALUE
R10, R12, R14, R32, R33, R16, R35, 0.0
R41
TYPE
FOOTPRINT
VOLTAGE*
-
0603
-
820PTC
Vishay TFPT0805L820F
0805
-
R18, R20
357_1%
-
0603
-
2
R19, R21
324_1%
-
0603
-
41
1
R22
46.4K_1%
-
0603
-
42
1
R23
402_1%
-
0603
-
43
2
R24, R28
0.1
Vishay WSL series
2512
-
44
2
R29, R31
2.43K
0603
-
45
1
SW1
SPDT
C&K SMT DIGIKEY PN
CKN1101CT-ND
gt11sc
-
46
1
SW2
DPST
C&K SMT DIGIKEY PN
CKN1099CT-ND
gt11sc
-
47
10
TP1, TP2, TP3, TP4, TP5, TP6,
Test Point
KEYSTONE 5002
PAD-100
-
-
-
-
-
TP7, TP8, TP13, TP14
48
1
TP9
Phase1
TEK 131-4244-00
TEK 131-4244-00
-
49
1
TP10
Phase2
TEK 131-4244-00
TEK 131-4244-00
-
50
1
TP11
Phase3
TEK 131-4244-00
TEK 131-4244-00
-
51
1
TP12
Phase4
TEK 131-4244-00
TEK 131-4244-00
-
52
1
TP15
VCC_CORE
TEK 131-4244-00
TEK 131-4244-00
-
53
1
TP16
Load Current
TEK 131-4244-00
TEK 131-4244-00
-
54
1
U1
ISL6244CR
Intersil ISL6244
32mlfp_5x5
-
55
4
U2, U3, U4, U5
ISL6207
Intersil ISL6207
soic8
-
56
1
U6
HIP2100
Intersil HIP2100
soic8
-
11
Application Note 1077
TOP LAYER SILKSCREEN
12
Application Note 1077
LAYER 2
13
Application Note 1077
LAYER 3
14
Application Note 1077
LAYER 4
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Application Note 1077
BOTTOM SILKSCREEN
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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