DATASHEET

ISL6323B
®
Data Sheet
May 12, 2010
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
Features
The ISL6323B dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6323B supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6323B features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is
provided by a two-to-four-phase PWM voltage regulator (VR)
controller. The integration of two power MOSFET drivers,
adding flexibility in layout, reduce the number of external
components in the multi-phase section. A single phase PWM
controller with integrated driver provides a second precision
voltage regulation system for the North Bridge portion of the
processor. This monolithic, dual controller with integrated
driver solution provides a cost and space saving power
management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6323B features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient
response to load apply and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6323B supports Power Savings Mode by dropping
the number of phases to two when the PSI_L bit is set.
Ordering Information
TEMP.
RANGE
(°C)
• Processor Core Voltage Via Integrated Multi-Phase
Power Conversion
• Configuration Flexibility
- 1- or 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• PSI_L Support with Phase Shedding for Improved
Efficiency at Light Load
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Parallel VID Interface Inputs
- 6-bit VID input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
• Variable Gate Drive Bias: 5V to 12V
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Processor NorthBridge Voltage Via Single Phase
Power Conversion
• Precision Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over Temperature
ISL6323BCRZ*
ISL6323B CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
ISL6323BIRZ*
ISL6323B IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
• Overcurrent Protection
PART NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
FN6879.1
• Continuous DCR Current Sensing
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6323B
Pinout
COMP_NB
ISEN_NB-
ISEN4+
ISEN4-
ISEN3+
ISEN3-
PVCC_NB
LGATE_NB
BOOT_NB
UGATE_NB
PHASE_NB
VDDPWRGD
ISL6323B
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
FB_NB
1
36
PWM4
ISEN_NB+
2
35
PWM3
RGND_NB
3
34
PWROK
VID0/VFIXEN
4
33
PHASE1
VID1/SEL
5
32
UGATE1
VID2/SVD
6
31
BOOT1
VID3/SVC
7
30
LGATE1
VID4
8
29
PVCC1_2
VID5
9
28
LGATE2
VCC 10
27
BOOT2
FS 11
26
UGATE2
RGND 12
25
PHASE2
2
13
14
15
16
17
18
19
20
21
22
23
24
VSEN
OFS
DVC
RSET
FB
COMP
APA
ISEN1+
ISEN1-
ISEN2+
ISEN2-
EN
49
GND
FN6879.1
May 12, 2010
ISL6323B
Functional Pin Description
PIN NUMBER
SYMBOL
DESCRIPTION
1, 48
FB_NB and
COMP_NB
These pins are the internal error amplifier inverting input and output respectively of the
NB VR controller. FB_NB, VDIFF_NB, and COMP_NB are tied together through external
R-C networks to compensate the regulator.
2, 47
ISEN_NB+,
ISEN_NB1-
These pins are used for differentially sensing the North Bridge output current. The
sensed current is used for protection and load line regulation if droop is enabled.
Connect ISEN_NB- to the node between the RC sense element surrounding the inductor.
Tie the ISEN_NB+ pin to the VNB side of the sense capacitor.
3
RGND_NB
This pin is an input to the NB VR controller precision differential remote-sense amplifier
and should be connected to the sense pin of the North Bridge, VDDNBFBL.
4
VID0/VFIXEN
If VID1 is LO prior to enable [SVI Mode], the pin functions as the VFIXEN selection input
from the AMD processor for determining SVI mode versus VFIX mode of operation.
If VID1 is HI prior to enable [PVI Mode], the pin is used as DAC input VID0. This pin has
an internal 30µA pull-down current applied to it at all times.
5
VID1/SEL
This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling
the ISL6323B. If the pin is LO prior to enable, the ISL6323B is in SVI mode and the dual
purpose pins [VID0/VFIXEN, VID2/SVC, VID3/SVD] use their SVI mode related
functions. If the pin held HI prior to enable, the ISL6323B is in PVI mode and dual
purpose pins use their VIDx related functions to decode the correct DAC code.
6
VID2/SVD
If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID data bi-directional
signal to and from the master device on AMD processor. If VID1 is HI prior to enable [PVI
Mode], this pin is used to decode the programmed DAC code for the processor. In PVI
mode, this pin has an internal 30µA pull-down current applied to it. There is no pull-down
current in SVI mode.
7
VID3/SVC
If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID clock input from the
AMD processor. If VID1 is HI prior to enable [PVI Mode], the ISL6323B is in PVI mode
and this pin is used to decode the programmed DAC code for the processor. In PVI mode,
this pin has an internal 30µA pull-down current applied to it. There is no pull-down
current in SVI mode.
8, 9
VID4, VID5
These pins are active only when the ISL6323B is in PVI mode. When VID1 is HI prior to
enable, the ISL6323B decodes the programmed DAC voltage required by the AMD
processor. These pins have an internal 30µA pull-down current applied to them at all
times.
10
VCC
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply
and decouple using a quality 0.1µF ceramic capacitor.
11
FS
A resistor, placed from FS to Ground or from FS to VCC, sets the switching frequency of
both controllers. Refer to Equation 1 for proper resistor calculation.
R T = 10
[ 10.61 – 1.035 log ( f s ) ]
(EQ. 1)
With the resistor tied from FS to Ground, Droop is enabled. With the resistor tied from
FS to VCC, Droop is disabled.
12, 13
RGND, VSEN
14
OFS
The OFS pin provides a means to program a DC current for generating an offset voltage
across the resistor between FB and VSEN The offset current is generated via an external
resistor and precision internal voltage references. The polarity of the offset is selected
by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left
unconnected.
15
DVC
The DVC pin is a buffered version of the reference to the error amplifier. A series resistor
and capacitor between the DVC pin and FB pin smooth the voltage transition during
VID-on-the-fly operations.
3
VSEN and RGND are inputs to the core voltage regulator (VR) controller precision
differential remote-sense amplifier and should be connected to the sense pins of the
remote processor core(s), VDDFB[H,L].
FN6879.1
May 12, 2010
ISL6323B
Functional Pin Description (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
16
RSET
Connect this pin to the VCC pin through a resistor (RSET) to set the effective value of
the internal RISEN current sense resistors. The values of the RSET resistor should be no
less than 20kΩ and no more than 80kΩ. A 0.1µF capacitor should be placed in parallel to
the RSET resistor.
17, 18
FB, COMP
These pins are the internal error amplifier inverting input and output respectively of the
core VR controller. FB, VSEN and COMP are tied together through external R-C networks
to compensate the regulator.
19
APA
Adaptive Phase Alignment (APA) pin for setting trip level and adjusting time constant. A
100µA current flows into the APA pin and by tying a resistor from this pin to COMP the
trip level for the Adaptive Phase Alignment circuitry can be set.
20, 21, 22, 23,
43, 44, 45, 46
ISEN1+, ISEN1-,
ISEN2+, ISEN2-,
ISEN3-, ISEN3+,
ISEN4-, ISEN4+
These pins are used for differentially sensing the corresponding channel output currents.
The sensed currents are used for channel balancing, protection, and core load line
regulation.
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node between the RC sense
elements surrounding the inductor of their respective channel. Tie the ISEN+ pins to the
VCORE side of their corresponding channel’s sense capacitor.
24
EN
This pin is a threshold-sensitive (approximately 0.85V) system enable input for the
controller. Held low, this pin disables both CORE and NB controller operation. Pulled high,
the pin enables both controllers for operation.
When the EN pin is pulled high, the ISL6323B will be placed in either SVI or PVI mode.
The mode is determined by the latched value of VID1 on the rising edge of the EN signal.
A third function of this pin is to provide driver bias monitor for external drivers. A resistor
divider with the center tap connected to this pin from the drive bias supply prevents
enabling the controller before insufficient bias is provided to external driver. The resistors
should be selected such that when the POR-trip point of the external driver is reached,
the voltage at this pin meets the above mentioned threshold level.
25, 33
PHASE2 and PHASE1 Connect these pins to the sources of the corresponding upper MOSFETs. These pins are
the return path for the upper MOSFET drives.
26, 32
UGATE2 and UGATE1 Connect these pins to the corresponding upper MOSFET gates. These pins are used to
control the upper MOSFETs and are monitored for shoot-through prevention purposes.
Maximum individual channel duty cycle is limited to 93.3%.
27, 31
28, 30
BOOT2 and BOOT1
These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect
these pins to appropriately chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC1_2 pin provide the necessary bootstrap charge.
LGATE2 and LGATE1 These pins are used to control the lower MOSFETs. Connect these pins to the
corresponding lower MOSFETs’ gates.
29
PVCC1_2
The power supply pin for the multi-phase internal MOSFET drivers. Connect this pin to
any voltage from +5V to +12V depending on the desired MOSFET gate-drive level.
Decouple this pin with a quality 1.0µF ceramic capacitor.
34
PWROK
System wide Power-Good signal. If this pin is low, the two SVI bits are decoded to
determine the “metal VID”. When the pin is high, the SVI is actively running its protocol.
35, 36
PWM3 and PWM4
Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil
driver IC if 3- or 4-phase operation is desired. Connect the ISEN- pins of the channels
not desired to +5V to disable them and configure the core VR controller for 2-phase or
3-phase operation.
37
VDDPWRGD
During normal operation this pin indicates whether both output voltages are within
specified overvoltage and undervoltage limits. If either output voltage exceeds these
limits or a reset event occurs (such as an overcurrent event), the pin is pulled low. This
pin is always low prior to the end of soft-start.
38
PHASE_NB
Connect this pin to the source of the corresponding upper MOSFET. This pin is the return
path for the upper MOSFET drive. This pin is used to monitor the voltage drop across the
upper MOSFET for overcurrent protection.
4
FN6879.1
May 12, 2010
ISL6323B
Functional Pin Description (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
39
UGATE_NB
Connect this pin to the corresponding upper MOSFET gate. This pin provides the
PWM-controlled gate drive for the upper MOSFET and is monitored for shoot-through
prevention purposes.
40
BOOT_NB
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect
this pin to appropriately chosen external bootstrap capacitor. The internal bootstrap
diode connected to the PVCC_NB pin provides the necessary bootstrap charge.
41
LGATE_NB
Connect this pin to the corresponding MOSFET’s gate. This pin provides the
PWM-controlled gate drive for the lower MOSFET. This pin is also monitored by the
adaptive shoot-through protection circuitry to determine when the lower MOSFET has
turned off.
42
PVCC_NB
The power supply pin for the internal MOSFET driver for the Northbridge controller.
Connect this pin to any voltage from +5V to +12V depending on the desired MOSFET
gate-drive level. Decouple this pin with a quality 1.0µF ceramic capacitor.
49
GND
GND is the bias and reference ground for the IC. The GND connection for the ISL6323B
is through the thermal pad on the bottom of the package.
Integrated Driver Block Diagram
PVCC
BOOT
UGATE
PWM
20KΩ
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOTTHROUGH
PROTECTION
PHASE
10KΩ
LGATE
5
FN6879.1
May 12, 2010
ISL6323B
Controller Block Diagram
RGND_NB
NB_REF
COMP_NB
FB_NB
∑
BOOT_NB
E/A
ISEN_NB+
UV
LOGIC
CURRENT
SENSE
ISEN_NB-
MOSFET
DRIVER
OV
LOGIC
RAMP
UGATE_NB
PHASE_NB
LGATE_NB
VDDPWRGD
EN_12V
PVCC_NB
APA
APA
NB
FAULT
LOGIC
COMP
OFS
ENABLE
LOGIC
EN
VCC
POWER-ON
RESET
OFFSET
PVCC1_2
SOFT-START
AND
FB
FAULT LOGIC
E/A
DVC
RGND
2X
BOOT1
∑
DROOP
CONTROL
LOAD APPLY
TRANSIENT
ENHANCEMENT
PWROK
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
MOSFET
DRIVER
UGATE1
PHASE1
LGATE1
SVI
SLAVE
BUS
AND
PVI
DAC
CLOCK AND
TRIANGLE WAVE
GENERATOR
FS
VID5
PWM1
∑
NB_REF
BOOT2
OV
LOGIC
PWM2
∑
VSEN
UV
LOGIC
RSET
MOSFET
DRIVER
PWM3
ISEN1-
PHASE2
LGATE2
∑
OC
RESISTOR
MATCHING
PH3/PH4
POR
PWM4
ISEN1+
UGATE2
I_TRIP
CH1
CURRENT
SENSE
I_AVG
∑
EN_12V
CHANNEL
DETECT
ISEN3ISEN4-
ISEN2+
ISEN2ISEN3+
ISEN3-
CH2
CURRENT
SENSE
CHANNEL
CURRENT
BALANCE
ISEN4-
1
N
PWM3
SIGNAL
LOGIC
CH3
CURRENT
SENSE
PWM3
∑
ISEN3-
ISEN4+
I_AVG
CH4
CURRENT
SENSE
PWM4
SIGNAL
LOGIC
PWM4
ISEN4-
GND
6
FN6879.1
May 12, 2010
ISL6323B
Typical Application - SVI Mode
+12V
+12V
FB
COMP
ISEN3+
ISEN3PWM3
VSEN
BOOT1
BOOT1
UGATE1
UGATE1
PHASE1
PHASE1
LGATE1
LGATE1
PWM1
PGND
APA
ISEN1ISEN1+
DVC
ISL6614
+12V
+5V
PVCC1_2
VDD
+12V
VCC
BOOT2
+12V
VCC
PVCC
BOOT2
OFS
UGATE2
FS
CPU
LOAD
PHASE2
+5V
RSET
NC
NC
UGATE2 GND
PHASE2
PWM2
LGATE2
LGATE2
VFIXEN
ISEN2SEL
ISEN2+
SVD
SVC
RGND
VID4
VID5
PWROK
VDDPWRGD ISEN4+
GND
ISEN4PWM4
+12V
ISL6323B
+12V
PVCC_NB
OFF
EN
BOOT_NB
ON
UGATE_NB
PHASE_NB
VDDNB
LGATE_NB
COMP_NB ISEN_NB-
NB
LOAD
ISEN_NB+
FB_NB
7
FN6879.1
May 12, 2010
ISL6323B
Typical Application - PVI Mode
+12V
+12V
FB
COMP
ISEN3+
ISEN3PWM3
VSEN
BOOT1
BOOT1
UGATE1
UGATE1
PHASE1
PHASE1
LGATE1
APA
LGATE1
DVC
ISEN1ISEN1+
PGND
ISL6614
+12V
+5V
PWM1
VDD
+12V
PVCC1_2
VCC
+12V
VCC
BOOT2 PVCC
BOOT2
+5V
OFS
UGATE2
FS
PHASE2
PHASE2
CPU
LOAD
PWM2
LGATE2
LGATE2
RSET
NC
UGATE2 GND
VID0
ISEN2VID1/SEL
ISEN2+
VID2
VID3
RGND
VID4
VID5
PWROK
VDDPWRGD ISEN4+
GND
ISEN4PWM4
ISL6323B
+12V
+12V
NORTH BRIDGE REGULATOR
PVCC_NB
OFF
DISABLED IN PVI MODE
EN
BOOT_NB
ON
UGATE_NB
PHASE_NB
VDDNB
LGATE_NB
COMP_NB ISEN_NB-
NB
LOAD
ISEN_NB+
FB_NB
8
FN6879.1
May 12, 2010
ISL6323B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.2V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage (VBOOT). . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage (VPHASE) . . . . . . . GND - 0.3V to 24V (PVCC = 12V)
GND - 8V (<400ns, 20µJ) to 31V (<200ns, VBOOT-PHASE = 5V)
Upper Gate Voltage (VUGATE). . . . VPHASE - 0.3V to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
Lower Gate Voltage (VLGATE) . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
Thermal Resistance
θJA (°C/W)
θJC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . . . .
27
2
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%
Ambient Temperature
ISL6323BCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6323BIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNITS
BIAS SUPPLIES
Input Bias Supply Current
IVCC; EN = high
15
22
25
mA
Gate Drive Bias Current - PVCC1_2 Pin
IPVCC1_2; EN = high
1
1.8
3
mA
Gate Drive Bias Current - PVCC_NB Pin
IPVCC_NB; EN = high
0.3
0.9
2
mA
VCC POR (Power-On Reset) Threshold
VCC Rising
4.20
4.35
4.50
V
VCC Falling
3.70
3.85
4.05
V
PVCC Rising
4.20
4.35
4.50
V
PVCC Falling
3.70
3.85
4.05
V
RT = 100kΩ (±0.1%) to Ground,
(Droop Enabled)
225
250
265
kHz
RT = 100kΩ (±0.1%) to VCC,
(Droop Disabled), 0°C to +70°C
245
275
310
kHz
RT = 100kΩ (±0.1%) to VCC,
(Droop Disabled), -40°C to +85°C
240
275
310
kHz
Typical Adjustment Range of Switching Frequency
(Note 4)
0.08
1.0
MHz
Oscillator Ramp Amplitude, VP-P
(Note 4)
1.50
V
Maximum Duty Cycle
(Note 4)
99.5
%
PVCC POR (Power-On Reset) Threshold
PWM MODULATOR
Oscillator Frequency Accuracy, FSW
CONTROL THRESHOLDS
EN Rising Threshold
EN Hysteresis
0.80
0.88
0.92
V
70
130
190
mV
PWROK Input HIGH Threshold
1.1
PWROK Input LOW Threshold
V
0.95
VDDPWRGD Sink Current
Open drain, V_VDDPWRGD = 400mV
PWM Channel Disable Threshold
VISEN3-, VISEN4-, VISEN2-
9
V
4
4.4
mA
V
FN6879.1
May 12, 2010
ISL6323B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNITS
PIN_ADJUSTABLE OFFSET
OFS Source Current Accuracy (Positive Offset)
ROFS = 10kΩ (±0.1%) from OFS to GND
27.5
31
34.5
µA
OFS Sink Current Accuracy (Negative Offset)
ROFS = 30kΩ (±0.1%) from OFS to VCC
50.5
53.5
56.5
µA
-0.6
0.6
%
System Accuracy (0.600V < VDAC < 1.000V)
-1.0
1.0
%
System Accuracy (VDAC < 0.600V)
-2.0
2.0
%
REFERENCE AND DAC
System Accuracy (VDAC > 1.000V)
DVC Voltage Gain
VDAC = 1V
APA Current Tolerance
VAPA = 1V
2.0
90
100
V
108
µA
ERROR AMPLIFIER
DC Gain
RL = 10k to ground (Note 4)
96
dB
Gain-Bandwidth Product (Note 4)
CL = 100pF, RL = 10k to ground (Note 4)
20
MHz
Slew Rate (Note 4)
CL = 100pF, Load = ±400µA (Note 4)
8
V/µs
Maximum Output Voltage
Load = 1mA
Minimum Output Voltage
Load = -1mA
3.80
4.20
V
1.3
1.6
V
3.0
4.0
mV/µs
0.5
V
SOFT-START RAMP
Soft-Start Ramp Rate
2.2
PWM OUTPUTS
PWM Output Voltage LOW Threshold
ILOAD = ±500µA
PWM Output Voltage HIGH Threshold
ILOAD = ±500µA
4.5
VISENn--VISENn+ = 23.2mV, RSET = 37.6kΩ,
4 Phases, TA = +25°C
68
88
µA
VISEN_NB- - VISEN_NB+ = 23.2mV,
RSET = 37.6kΩ, 4 Phases, TA = +25°C
68
89
µA
VISENn- - VISENn+ = 23.2mV, RSET = 37.6kΩ,
4 Phases, TA = +25°C
68
88
µA
Normal Operation, RSET = 28.2kΩ
87
120
µA
V
CURRENT SENSING - CORE CONTROLLER
Sensed Current Tolerance
CURRENT SENSING - NB CONTROLLER
Sensed Current Tolerance
DROOP CURRENT
Tolerance
OVERCURRENT PROTECTION
Overcurrent Trip Level - Average Channel
Overcurrent Limiting - Individual Channel
100
Dynamic VID Change (Note 4)
130
µA
Normal Operation, RSET = 28.2kΩ
142
µA
Dynamic VID Change (Note 4)
190
µA
POWER GOOD
Core Overvoltage Threshold
VSEN Rising
VDAC
+225mV
VDAC +
250mV
VDAC
+275mV
Core Undervoltage Threshold
VSEN Falling
VDAC
-325mV
VDAC
-300mV
VDAC
-270mV
NB Undervoltage Threshold
ISEN_NB+ falling
VDAC
-310mV
VDAC
-275mV
VDAC
-235mV
Power Good Hysteresis
50
10
mV
FN6879.1
May 12, 2010
ISL6323B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified. (Continued)
MIN
(Note 3)
TYP
MAX
(Note 3)
UNITS
OVP Trip Level
1.73
1.80
1.84
V
OVP Lower Gate Release Threshold
350
400
mV
tRUGATE; VPVCC = 12V, 3nF Load, 10% to 90%
26
ns
LGATE Rise Time
tRLGATE; VPVCC = 12V, 3nF Load, 10% to 90%
18
ns
UGATE Fall Time
tFUGATE; VPVCC = 12V, 3nF Load, 90% to 10%
18
ns
LGATE Fall Time
tFLGATE; VPVCC = 12V, 3nF Load, 90% to 10%
12
ns
UGATE Turn-On Non-overlap
tPDHUGATE; VPVCC = 12V, 3nF Load, Adaptive
10
ns
LGATE Turn-On Non-overlap
tPDHLGATE; VPVCC = 12V, 3nF Load, Adaptive
10
ns
Upper Drive Source Resistance
VPVCC = 12V, 15mA Source Current
2.0
Ω
Upper Drive Sink Resistance
VPVCC = 12V, 15mA Sink Current
1.65
Ω
PARAMETER
TEST CONDITIONS
OVERVOLTAGE PROTECTION
SWITCHING TIME (Note 4) [See “Timing Diagram” on page 12]
UGATE Rise Time
GATE DRIVE RESISTANCE (Note 3)
Lower Drive Source Resistance
VPVCC = 12V, 15mA Source Current
1.25
Ω
Lower Drive Sink Resistance
VPVCC = 12V, 15mA Sink Current
0.80
Ω
MODE SELECTION
VID1/SEL Input Low
EN taken from LO to HI, VDDIO = 1.5V
VID1/SEL Input High
EN taken from LO to HI, VDDIO = 1.5V
0.6
1.00
V
V
PVI INTERFACE
VIDx Pull-down
VDDIO = 1.5V
VIDx Input Low
VDDIO = 1.5V
VIDx Input High
VDDIO = 1.5V
30
40
µA
0.6
V
1.00
V
0.95
V
SVI INTERFACE
SVC, SVD Input HIGH (VIH)
SVC, SVD Input LOW (VIL)
Schmitt Trigger Input Hysteresis
0.14
SVD Low Level Output Voltage
0.35
3mA Sink Current
Maximum SVC, SVD Leakage (Note 4)
±5
0.4
V
0.45
V
0.285
V
µA
NOTES:
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
4. Limits established by characterization and are not production tested.
11
FN6879.1
May 12, 2010
ISL6323B
Timing Diagram
tPDHUGATE
tRUGATE
tFUGATE
UGATE
LGATE
tFLGATE
tRLGATE
tPDHLGATE
Operation
The ISL6323B utilizes a multi-phase architecture to provide
a low cost, space saving power conversion solution for the
processor core voltage. The controller also implements a
simple single phase architecture to provide the Northbridge
voltage on the same chip.
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.
IL1 + IL2 + IL3, 7A/DIV
Multi-phase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multi-phase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter that is
both cost-effective and thermally viable have forced a
change to the cost-saving approach of multi-phase. The
ISL6323B controller helps simplify implementation by
integrating vital functions and requiring minimal external
components. The “Controller Block Diagram” on page 6
provides a top level view of the multi-phase power
conversion using the ISL6323B controller.
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-topeak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 2 and 3).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
12
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
PWM2, 5V/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
1μs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine Equation 2, which represents
an individual channel peak-to-peak inductor current.
( V IN – V OUT ) V OUT
I P-P = ----------------------------------------------------L fS V
(EQ. 2)
IN
In Equation 2, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 2 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 3. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels.
Output-voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
FN6879.1
May 12, 2010
ISL6323B
( V IN – N V OUT ) V OUT
I C, PP = ----------------------------------------------------------L fS V
(EQ. 3)
IN
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has
11.9ARMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
Figures 25, 26 and 27 in the section entitled “” on page 33
can be used to determine the input-capacitor RMS current
based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution.
Active Pulse Positioning Modulated PWM
Operation
The ISL6323B uses a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. The advantage of Intersil’s proprietary Active Pulse
Positioning (APP) modulator is that the PWM signal has the
ability to turn on at any point during this PWM time interval,
and turn off immediately after the PWM signal has
13
transitioned high. This is important because it allows the
controller to quickly respond to output voltage drops
associated with current load spikes, while avoiding the ring
back affects associated with other modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, VCOMP, minus the current correction
signal relative to the proprietary modulator ramp waveform
as illustrated in Figure 3. At the beginning of each PWM time
interval, this modified VCOMP signal is compared to the
internal modulator waveform. As long as the modified
VCOMP voltage is lower then the modulator waveform
voltage, the PWM signal is commanded low. The internal
MOSFET driver detects the low state of the PWM signal and
turns off the upper MOSFET and turns on the lower
synchronous MOSFET. When the modified VCOMP voltage
crosses the modulator ramp, the PWM output transitions
high, turning off the synchronous MOSFET and turning on
the upper MOSFET. The PWM signal will remain high until
the modified VCOMP voltage crosses the modulator ramp
again. When this occurs the PWM signal will transition low
again.
During each PWM time interval the PWM signal can only
transition high once. Once PWM transitions high it can not
transition high again until the beginning of the next PWM
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.
To further improve the transient response, ISL6323B also
implements Intersil’s proprietary Adaptive Phase Alignment
(APA) technique, which turns on all phases together under
transient events with large step current. With both APP and
APA control, ISL6323B can achieve excellent transient
performance and reduce the demand on the output
capacitors.
Adaptive Phase Alignment (APA)
To further improve the transient response, the ISL6323B
also implements Intersil’s proprietary Adaptive Phase
Alignment (APA) technique, which turns on all of the
channels together at the same time during large current step
transient events. As Figure 3 shows, the APA circuitry works
by monitoring the voltage on the APA pin and comparing it to
a filtered copy of the voltage on the COMP pin. The voltage
on the APA pin is a copy of the COMP pin voltage that has
been negatively offset. If the APA pin exceeds the filtered
COMP pin voltage an APA event occurs and all of the
channels are forced on.
FN6879.1
May 12, 2010
ISL6323B
ISL6323B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
inductor current, IL. This sensed current, ISEN, is simply a
scaled version of the inductor current.
APA
CAPA
RAPA
100µA
VAPA,TRIP
+
+
LOW
PASS
FILTER
COMP
APA
TO APA
CIRCUITRY
PWM
SWITCHING PERIOD
IL
+
-
ERROR
AMPLIFIER
FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION
The APA trip level is the amount of DC offset between the
COMP pin and the APA pin. This is the voltage excursion
that the APA and COMP pins must have during a transient
event to activate the Adaptive Phase Alignment circuitry.
This APA trip level is set through a resistor, RAPA, that
connects from the APA pin to the COMP pin. A 100µA
current flows across RAPA into the APA pin to set the APA
trip level as described in Equation 4. An APA trip level of
500mV is recommended for most applications. A 0.1µF
capacitor, CAPA, should also be placed across the RAPA
resistor to help with noise immunity.
V APA, TRIP = R APA ⋅ 100 × 10
–6
(EQ. 4)
PWM Operation
The timing of each core channel is set by the number of
active channels. Channel detection on the ISEN2-, ISEN3and ISEN4- pins selects 1-Channel to 4-Channel operation
for the ISL6323B. The switching cycle is defined as the time
between PWM pulse termination signals of each channel.
The cycle time of the pulse signal is the inverse of the
switching frequency set by the resistor between the FS pin
and ground. The PWM signals command the MOSFET
driver to turn on/off the channel MOSFETs.
For 4-channel operation, the channel firing order is 1-2-3-4:
PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2
output follows another 1/4 of a cycle after PWM3, and
PWM1 delays another 1/4 of a cycle after PWM2. For
3-channel operation, the channel firing order is 1-2-3.
Connecting ISEN4- to VCC selects three channel operation
and the pulse times are spaced in 1/3 cycle increments. If
ISEN3- is also connected to VCC, 2-Channel operation is
selected and the PWM2 pulse happens 1/2 of a cycle after
PWM1 pulse. If ISEN2- is also connected to VCC,
1HChannel operation is selected.
Continuous Current Sampling
In order to realize proper current-balance, the currents in
each channel are sampled continuously every switching
cycle. During this time, the current-sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
14
ISEN
TIME
FIGURE 4. CONTINUOUS CURRENT SAMPLING
The ISL6323B supports Inductor DCR current sensing to
continuously sample each channel’s current for channel-current
balance. The internal circuitry, shown in Figure 4 represents
Channel N of an N-Channel converter. This circuitry is repeated
for each channel in the converter, but may not be active
depending on how many channels are operating.
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 5. The channel current
ILn, flowing through the inductor, passes through the DCR.
Equation 5 shows the S-domain equivalent voltage, VL,
across the inductor.
V L ( s ) = I L ⋅ ( s ⋅ L + DCR )
n
(EQ. 5)
A simple R-C network across the inductor (R1, R2 and C)
extracts the DCR voltage, as shown in Figure 5. The voltage
across the sense capacitor, VC, can be shown to be
proportional to the channel current ILn, shown in Equation 6.
s⋅L
⎛ ------------+ 1⎞
⎝ DCR
⎠
V C ( s ) = -------------------------------------------------------- ⋅ K ⋅ DCR ⋅ I L
n
⎛ ( R1 ⋅ R2 )
⎞
⎜ s ⋅ ------------------------ ⋅ C + 1⎟
R1 + R2
⎝
⎠
(EQ. 6)
Where:
R2
K = --------------------R2 + R1
(EQ. 7)
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time constant
(see Equations 7 and 8), then VC is equal to the voltage drop
across the DCR multiplied by the ratio of the resistor divider,
K. If a resistor divider is not being used, the value for K is 1.
FN6879.1
May 12, 2010
ISL6323B
I
VIN
L
n
UGATE(n)
L
MOSFET
LGATE(n)
DCR
VOUT
+
VL(s)
VC(s)
R1
COUT
C
R2
ISL6323B INTERNAL CIRCUIT
In
SAMPLE
-
VC(s)
RISEN
-
+
+
ISENnISENn+
VCC
ISEN
RSET
RSET
CSET
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
R1 ⋅ R2
L
-⋅C
------------- = -------------------R1 + R2
DCR
(EQ. 8)
The capacitor voltage VC, is then replicated across the
effective internal sense resistor, RISEN. This develops a
current through RISEN which is proportional to the inductor
current. This current, ISEN, is continuously sensed and is
then used by the controller for load-line regulation,
channel-current balancing, and overcurrent detection and
limiting. Equation 9 shows that the proportion between the
channel current, IL, and the sensed current, ISEN, is driven
by the value of the effective sense resistance, RISEN, and
the DCR of the inductor.
DCR
I SEN = I L ⋅ -----------------R ISEN
(EQ. 9)
The effective internal RISEN resistance is important to the
current sensing process because it sets the gain of the load
line regulation loop when droop is enabled as well as the
gain of the channel-current balance loop and the overcurrent
trip level. The effective internal RISEN resistance is user
programmable and is set through use of the RSET pin.
Placing a single resistor, RSET, from the RSET pin to the
VCC pin programs the effective internal RISEN resistance
according to Equation 10.
3
R ISEN = ---------- ⋅ R SET
400
(EQ. 10)
15
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
-
+
INDUCTOR
-
DRIVER
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The RSET resistor
will program all the effective internal RISEN resistors to the
same value.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, In,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, IAVG, provides a measure of the total loadcurrent demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented
current-balance method is illustrated in Figure 6, with error
correction for Channel 1 represented. In the figure, the cycle
average current, IAVG, is compared with the Channel 1
sample, I1, to create an error signal IER.The filtered error
signal modifies the pulse width commanded by VCOMP to
correct any unbalance and force IER toward zero. The same
method for error signal correction is applied to each active
channel.
VCOMP
+
+
MODULATOR
RAMP
WAVEFORM
FILTER
PWM1
-
TO GATE
CONTROL
LOGIC
f(s)
I4
IER
IAVG
-
÷N
+
Σ
I3
I2
I1
NOTE: Channel 3 and 4 are optional.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENTBALANCE ADJUSTMENT
VID Interface
The ISL6323B supports hybrid power control of AMD
processors which operate from either a 6-bit parallel VID
interface (PVI) or a serial VID interface (SVI). The VID1/SEL pin
is used to command the ISL6323B into either the PVI mode or
the SVI mode. Whenever the EN pin is held LOW, both the
FN6879.1
May 12, 2010
ISL6323B
multi-phase Core and single-phase North Bridge Regulators
are disabled and the ISL6323B is continuously sampling
voltage on the VID1/SEL pin. When the EN pin is toggled
HIGH, the status of the VID1/SEL pin will latch the ISL6323B
into either PVI or SVI mode. This latching occurs on the rising
edge of the EN signal. If the VID1/SEL pin is held LOW during
the latch, the ISL6323B will be placed into SVI mode. If the
VID1/SEL pin is held HIGH during the latch, the ISL6323B will
be placed into PVI mode. For the ISL6323B to properly enter
into either mode, the level on the VID1/SEL pin must be stable
no less that 1µs prior to the EN signal transitioning from low to
high.
TABLE 1. 6-BIT PARALLEL VID CODES (Continued)
VID5
VID4
VID3
VID2
VID1
VID0
VREF
0
1
1
1
0
0
0.8500
0
1
1
1
0
1
0.8250
0
1
1
1
1
0
0.8000
0
1
1
1
1
1
0.7750
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
6-bit Parallel VID Interface (PVI)
1
0
0
1
0
0
0.7125
With the ISL6323B in PVI mode, the single-phase North
Bridge regulator is disabled. Only the multi-phase controller
is active in PVI mode to support uniplane VDD only
processors. Table 1 shows the 6-bit parallel VID codes and
the corresponding reference voltage.
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
1
0
0
1
1
1
0.6750
1
0
1
0
0
0
0.6625
1
0
1
0
0
1
0.6500
TABLE 1. 6-BIT PARALLEL VID CODES
1
0
1
0
1
0
0.6375
VID5
VID4
VID3
VID2
VID1
VID0
VREF
1
0
1
0
1
1
0.6250
0
0
0
0
0
0
1.5500
1
0
1
1
0
0
0.6125
0
0
0
0
0
1
1.5250
1
0
1
1
0
1
0.6000
0
0
0
0
1
0
1.5000
1
0
1
1
1
0
0.5875
0
0
0
0
1
1
1.4750
1
0
1
1
1
1
0.5750
0
0
0
1
0
0
1.4500
1
1
0
0
0
0
0.5625
0
0
0
1
0
1
1.4250
1
1
0
0
0
1
0.5500
0
0
0
1
1
0
1.4000
1
1
0
0
1
0
0.5375
0
0
0
1
1
1
1.3750
1
1
0
0
1
1
0.5250
0
0
1
0
0
0
1.3500
1
1
0
1
0
0
0.5125
0
0
1
0
0
1
1.3250
1
1
0
1
0
1
0.5000
0
0
1
0
1
0
1.3000
1
1
0
1
1
0
0.4875
0
0
1
0
1
1
1.2750
1
1
0
1
1
1
0.4750
0
0
1
1
0
0
1.2500
1
1
1
0
0
0
0.4625
0
0
1
1
0
1
1.2250
1
1
1
0
0
1
0.4500
0
0
1
1
1
0
1.2000
1
1
1
0
1
0
0.4375
0
0
1
1
1
1
1.1750
1
1
1
0
1
1
0.4250
0
1
0
0
0
0
1.1500
1
1
1
1
0
0
0.4125
0
1
0
0
0
1
1.1250
1
1
1
1
0
1
0.4000
0
1
0
0
1
0
1.1000
1
1
1
1
1
0
0.3875
0
1
0
0
1
1
1.0750
1
1
1
1
1
1
0.3750
0
1
0
1
0
0
1.0500
0
1
0
1
0
1
1.0250
Serial VID Interface (SVI)
0
1
0
1
1
0
1.0000
0
1
0
1
1
1
0.9750
0
1
1
0
0
0
0.9500
0
1
1
0
0
1
0.9250
0
1
1
0
1
0
0.9000
0
1
1
0
1
1
0.8750
The on-board Serial VID interface (SVI) circuitry allows the
processor to directly drive the core voltage and Northbridge
voltage reference level within the ISL6323B. The SVC and
SVD states are decoded with direction from the PWROK and
VFIXEN inputs as described in the following sections. The
ISL6323B uses a digital to analog converter (DAC) to
generate a reference voltage based on the decoded SVI
16
FN6879.1
May 12, 2010
ISL6323B
value. See Figure 7 for a simple SVI interface timing
diagram.
VDDPWRGD output transitions high indicating both output
planes are within regulation limits
PRE-PWROK METAL VID
If the EN input falls below the enable falling threshold, the
ISL6323B ramps the internal reference voltage down to near
zero. The VDDPWRGD deasserts with the loss of enable.
The VDD and VDDNB planes will linearly decrease to near
zero.
Typical motherboard start-up occurs with the VFIXEN input
low. The controller decodes the SVC and SVD inputs to
determine the Pre-PWROK metal VID setting. Once the
POR circuitry is satisfied, the ISL6323B begins decoding the
inputs per Table 2. Once the EN input exceeds the rising
enable threshold, the ISL6323B saves the Pre-PWROK
metal VID value in an on-board holding register and passes
this target to the internal DAC circuitry.
TABLE 3. VFIXEN VID CODES
TABLE 2. PRE-PWROK METAL VID CODES
SVC
SVD
OUTPUT VOLTAGE
(V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
2
3
SVD
OUTPUT VOLTAGE
(V)
0
0
1.4
0
1
1.2
1
0
1.0
1
1
0.8
VFIX MODE
In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed
external to the controller through jumpers to either GND or
VDDIO. These inputs are not expected to change, but the
ISL6323B is designed to support the potential change of
state of these inputs. If VFIXEN is high, the IC decodes the
SVC and SVD states per Table 3.
The Pre-PWROK metal VID code is decoded and latched on
the rising edge of the enable signal. Once enabled, the
ISL6323B passes the Pre-PWROK metal VID code on to
internal DAC circuitry. The internal DAC circuitry begins to
ramp both the VDD and VDDNB planes to the decoded
Pre-PWROK metal VID output level. The digital soft-start
circuitry actually stair steps the internal reference to the
target gradually over a fix interval. The controlled ramp of
both output voltage planes reduces in-rush current during
the soft-start interval. At the end of the soft-start interval, the
1
SVC
4
5
Once enabled, the ISL6323B begins to soft-start both VDD
and VDDNB planes to the programmed VFIX level. The
internal soft-start circuitry slowly stair steps the reference up
to the target value and this results in a controlled ramp of the
power planes. Once soft-start has ended and both output
planes are within regulation limits, the VDDPWRGD pin
transitions high. If the EN input falls below the enable falling
6
7
8
9
10
11
12
VCC
SVC
SVD
ENABLE
PWROK
METAL_VID
V_SVI
METAL_VID
V_SVI
VDD AND VDDNB
VDDPWRGD
VFIXEN
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID STAR-TUP
17
FN6879.1
May 12, 2010
ISL6323B
threshold, then the controller ramps both VDD and VDDNB
down to near zero.
SVI MODE
Once the controller has successfully soft-started and
VDDPWRGD transitions high, the Northbridge SVI interface
can assert PWROK to signal the ISL6323B to prepare for
SVI commands. The controller actively monitors the SVI
interface for set VID commands to move the plane voltages
to start-up VID values. Details of the SVI Bus protocol are
provided in the AMD Design Guide for Voltage Regulator
Controllers Accepting Serial VID Codes specification.
Once the set VID command is received, the ISL6323B
decodes the information to determine which plane and the
VID target required (see Table 4). The internal DAC circuitry
steps the required output plane voltage to the new VID level.
During this time one or both of the planes could be targeted.
In the event the core voltage plane, VDD, is commanded to
power off by serial VID commands, the VDDPWRGD signal
remains asserted. The Northbridge voltage plane must
remain active during this time.
If the PWROK input is deasserted, then the controller steps
both VDD and VDDNB planes back to the stored
Pre-PWROK metal VID level in the holding register from
initial soft-start. No attempt is made to read the SVC and
SVD inputs during this time. If PWROK is reasserted, then
the on-board SVI interface waits for a set VID command.
If VDDPWRGD deasserts during normal operation, both
voltage planes are powered down in a controlled fashion.
The internal DAC circuitry stair steps both outputs down to
near zero.
TABLE 4. SERIAL VID CODES
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
000_0000b
1.5500
010_0000b
1.1500
100_0000b
0.7500
110_0000b
0.3500*
000_0001b
1.5375
010_0001b
1.1375
100_0001b
0.7375
110_0001b
0.3375*
000_0010b
1.5250
010_0010b
1.1250
100_0010b
0.7250
110_0010b
0.3250*
000_0011b
1.5125
010_0011b
1.1125
100_0011b
0.7125
110_0011b
0.3125*
000_0100b
1.5000
010_0100b
1.1000
100_0100b
0.7000
110_0100b
0.3000*
000_0101b
1.4875
010_0101b
1.0875
100_0101b
0.6875
110_0101b
0.2875*
000_0110b
1.4750
010_0110b
1.0750
100_0110b
0.6750
110_0110b
0.2750*
000_0111b
1.4625
010_0111b
1.0625
100_0111b
0.6625
110_0111b
0.2625*
000_1000b
1.4500
010_1000b
1.0500
100_1000b
0.6500
110_1000b
0.2500*
000_1001b
1.4375
010_1001b
1.0375
100_1001b
0.6375
110_1001b
0.2375*
000_1010b
1.4250
010_1010b
1.0250
100_1010b
0.6250
110_1010b
0.2250*
000_1011b
1.4125
010_1011b
1.0125
100_1011b
0.6125
110_1011b
0.2125*
000_1100b
1.4000
010_1100b
1.0000
100_1100b
0.6000
110_1100b
0.2000*
000_1101b
1.3875
010_1101b
0.9875
100_1101b
0.5875
110_1101b
0.1875*
000_1110b
1.3750
010_1110b
0.9750
100_1110b
0.5750
110_1110b
0.1750*
000_1111b
1.3625
010_1111b
0.9625
100_1111b
0.5625
110_1111b
0.1625*
001_0000b
1.3500
011_0000b
0.9500
101_0000b
0.5500
111_0000b
0.1500*
001_0001b
1.3375
011_0001b
0.9375
101_0001b
0.5375
111_0001b
0.1375*
001_0010b
1.3250
011_0010b
0.9250
101_0010b
0.5250
111_0010b
0.1250*
001_0011b
1.3125
011_0011b
0.9125
101_0011b
0.5125
111_0011b
0.1125*
001_0100b
1.3000
011_0100b
0.9000
101_0100b
0.5000
111_0100b
0.1000*
001_0101b
1.2875
011_0101b
0.8875
101_0101b
0.4875*
111_0101b
0.0875*
001_0110b
1.2750
011_0110b
0.8750
101_0110b
0.4750*
111_0110b
0.0750*
001_0111b
1.2625
011_0111b
0.8625
101_0111b
0.4625*
111_0111b
0.0625*
001_1000b
1.2500
011_1000b
0.8500
101_1000b
0.4500*
111_1000b
0.0500*
001_1001b
1.2375
011_1001b
0.8375
101_1001b
0.4375*
111_1001b
0.0375*
001_1010b
1.2250
011_1010b
0.8250
101_1010b
0.4250*
111_1010b
0.0250*
18
FN6879.1
May 12, 2010
ISL6323B
TABLE 4. SERIAL VID CODES (Continued)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
001_1011b
1.2125
011_1011b
0.8125
101_1011b
0.4125*
111_1011b
0.0125*
001_1100b
1.2000
011_1100b
0.8000
101_1100b
0.4000*
111_1100b
OFF
001_1101b
1.1875
011_1101b
0.7875
101_1101b
0.3875*
111_1101b
OFF
001_1110b
1.1750
011_1110b
0.7750
101_1110b
0.3750*
111_1110b
OFF
001_1111b
1.1625
011_1111b
0.7625
101_1111b
0.3625*
111_1111b
OFF
NOTE: *Indicates a VID not required for AMD Family 10h processors.
POWER SAVINGS MODE: PSI_L
Bit 7 of the Serial VID codes transmitted as part of the 8-bit
data phase over the SVI bus is allocated for the PSI_L. If
Bit 7 is 0, then the processor is at an optimal load for the
regulator to enter power savings mode. If Bit 7 is 1, then the
regulator should not be in power savings mode.
With the ISL6323B, Power Savings mode is realized through
phase shedding. Once a Serial VID command with Bit 7 set to 0
is received, the ISL6323B will shed all phases in a sequential
manner until only Channel 1 and Channel 2 are switching. If
active, Channel 4 will be shed first, followed by Channel 3.
When a phase is shed, that phase will not go into a tri-state
mode until that phase would have had its PWM go HIGH.
The ISL6323B incorporates differential remote-sense
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output voltage.
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution can help to reduce
the output-voltage spike that results from fast load-current
demand changes.
EXTERNAL CIRCUIT
FS
When leaving Power Savings Mode, through the reception of
a Serial VID command with Bit 7 set to 1, the ISL6323B will
sequentially turn on phases starting with Phase 3. When a
phase is being reactivated, it will not leave a tri-state until the
PWM of that phase goes HIGH.
If, while in Power Savings Mode, a Serial VID command is
received that forces a VID level change while maintaining
Bit 7 at 0, the ISL6323B will first exit the Power Savings
Mode state as described above. The output voltage will then
be stepped up or down to the appropriate VID level. Finally,
the ISL6323B will then re-enter Power Savings Mode.
ISL6323B INTERNAL CIRCUIT
RFS
DROOP
CONTROL
COMP
CC
8 IAVG
RC
IOFS
FB
+
Voltage Regulation
The integrating compensation network shown in Figure 8
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage and offset
errors in the OFS current source, remote-sense and error
amplifiers. Intersil specifies the guaranteed tolerance of the
ISL6323B to include the combined tolerances of each of
these elements.
The output of the error amplifier, VCOMP, is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is equal
to the voltage at REF. This will regulate the output voltage to
be equal to Equation 11. The internal and external circuitry
that controls voltage regulation is illustrated in Figure 8.
V OUT = V REF – V OFS – V DROOP
19
(EQ. 11)
TO
OSCILLATOR
RFB
+
(VDROOP + VOFS)
-
VSEN
+
VOUT
-
VCOMP
ERROR
AMPLIFIER
2k
∑
VID
DAC
RGND
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
FN6879.1
May 12, 2010
ISL6323B
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied to ground, a
current 8x the average current of all active channels, 8*IAVG,
flows from FB through a load-line regulation resistor RFB.
The resulting voltage drop across RFB is proportional to the
output current, effectively creating an output voltage droop
with a steady-state value defined as Equation 12:
V DROOP = I AVG ⋅ R FB
For Negative Offset (connect ROFS to VCC):
1.6 × R FB
R OFS = -------------------------V OFFSET
VDIFF
VOFS
+
RFB
FB
IOFS
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
shown in Equation 13.
In Equation 13, VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current
of the converter, KI is an internal gain determined by the
RSET resistor connected to the RSET pin (KI is defined in
Equation 10), K is the DC gain of the RC filter across the
inductor (K is defined in Equation 7), N is the number of
active channels, and DCR is the Inductor DCR value.
VREF
E/A
(EQ. 12)
⎛ I OUT
⎞
400
1
V OUT = V REF – V OFS – ⎜ ------------- ⋅ DCR ⋅ ⎛ ---------- ⋅ ---------------⎞ ⋅ K ⋅ R FB⎟
⎝ 3 R
⎠
⎝ N
⎠
SET
(EQ. 13)
(EQ. 15)
VCC
-
ROFS
OFS
ISL6323B
-
1.6V
+
+
0.3V
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Output-Voltage Offset Programming
The ISL6323B allows the designer to accurately adjust the
offset voltage by connecting a resistor, ROFS, from the OFS
pin to VCC or GND. When ROFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into the FB pin
and out of the OFS pin. If ROFS is connected to ground, the
voltage across it is regulated to 0.3V, and IOFS flows into the
OFS pin and out of the FB pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product
(IOFS x RFB). These functions are shown in Figures 9 and 10.
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6323B through
either the PVI or SVI interface. The ISL6323B manages the
resulting VID-on-the-Fly transition in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption. The ISL6323B begins slewing the
DAC at 3.25mV/μs until the DAC and target voltage are
equal. Thus, the total time required for a dynamic VID
transition is dependent only on the size of the DAC change.
Once the desired output offset voltage has been determined,
use the following formulas to set ROFS:
For Positive Offset (connect ROFS to GND):
0.3 × R FB
R OFS = -------------------------V OFFSET
(EQ. 14)
20
FN6879.1
May 12, 2010
ISL6323B
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
ISL6323B sets the voltage on the DVC pin to be 2x the
voltage on the REF pin. Since the error amplifier forces the
voltage on the FB pin and the REF pin to be equal, the
resulting voltage across the series RC between DVC and FB
is equal to the REF pin voltage. The RC compensation
components, RDVC and CDVC, can then be selected to
create the desired amount of compensation current.
VOUT
+
VOFS
-
RFB
VREF
E/A
FB
IOFS
+
OFS
0.3V
-
ISL6323B
ROFS
1.6V
+
GND
VCC
GND
FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
To further improve dynamic VID performance, ISL6323B
also implements a proprietary DAC smoothing feature. The
external series RC components connected between DVC
and FB limit any stair-stepping of the output voltage during a
VID-on-the-Fly transition.
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on
the FB pin and the COMP pin causes an AC current to flow
through the error amplifier compensation components from
the FB to the COMP pin. This current then flows through the
feedback resistor, RFB, and can cause the output voltage to
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
during a VID change, a VID-on-the-fly compensation
network is required. This network is composed of a resistor
and capacitor in series, RDVC and CDVC, between the DVC
and the FB pin.
RFB
IDVC = IC
VSEN
IC
IDVC
CC
CDVC
RC
RDVC
DVC
COMP
FB
+
VDAC+RGND
ERROR
AMPLIFIER
ISL6323B INTERNAL CIRCUIT
FIGURE 11. DYNAMIC VID COMPENSATION NETWORK
21
The amount of compensation current required is dependant
on the modulator gain of the system, K1, and the error
amplifier R-C components, RC and CC, that are in series
between the FB and COMP pins. Use Equations 17, 18 and
19 to calculate the RC component values, RDVC and CDVC,
for the VID-on-the-fly compensation network. For these
equations: VIN is the input voltage for the power train; VP-P
is the oscillator ramp amplitude (1.5V); and RC and CC are
the error amplifier R-C components between the FB and
COMP pins.
R RCOMP = A × R C
(EQ. 17)
CC
C RCOMP = -------A
(EQ. 18)
V IN
K1 = -----------V P-P
K1
A = ----------------K1 – 1
(EQ. 16)
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V (forward/reverse
inductor current). At this time the UGATE is released to rise. An
auto-zero comparator is used to correct the rDS(ON) drop in the
phase voltage preventing false detection of the -0.3V phase
level during rDS(ON) conduction period. In the case of zero
current, the UGATE is released after 35ns delay of the LGATE
dropping below 0.5V. When LGATE first begins to transition
low, this quick transition can disturb the PHASE node and
cause a false trip, so there is 20ns of blanking time once
LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
FN6879.1
May 12, 2010
ISL6323B
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
Detect block, the external driver POR checking is supported
by the Enable Comparator.
Initialization
Enable Comparator
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC1_2, PVCC_NB, ISEN3-, and ISEN4- pins. When
the conditions are met, the controller begins soft-start. Once
the output voltage is within the proper window of operation,
the controller asserts PGOOD.
ISL6323B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
PVCC1_2
PVCC_NB
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
When selecting the value of the resistor divider the driver
maximum rising POR threshold should be used for calculating
the proper resistor values. This will prevent improper
sequencing events from creating false trips during soft-start.
10.7kΩ
EN
+
The ISL6323B features a dual function enable input (EN) for
enabling the controller and power sequencing between the
controller and external drivers or another voltage rail. The
enable comparator holds the ISL6323B in shutdown until the
voltage at EN rises above 0.86V. The enable comparator has
about 110mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their rising POR level before the
ISL6323B becomes enabled. The schematic in Figure 12
demonstrates sequencing the ISL6323B with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
1.00kΩ
If the controller is configured for 2-phase CORE operation,
then the resistor divider can be used for sequencing the
controller with another voltage rail. The resistor divider to EN
should be selected using a similar approach as the previous
driver discussion.
0.86V
ISEN3SOFT-START
AND
FAULT LOGIC
CHANNEL
DETECT
ISEN4-
FIGURE 12. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
Power-On Reset
The ISL6323B requires VCC, PVCC1_2, and PVCC_NB
inputs to exceed their rising POR thresholds before the
ISL6323B has sufficient bias to guarantee proper operation.
The bias voltage applied to VCC must reach the internal
power-on reset (POR) rising threshold. Once this threshold
is reached, the ISL6323B has enough bias to begin checking
the driver POR inputs, EN, and channel detect portions of
the initialization cycle. Hysteresis between the rising and
falling thresholds assure the ISL6323B will not advertently
turn off unless the bias voltage drops substantially (see
Electrical Specifications on page 9).
The bias voltage applied to the PVCC1_2 and PVCC_NB
pins power the internal MOSFET drivers of each output
channel. In order for the ISL6323B to begin operation, both
PVCC inputs must exceed their POR rising threshold to
guarantee proper operation of the internal drivers.
Hysteresis between the rising and falling thresholds assure
that once enabled, the ISL6323B will not inadvertently turn
off unless the PVCC bias voltage drops substantially (see
Electrical Specifications on page 9). Depending on the
number of active CORE channels determined by the Phase
22
The EN pin is also used to force the ISL6323B into either
PVI or SVI mode. The mode is set upon the rising edge of
the EN signal. When the voltage on the EN pin rises above
0.86V, the mode will be set depending upon the status of the
VID1/SEL pin.
Phase Detection
The ISEN3- and ISEN4- pins are monitored prior to soft-start
to determine the number of active CORE channel phases.
If ISEN4- is tied to VCC, the controller will configure the
channel firing order and timing for 3-phase operation. If
ISEN3- and ISEN4- are tied to VCC, the controller will set
the channel firing order and timing for 2-phase operation
(see “PWM Operation” on page 14 for details).
Soft-Start Output Voltage Targets
Once the POR and Phase Detect blocks and enable
comparator are satisfied, the controller will begin the
soft-start sequence and will ramp the CORE and NB output
voltages up to the SVI interface designated target level if the
controller is set SVI mode. If set to PVI mode, the North
Bridge regulator is disabled and the core is soft started to the
level designated by the parallel VID code.
SVI Mode
Prior to soft-starting both CORE and NB outputs, the
ISL6323B must check the state of the SVI interface inputs to
determine the correct target voltages for both outputs. When
the controller is enabled, the state of the VFIXEN, SVD and
SVC inputs are checked and the target output voltages set
for both CORE and NB outputs are set by the DAC (see
“Serial VID Interface (SVI)” on page 16). These targets will
FN6879.1
May 12, 2010
ISL6323B
only change if the EN signal is pulled low or after a POR
reset of VCC.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
Soft-Start
The soft-start sequence is composed of three periods, as
shown in Figure 13. At the beginning of soft-start, the DAC
immediately obtains the output voltage targets for both outputs
by decoding the state of the SVI or PVI inputs. A 100µs fixed
delay time, TDA, proceeds the output voltage rise. After this
delay period the ISL6323B will begin ramping both CORE and
NB output voltages to the programmed DAC level at a fixed rate
of 3.25mV/µs. The amount of time required to ramp the output
voltage to the final DAC voltage is referred to as TDB, and can
be calculated as shown in Equation 19.
V DAC
TDB = -----------------------------–3
3.25 × 10
(EQ. 19)
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high.
VNB
400mV/DIV
VCORE
400mV/DIV
TDA
TDB
EN
5V/DIV
VDDPWRGD
5V/DIV
100µs/DIV
FIGURE 13. SOFT-START WAVEFORMS
Pre-Biased Soft-Start
The ISL6323B also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level. Both CORE and NB output support start up into a
pre-charged output.
23
OUTPUT PRECHARGED
BELOW DAC LEVEL
VCORE
400mV/DIV
EN
5V/DIV
100µs/DIV
FIGURE 14. SOFT-START WAVEFORMS FOR
ISL6323B-BASED MULTI-PHASE CONVERTER
Fault Monitoring and Protection
The ISL6323B actively monitors both CORE and NB output
voltages and currents to detect fault conditions. Fault
monitors trigger protective measures to prevent damage to
either load. One common power good indicator is provided
for linking to external system monitors. The schematic in
Figure 15 outlines the interaction between the fault monitors
and the power good signal.
Power-Good Signal
The power-good pin (VDDPWRGD) is an open-drain logic
output that signals whether or not the ISL6323B is regulating
both NB and CORE output voltages within the proper levels,
and whether any fault conditions exist. This pin should be
tied to a +5V source through a resistor.
During shutdown and soft-start, VDDPWRGD pulls low and
releases high after a successful soft-start and both output
voltages are operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is detected
on either regulator output or when the controller is disabled by a
POR reset or EN. In the event of an overvoltage or overcurrent
condition, the controller latches off and PGOOD will not return
high. Pending a POR reset of the ISL6323B and successful
soft-start, the PGOOD will return high.
Overvoltage Protection
The ISL6323B constantly monitors the sensed output voltage
on the VSEN pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level and
exceeds the PGOOD OV limit actions are taken by the
ISL6323B to protect the microprocessor load.
At the inception of an overvoltage event, both on-board lower
gate pins are commanded low as are the active PWM outputs
to the external drivers, the PGOOD signal is driven low, and the
ISL6323B latches off normal PWM action. This turns on the all
of the lower MOSFETs and pulls the output voltage below a
FN6879.1
May 12, 2010
ISL6323B
level that might cause damage to the load. The lower
MOSFETs remain driven ON until VDIFF falls below 400mV.
The ISL6323B will continue to protect the load in this fashion as
long as the overvoltage condition recurs. Once an overvoltage
condition ends the ISL6323B latches off, and must be reset by
toggling POR, before a soft-start can be re-initiated.
Undervoltage Detection
The undervoltage threshold is set at VDAC - 300mV typical.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above VDAC - 250mV typical.
Open Sense Line Protection
-
142µA
OCL
+
100µA
-
INB
+
I1
REPEAT FOR EACH
CORE CHANNEL
OCP
-
100µA
OCP
+
IAVG
CORE ONLY
NB ONLY
+
1.8V
OVP
-
ISEN_NB+
Overcurrent Protection
The ISL6323B takes advantage of the proportionality between
the load current and the average current, IAVG, to detect an
overcurrent condition. See “Continuous Current Sampling” on
page 14 and “Channel-Current Balance” on page 15 for more
detail on how the average current is measured. Once the
average current exceeds 100µA, a comparator triggers the
converter to begin overcurrent protection procedures. The
Core regulator and the North Bridge regulator have the same
type of overcurrent protection.
SOFT-START, FAULT
AND CONTROL LOGIC
NB ONLY
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6323B is designed to detect this
and shut down the controller. This event is detected by
monitoring small currents that are fed out the VSEN and RGND
pins. In the event of an open sense line fault, the controller will
continue to remain off until the fault goes away, at which point
the controller will re-initiate a soft-start sequence.
UV
+
DAC - 300mV
CORE ONLY
+
1.8V
OVP
DAC + 250mV
VDDPWRGD
OV
The overcurrent trip threshold is dictated by the DCR of the
inductors, the number of active channels, the DC gain of the
inductor RC filter and the RSET resistor. The overcurrent trip
threshold is shown in Equation 20.
V IN – N ⋅ V OUT V OUT
N
1
3
I OCP = 100μA ⋅ ------------- ⋅ ---- ⋅ ⎛ ---------- ⋅ R SET⎞ – ---------------------------------------- ⋅ ---------------⎠
V IN
2 ⋅ L ⋅ fS
DCR K ⎝ 400
+
(EQ. 20)
UV
VSEN
+
DAC - 300mV
ISL6323B INTERNAL CIRCUITRY
FIGURE 15. POWER-GOOD AND PROTECTION CIRCUITRY
Where:
R2
K = -------------------R1 + R2
See “Continuous Current Sampling” on
page 14.
fSW = Switching Frequency
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6323B is designed to protect either load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10kΩ resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
24
Equation 20 is valid for both the Core regulator and the
North Bridge regulator. This equation includes the DC load
current as well as the total ripple current contributed by all
the phases. For the North Bridge regulator, N is 1.
During soft-start, the overcurrent trip point is boosted by a factor
of 1.4. Instead of comparing the average measured current to
100µA, the average current is compared to 140µA. Immediately
after soft-start is over, the comparison level changes to 100µA.
This is done to allow for start-up into an active load while still
supplying output capacitor in-rush current.
CORE REGULATOR OVERCURRENT
At the beginning of overcurrent shutdown, the controller sets all
of the UGATE and LGATE signals low, puts PWM3 and PWM4
FN6879.1
May 12, 2010
ISL6323B
(if active) in a high-impedance state, and forces VDDPWRGD
low. This turns off all of the upper and lower MOSFETs. The
system remains in this state for fixed period of 12ms. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start, as shown in Figure 16. If the fault remains,
the trip-retry cycles will continue until either the fault is cleared
or for a total of seven attempts. If the fault is not cleared on the
final attempt, the controller disables UGATE and LGATE
signals for both Core and North Bridge and latches off requiring
a POR of VCC to reset the ISL6323B.
OVERCURRENT PROTECTION IN POWER SAVINGS
MODE
While in Power Savings Mode, the OCP trip point will be
lower than when running in Normal Mode. Equation 20, with
N = 1, will yield the OCP trip point for the Core regulator
while in Power Savings mode.
If an overcurrent event should occur while the system is in
Power Savings Mode, the ISL6323B will restart in the
Normal state with the PSI_L bit set to 1.
Individual Channel Overcurrent Limiting
OUTPUT CURRENT, 50A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
The ISL6323B has the ability to limit the current in each
individual channel of the Core regulator without shutting
down the entire regulator. This is accomplished by
continuously comparing the sensed currents of each channel
with a constant 140µA OCL reference current. If a channel’s
individual sensed current exceeds this OCL limit, the UGATE
signal of that channel is immediately forced low, and the
LGATE signal is forced high. This turns off the upper
MOSFET(s), turns on the lower MOSFET(s), and stops the
rise of current in that channel, forcing the current in the
channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel current falls
back below the 140µA reference.
3ms/DIV
FIGURE 16. OVERCURRENT BEHAVIOR IN HICCUP MODE
It is important to note that during soft start, the overcurrent
trip point is increased by a factor of 1.4. If the fault draws
enough current to trip overcurrent during normal run mode, it
may not draw enough current during the soft start ramp
period to trip overcurrent while the output is ramping up. If a
fault of this type is affecting the output, then the regulator will
complete soft start and the trip-retry counter will be reset to
zero. Once the regulator has completed soft start, the
overcurrent trip point will return to it’s nominal setting and an
overcurrent shutdown will be initiated. This will result in a
continuous hiccup mode.
Note that the energy delivered during trip-retry cycling is
much less than during full-load operation, so there is no
thermal hazard.
NORTH BRIDGE REGULATOR OVERCURRENT
The overcurrent shutdown sequence for the North Bridge
regulator is identical to the Core regulator with the exception
that it is a single phase regulator and will only disable the
MOSFET drivers for the North Bridge. Once 7 retry attempts
have been executed unsuccessfully, the controller will disable
UGATE and LGATE signals for both Core and North Bridge and
will latch off requiring a POR of VCC to reset the ISL6323B.
Note that the energy delivered during trip-retry cycling is
much less than during full-load operation, so there is no
thermal hazard.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination depends
heavily on the cost analysis which in turn depends on system
constraints that differ from one design to the next. Principally,
the designer will be concerned with whether components can
be mounted on both sides of the circuit board, whether
through-hole components are permitted, the total board space
available for power-supply circuitry, and the maximum amount
of load current. Generally speaking, the most economical
solutions are those in which each phase handles between
25A and 30A. All surface-mount designs will tend toward the
lower end of this current range. If through-hole MOSFETs and
inductors can be used, higher per-phase currents are
possible. In cases where board space is the limiting
constraint, current can be pushed as high as 40A per phase,
but these designs require heat sinks and forced air to cool the
MOSFETs, inductors and heat-dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
25
FN6879.1
May 12, 2010
ISL6323B
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(rDS(ON)). In Equation 21, IM is the maximum continuous
output current, IP-P is the peak-to-peak inductor current
(see Equation 2), and d is the duty cycle (VOUT/VIN).
I L, 2PP ⋅ ( 1 – d )
⎛ I M⎞ 2
P LOW, 1 = r DS ( ON ) ⋅ ⎜ -----⎟ ⋅ ( 1 – d ) + ------------------------------------12
⎝ N⎠
(EQ. 21)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON), the switching
frequency, fS, and the length of dead times, td1 and td2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
⎛I
⎞
⎛I
⎞
(EQ. 22)
⎟
M I P-P⎟ ⋅ t
M I----------P LOW, 2 = V D ( ON ) ⋅ f S ⋅ ⎜ -----+ ⎜ -----+ ----------– P-P⎟ ⋅ t d2
2 ⎠
⎝N
2 ⎠ d1 ⎜⎝ N
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of PLOW,1 and PLOW,2.
UPPER MOSFET POWER CALCULATION
In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times,
the lower-MOSFET body-diode reverse-recovery charge, Qrr,
and the upper MOSFET rDS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 23,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
I M I P-P⎞ ⎛ t 1 ⎞
P UP,1 ≈ V IN ⋅ ⎛ ----- ⋅ ⎜ ---- ⎟ ⋅ f
⎝ N- + --------2 ⎠ ⎝ 2⎠ S
(EQ. 23)
A third component involves the lower MOSFET
reverse-recovery charge, Qrr. Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Qrr, it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is PUP,3.
P UP,3 = V IN ⋅ Q rr ⋅ f S
(EQ. 25)
Finally, the resistive part of the upper MOSFET is given in
Equation 26 as PUP,4.
2
2
I P-P
⎛ I M⎞
P UP,4 ≈ r DS ( ON ) ⋅ ⎜ -----⎟ ⋅ d + ---------12
⎝ N⎠
(EQ. 26)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 23, 24, 25 and 26. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 27:
Q GATE
C BOOT_CAP ≥ -------------------------------------ΔV BOOT_CAP
Q G1 • PVCC
Q GATE = ------------------------------------ • N Q1
V GS1
(EQ. 27)
where QG1 is the amount of gate charge per upper MOSFET
at VGS1 gate-source voltage and NQ1 is the number of
control MOSFETs. The ΔVBOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
Gate Drive Voltage Versatility
The ISL6323B provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 24, the
approximate power loss is PUP,2.
⎛ I M I P-P⎞
P UP, 2 ≈ V IN ⋅ ⎜ ----- – ----------⎟
2 ⎠
⎝N
⎛t ⎞
⋅ ⎜ ----2 ⎟ ⋅ f S
⎝ 2⎠
26
(EQ. 24)
FN6879.1
May 12, 2010
ISL6323B
In Equations 28 and 29, PQg_Q1 is the total upper gate drive
power loss and PQg_Q2 is the total lower gate drive power
loss; the gate charge (QG1 and QG2) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; IQ is the driver total
quiescent current with no load at both drive outputs; NQ1 and
NQ2 are the number of upper and lower MOSFETs per phase,
respectively; NPHASE is the number of active phases. The
IQ*VCC product is the quiescent power of the controller
without capacitive load and is typically 75mW at 300kHz.
1.6
1.4
CBOOT_CAP (µF)
1.2
1.0
0.8
0.6
QGATE = 100nC
PVCC
0.4
BOOT
50nC
0.2
D
20nC
0.0
0.0
0.1
CGD
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
RHI1
1.0
ΔVBOOT_CAP (V)
G
UGATE
RLO1
RG1
CDS
RGI1
FIGURE 17. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
CGS
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See “Layout Considerations” on
page 33 for thermal transfer improvement suggestions.
When designing the ISL6323B into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
PQg_TOT, due to the gate charge of MOSFETs and the
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 28
and 29, respectively.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ⋅ VCC
(EQ. 28)
3
P Qg_Q1 = --- ⋅ Q G1 ⋅ PVCC ⋅ F SW ⋅ N Q1 ⋅ N PHASE
2
27
PHASE
FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
CGD
RHI2
RLO2
LGATE
G
RG2
CDS
RGI2
CGS
Q2
S
FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance (PDR_UP), the lower drive path resistance
(PDR_UP), and in the boot strap diode (PBOOT). The rest of
the power will be dissipated by the external gate resistors
(RG1 and RG2) and the internal gate resistors (RGI1 and
RGI2) of the MOSFETs. Figures 18 and 19 show the typical
upper and lower gate drives turn-on transition path. The total
power dissipation in the controller itself, PDR, can be roughly
estimated as Equation 30:
Inductor DCR Current Sensing Component
Selection and RSET Value Calculation
P Qg_Q2 = Q G2 ⋅ PVCC ⋅ F SW ⋅ N Q2 ⋅ N PHASE
3
+ Q G2 ⋅ N Q2⎞ ⋅ N PHASE ⋅ F SW + I Q
I DR = ⎛ --- ⋅ Q G1 ⋅ N
⎝2
⎠
Q1
Q1
S
(EQ. 29)
With the single RSET resistor setting the value of the
effective internal sense resistors for both the North Bridge
and Core regulators, it is important to set the RSET value
and the inductor RC filter gain, K, properly. See “Continuous
Current Sampling” on page 14 and “Channel-Current
Balance” on page 15 for more details on the application of
the RSET resistor and the RC filter gain.
FN6879.1
May 12, 2010
ISL6323B
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ⋅ VCC )
(EQ. 30)
P Qg_Q1
P BOOT = --------------------3
R LO1
R HI1
⎛
⎞ P Qg_Q1
P DR_UP = ⎜ -------------------------------------- + ----------------------------------------⎟ ⋅ --------------------3
⎝ R HI1 + R EXT1 R LO1 + R EXT1⎠
R GI2
R EXT2 = R G2 + ------------N Q2
For all three cases, use the expected VID voltage that would
be used at TDC for Core and North Bridge for the VCORE
and VNB variables, respectively.
CASE 1
I Core
MAX
⋅ DCR NB < -------------------------- ⋅ DCR Core
N
MAX
(EQ. 35)
R1
⋅ R2
L Core
Core
Core
------------------------- = ---------------------------------------------⋅ C Core
DCR Core
+ R2
R1
Core
Core
(EQ. 36)
Core
CASE 2
There are 3 separate cases to consider when calculating these
component values. If the system under design will never utilize
the North Bridge regulator and the ISL6323 will always be in
parallel mode, then follow the instructions for Case 3 and only
calculate values for Core regulator components.
I NB
R2
Core
K = ---------------------------------------------R1
+ R2
Core
R LO2
R HI2
⎛
⎞ P Qg_Q2
P DR_LOW = ⎜ -------------------------------------- + ----------------------------------------⎟ ⋅ --------------------2
⎝ R HI2 + R EXT2 R LO2 + R EXT2⎠
R GI1
R EXT1 = R G1 + ------------N Q1
6. Calculate the values for R1 and R2 for Core.
Equations 35 and 36 will allow for their computation.
(EQ. 31)
I NB
I Core
MAX
⋅ DCR NB > -------------------------- ⋅ DCR Core
N
MAX
(EQ. 37)
In Case 2, the DC voltage across the North Bridge inductor
at full load is greater than the DC voltage across a single
phase of the Core regulator while at full load. Here, the DC
voltage across the North Bridge inductor must be scaled
down to match the DC voltage across the Core inductors,
which will be impressed across the ISEN pins without any
gain. So, the R2 resistor for the Core inductor RC filters is
left unpopulated and K = 1.
1. Choose a capacitor value for the Core RC filter. A 0.1µF
capacitor is a recommended starting point.
2. Calculate the value for resistor R1:
In Case 1, the DC voltage across the North Bridge inductor
at full load is less than the DC voltage across a single phase
of the Core regulator while at full load. Here, the DC voltage
across the Core inductors must be scaled down to match the
DC voltage across the North Bridge inductor, which will be
impressed across the ISEN_NB pins without any gain. So,
the R2 resistor for the North Bridge inductor RC filter is left
unpopulated and K = 1.
1. Choose a capacitor value for the North Bridge RC filter. A
0.1µF capacitor is a recommended starting point.
2. Calculate the value for resistor R1 using Equation 32:
R1
L NB
= -------------------------------------DCR NB ⋅ C NB
NB
(EQ. 32)
R1
Core
L Core
= -----------------------------------------------DCR Core ⋅ C Core
3. Calculate the value for the RSET resistor using Equation 39
(Derived from Equation 20).
V IN – V CORE V CORE⎞
400 DCR CORE ⋅ K ⎛
R SET = ---------- ⋅ --------------------------------------- ⋅ ⎜ I OCP
+ ------------------------------------------- ⋅ --------------------⎟
100μA ⋅ N
V IN ⎠
3
CORE 2 ⋅ L CORE ⋅ f SW
⎝
(EQ. 39)
Where: K = 1
4. Using Equation 40 (also derived from Equation 20),
calculate the value of K for the North bridge regulator.
100μA
1
3
K = ---------- ⋅ R SET ⋅ --------------------- ⋅ ------------------------------------------------------------------------------V IN – V NB V NB
DCR NB
400
I OCP
+ ---------------------------------- ⋅ ----------NB 2 ⋅ L NB ⋅ f SW V IN
3. Calculate the value for the RSET resistor using
Equation 33: (Derived from Equation 20).
(EQ. 40)
V IN – V NB V NB⎞
400 DCR NB ⋅ K ⎛
+ ---------------------------------- ⋅ -----------⎟
R SET = ---------- ⋅ ------------------------------ ⋅ ⎜ I OCP
100μA
2
⋅ L NB ⋅ f SW V IN ⎠
3
NB
⎝
(EQ. 33)
Where: K = 1
(EQ. 38)
4. Using Equation 34 (also derived from Equation 20),
calculate the value of K for the Core regulator.
100μA
N
3
K = ---------- ⋅ R SET ⋅ ------------------------------ ⋅ ----------------------------------------------------------------------------------------------------------V IN – N ⋅ V CORE V CORE
DCR CORE
400
I OCP
+ --------------------------------------------- ⋅ -------------------V IN
CORE 2 ⋅ L CORE ⋅ f SW
(EQ. 34)
5. Choose a capacitor value for the North Bridge RC filter. A
0.1µF capacitor is a recommended starting point.
6. Calculate the values for R1 and R2 for North Bridge.
Equations 41 and 42 will allow for their computation.
R2
NB
K = ------------------------------------R1
+ R2
(EQ. 41)
R1
⋅ R2
L NB
NB
NB
--------------------= ------------------------------------- ⋅ C NB
DCR NB
+ R2
R1
NB
NB
(EQ. 42)
NB
NB
5. Choose a capacitor value for the Core RC filters. A 0.1µF
capacitor is a recommended starting point.
28
FN6879.1
May 12, 2010
ISL6323B
For this Case, it is recommended that the overcurrent trip
point for the North Bridge regulator be equal to the
overcurrent trip point for the Core regulator divided by the
number of core phases.
1. Choose a capacitor value for the North Bridge RC filter. A
0.1µF capacitor is a recommended starting point.
Inductor DCR Current Sensing Component Fine
Tuning
I
VIN
L
n
UGATE(n)
L
MOSFET
DRIVER
LGATE(n)
DCR
VOUT
INDUCTOR
+
In Case 3, the DC voltage across the North Bridge inductor
at full load is equal to the DC voltage across a single phase
of the Core regulator while at full load. Here, the full scale
DC inductor voltages for both North Bridge and Core will be
impressed across the ISEN pins without any gain. So, the R2
resistors for the Core and North Bridge inductor RC filters
are left unpopulated and K = 1 for both regulators.
VL(s)
+
(EQ. 43)
Core inductors must be set up with proper gain. This gain
will represent the variable “K” in all equations. It is also very
important that the RSET resistor be tied between the RSET
pin and the VCC pin of the ISL6323.
R1
COUT
VC(s)
-
I Core
MAX
I NB
⋅ DCR NB = -------------------------- ⋅ DCR Core
N
MAX
-
CASE 3
C
R2
ISL6323B INTERNAL CIRCUIT
2. Calculate the value for the North Bridge resistor R1:
NB
L NB
= -------------------------------------DCR NB ⋅ C NB
(EQ. 44)
3. Choose a capacitor value for the Core RC filter. A 0.1µF
capacitor is a recommended starting point.
5. Calculate the value for the Core resistor R1:
L Core
= -----------------------------------------------R1
DCR Core ⋅ C Core
Core
In
KI
40kΩ
K I = ----------------R SET
SAMPLE
(EQ. 45)
+
+
-
6. Calculate the value for the RSET resistor using Equation 46:
V IN – V CORE V CORE⎞
400 DCR CORE ⋅ K ⎛
R SET = ---------- ⋅ --------------------------------------- ⋅ ⎜ I OCP
+ ------------------------------------------- ⋅ --------------------⎟
100μA ⋅ N
2
⋅ L CORE ⋅ f SW
V IN ⎠
3
CORE
⎝
(EQ. 46)
Where: K = 1
7. Calculate the OCP trip point for the North Bridge regulator
using Equation 47. If the OCP trip point is higher than
desired, then the component values must be recalculated
utilizing Case 1. If the OCP trip point is lower than desired,
then the component values must be recalculated utilized
Case 2.
I OCP
V IN – V NB V NB
3
1
= 100μA ⋅ --------------------- ⋅ ⎛ ---------- ⋅ R SET⎞ + ---------------------------------- ⋅ ----------⎝
⎠
⋅ L NB ⋅ f SW V IN
400
2
DCR
NB
NB
(EQ. 47)
NOTE: The values of RSET must be greater than 20kΩ and
less than 80kΩ. For all of the 3 cases, if the calculated value
of RSET is less than 20kΩ, then either the OCP trip point
needs to be increased or the inductor must be changed to an
inductor with higher DCR. If the RSET resistor is greater than
80kΩ, then a value of RSET that is less than 80kΩ must be
chosen and a resistor divider across both North Bridge and
29
VC(s)
RISEN
2.4kΩ
-
R1
ISENnISENn+
ISEN
RSET
VCC
RSET
FIGURE 20. DCR SENSING CONFIGURATION
Due to errors in the inductance and/or DCR it may be
necessary to adjust the value of R1 and R2 to match the time
constants correctly. The effects of time constant mismatch
can be seen in the form of droop overshoot or undershoot
during the initial load transient spike, as shown in Figure 21.
Follow the steps below to ensure the R-C and inductor
L/DCR time constants are matched accurately.
1. If the regulator is not utilizing droop, modify the circuit by
placing the frequency set resistor between FS and
Ground for the duration of this procedure.
2. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1µH and
DCR = 1mΩ, set the oscilloscope to 500µs/div.
3. Record ΔV1 and ΔV2 as shown in Figure 21.
FN6879.1
May 12, 2010
ISL6323B
C2 (OPTIONAL)
ΔV2
RC
ΔV1
VOUT
CC
COMP
FB
ISL6323B
RFB
ITRAN
VSEN
ΔI
FIGURE 22. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6323B CIRCUIT
FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR
4. Select new values, R1,NEW and R2,NEW, for the time
constant resistors based on the original values, R1,OLD
and R2,OLD, using Equations 48 and 49.
ΔV 1
(EQ. 48)
R 1, NEW = R 1, OLD ⋅ ----------ΔV 2
ΔV 1
R 2, NEW = R 2, OLD ⋅ ----------ΔV 2
(EQ. 49)
5. Replace R1 and R2 with the new values and check to see
that the error is corrected. Repeat the procedure if
necessary.
Loadline Regulation Resistor
The loadline regulation resistor, labeled RFB in Figure 8,
sets the desired loadline required for the application.
Equation 50 can be used to calculate RFB.
V DROOP
MAX
R FB = --------------------------------------------------------------------I OUT
400
MAX DCR
---------- ⋅ -------------------------- ⋅ --------------- ⋅ K
N
R SET
3
(EQ. 50)
Where RISEN is the 2.4kΩ internal current sense resistor, KI
is defined in Equation 10 and K is defined in Equation 7.
If no loadline regulation is required, FS resistor should be
tied between the FS pin and VCC. To choose the value for
RFB in this situation, please refer to “Compensation Without
Loadline Regulation” on page 31.
Compensation With Loadline Regulation
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
30
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f0.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equation 51, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and VPP is the
peak-to-peak sawtooth signal amplitude as described in the
Electrical Specifications on page 9.
Once selected, the compensation values in Equation 51
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equation 51 unless some performance issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 22). Keep
a position available for C2, and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
FN6879.1
May 12, 2010
ISL6323B
.
Case 1:
C ⋅ ESR
R 1 = R FB ⋅ -------------------------------------------L ⋅ C – C ⋅ ESR
1
-------------------------------- > f 0
2⋅π⋅ L⋅C
2 ⋅ π ⋅ f 0 ⋅ V P-P ⋅ L ⋅ C
R C = R FB ⋅ ---------------------------------------------------------0.66 ⋅ V IN
L ⋅ C – C ⋅ ESR
C 1 = -------------------------------------------R FB
0.66 ⋅ V IN
C C = ---------------------------------------------------2 ⋅ π ⋅ V PP ⋅ R FB ⋅ f 0
Case 2:
0.75 ⋅ V IN
C 2 = ---------------------------------------------------------------------------------------------------( 2 ⋅ π ) 2 ⋅ f 0 ⋅ f HF ⋅ ( L ⋅ C ) ⋅ R FB ⋅ V P-P
(EQ. 52)
1
1
-------------------------------- ≤ f 0 < -----------------------------------2 ⋅ π ⋅ C ⋅ ESR
2⋅π⋅ L⋅C
2
V P-P ⋅ ( 2 ⋅ π ) 2 ⋅ f 02 ⋅ L ⋅ C
R C = R FB ⋅ -----------------------------------------------------------------0.66 ⋅ V IN
(EQ. 51)
0.66 ⋅ V IN
C C = ------------------------------------------------------------------------------------2
2
( 2 ⋅ π ) ⋅ f 0 ⋅ V PP ⋅ R FB ⋅ L ⋅ C
Case 3:
1
f 0 > ------------------------------------2 ⋅ π ⋅ C ⋅ ESR
V P-P ⋅ ⎛ 2π⎞ ⋅ f 0 ⋅ f HF ⋅ L ⋅ C ⋅ R FB
⎝ ⎠
R C = ----------------------------------------------------------------------------------------0.75 ⋅ V IN ⋅ ( 2 ⋅ π ⋅ f HF ⋅ L ⋅ C – 1 )
0.75 ⋅ V IN ⋅ ( 2 ⋅ π ⋅ f HF ⋅ L ⋅ C – 1 )
C C = ---------------------------------------------------------------------------------------------------( 2 ⋅ π ) 2 ⋅ f 0 ⋅ f HF ⋅ ( L ⋅ C ) ⋅ R FB ⋅ V P-P
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 53, RFB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 53.
2 ⋅ π ⋅ f 0 ⋅ V P-P ⋅ L
R C = R FB ⋅ ---------------------------------------------0.66 ⋅ V IN ⋅ ESR
0.66 ⋅ V IN ⋅ ESR ⋅ C
C C = ----------------------------------------------------------------2 ⋅ π ⋅ V P-P ⋅ R FB ⋅ f 0 ⋅ L
Compensation Without Loadline Regulation
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 23, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, fHF. This pole can be used for added
noise rejection or to assure adequate attenuation at the erroramplifier high-order pole and zero frequencies. A good general
rule is to choose fHF = 10f0, but it can be higher if desired.
Choosing fHF to be lower than 10f0 can cause problems with
too much phase shift below the system bandwidth.
In Equation 53, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in Electrical
Specifications on page 9.
Case 1:
2 ⋅ π ⋅ f 0 ⋅ V P-P ⋅ L ⋅ C
R C = R FB ⋅ ---------------------------------------------------------0.66 ⋅ V
IN
0.66 ⋅ V IN
C C = --------------------------------------------------2 ⋅ π ⋅ V PP ⋅ R FB ⋅ f 0
Case 2:
(EQ. 53)
0.66 ⋅ V IN
C C = ------------------------------------------------------------------------------------( 2 ⋅ π ) 2 ⋅ f 02 ⋅ V PP ⋅ R FB ⋅ L ⋅ C
CC
COMP
Case 3:
FB
C1
R1
1
1
-------------------------------- ≤ f 0 < -----------------------------------2 ⋅ π ⋅ C ⋅ ESR
2⋅π⋅ L⋅C
V P-P ⋅ ( 2 ⋅ π ) 2 ⋅ f 02 ⋅ L ⋅ C
R C = R FB ⋅ -----------------------------------------------------------------0.66 ⋅ V IN
C2
RC
1
-------------------------------- > f 0
2⋅π⋅ L⋅C
ISL6323B
RFB
VSEN
1
f 0 > ------------------------------------2 ⋅ π ⋅ C ⋅ ESR
2 ⋅ π ⋅ f 0 ⋅ V P-P ⋅ L
R C = R FB ⋅ ---------------------------------------------0.66 ⋅ V IN ⋅ ESR
0.66 ⋅ V IN ⋅ ESR ⋅ C
C C = ----------------------------------------------------------------2 ⋅ π ⋅ V P-P ⋅ R FB ⋅ f 0 ⋅ L
FIGURE 23. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
31
FN6879.1
May 12, 2010
ISL6323B
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔVMAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
as shown in Equation 54
di
ΔV ≈ ESL ⋅ ----- + ESR ⋅ ΔI
dt
(EQ. 54)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔVMAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 12 and Equation 3), a voltage develops across the bulk
capacitor ESR equal to IC(P-P ) (ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
32
voltage, VP-P(MAX), determines the lower limit on the
inductance..
⎛V – N ⋅ V
⎞
OUT⎠ ⋅ V OUT
⎝ IN
L ≥ ESR ⋅ -------------------------------------------------------------------f S ⋅ V IN ⋅ V P-P( MAX )
(EQ. 55)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔVMAX. This places an upper limit on inductance.
Equation 56 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 57
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
2 ⋅ N ⋅ C ⋅ VO
L ≤ --------------------------------- ⋅ ΔV MAX – ( ΔI ⋅ ESR )
( ΔI ) 2
(EQ. 56)
1.25 ⋅ N ⋅ C- ⋅ ΔV
⎛
⎞
L ≤ ---------------------------MAX – ( ΔI ⋅ ESR ) ⋅ ⎝ V IN – V O⎠
( ΔI ) 2
(EQ. 57)
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 25, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 32. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT. Figure 24 and Equation 58
are provided to assist in selecting the correct value for RT.
R T = 10
[10.61 – ( 1.035 ⋅ log ( f S ) ) ]
(EQ. 58)
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
FN6879.1
May 12, 2010
ISL6323B
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
RT (kΩ)
1k
100
10
10k
100k
1M
10M
SWITCHING FREQUENCY (Hz)
IL(P-P) = 0.25 IO
IL(P-P) = 0.75 IO
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0.3
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
For a four-phase design, use Figure 25 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (IO), and the ratio
of the peak-to-peak inductor current (IL(P-P)) to IO. Select a
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated.
The voltage rating of the capacitors should also be at least
1.25x greater than the maximum input voltage. Figures 26 and
27 provide the same input RMS current information for 3-phase
and two-phase designs respectively. Use the same approach
for selecting the bulk capacitor type and number.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result from
the high current slew rate produced by the upper MOSFET
turn on and off. Select low ESL ceramic capacitors and place
one as close as possible to each upper MOSFET drain to
minimize board parasitics and maximize suppression.
33
INPUT-CAPACITOR CURRENT (IRMS/IO)
INPUT-CAPACITOR CURRENT (IRMS/IO)
IL(P-P) = 0
IL(P-P) = 0.25 IO
IL(P-P) = 0.5 IO
0.2
FIGURE 24. RT vs SWITCHING FREQUENCY
0.3
IL(P-P) = 0
0.2
0.1
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
selection, layout, and placement minimizes these voltage
spikes. Consider, as an example, the turnoff transition of the
upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel current. During the turnoff, current
stops flowing in the upper MOSFET and is picked up by the
lower MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
FN6879.1
May 12, 2010
ISL6323B
There are two sets of critical components in a DC/DC
converter using a ISL6323B controller. The power
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
The power components should be placed first, which include
the MOSFETs, input and output capacitors, and the inductors. It
is important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally
across all power trains. Equidistant placement of the controller
to the CORE and NB power trains it controls through the
integrated drivers helps keep the gate drive traces equally
short, resulting in equal trace impedances and similar drive
capability of all sets of MOSFETs.
When placing the MOSFETs try to keep the source of the
upper FETs and the drain of the lower FETs as close as
thermally possible. Input high-frequency capacitors, CHF,
should be placed close to the drain of the upper FETs and the
source of the lower FETs. Input bulk capacitors, CBULK, case
size typically limits following the same rule as the
high-frequency input capacitors. Place the input bulk
capacitors as close to the drain of the upper FETs as possible
and minimize the distance to the source of the lower FETs.
Locate the output inductors and output capacitors between the
MOSFETs and the load. The high-frequency output decoupling
capacitors (ceramic) should be placed as close as practicable
to the decoupling target, making use of the shortest connection
paths to any internal planes, such as vias to GND next or on the
capacitor solder pad.
The critical small components include the bypass capacitors
(CFILTER) for VCC and PVCC, and many of the components
surrounding the controller including the feedback network
and current sense components. Locate the VCC/PVCC
bypass capacitors as close to the ISL6323B as possible. It is
especially important to locate the components associated
with the feedback circuit close to their respective controller
pins, since they belong to a high-impedance circuit loop,
sensitive to EMI pick-up.
A multi-layer printed circuit board is recommended. Figure 28
shows the connections of the critical components for the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually the one underneath the component side of the
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from the
PHASE terminal to output inductors short. The power plane
should support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
the phase nodes. Use the remaining printed circuit layers for
small signal wiring.
Routing UGATE, LGATE, and PHASE Traces
Great attention should be paid to routing the UGATE, LGATE,
and PHASE traces since they drive the power train MOSFETs
using short, high current pulses. It is important to size them as
large and as short as possible to reduce their overall
impedance and inductance. They should be sized to carry at
least one ampere of current (0.02” to 0.05”). Going between
layers with vias should also be avoided, but if so, use two vias
for interconnection when possible.
Extra care should be given to the LGATE traces in particular
since keeping their impedance and inductance low helps to
significantly reduce the possibility of shoot-through. It is also
important to route each channels UGATE and PHASE traces
in as close proximity as possible to reduce their inductances.
Current Sense Component Placement and
Trace Routing
One of the most critical aspects of the ISL6323B regulator
layout is the placement of the inductor DCR current sense
components and traces. The R-C current sense components
must be placed as close to their respective ISEN+ and
ISEN- pins on the ISL6323B as possible.
The sense traces that connect the R-C sense components to
each side of the output inductors should be routed on the
bottom of the board, away from the noisy switching
components located on the top of the board. These traces
should be routed side by side, and they should be very thin
traces. It’s important to route these traces as far away from
any other noisy traces or planes as possible. These traces
should pick up as little noise as possible.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
GND pad of the ISL6323B to the ground plane with multiple
vias is recommended. This heat spreading allows the part to
achieve its full thermal potential. It is also recommended
that the controller be placed in a direct path of airflow if
possible to help thermally manage the part.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
34
FN6879.1
May 12, 2010
ISL6323B
RFB
C2
+12V
+12V
CC
RC
FB
CIN
VSEN
R3_2
CBOOT
CBOOT
COMP
C3
BOOT1
ISEN3+
ISEN3-
CIN
BOOT1
R3_1
UGATE1
UGATE1
PWM3
PHASE1
PHASE1
RAPA
R1_1
CAPA
C1
LGATE1
LGATE1
APA
PGND
PWM1
R1_2
ISEN1ISEN1+
DVC
ISL6614
+12V
+12V
V_CORE
+5V
+12V
PVCC1_2
CIN
CFILTER
CFILTER
VCC
CBOOT
BOOT2
ROFS
CBULK
UGATE2
CPU
LOAD
PHASE2
PWM2
C2
C4
R2_2
R4_2
R2_1
R4_1
LGATE2
LGATE2
RSET
VFIXEN
SEL
SVD
ISEN2ISEN2+
SVC
VID4
VID5
PWROK
NC
NC
GND
PHASE2
RFS
RSET
CFILTER
CHF
UGATE2
FS
+5V
CIN
CBOOT
OFS
VCC
PVCC
BOOT2
RGND
VDDPWRGD
ISEN4+
GND
ISEN4-
PWM4
+12V
ISL6323B
REN1
OFF
+12V
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
PVCC_NB
CIN
CFILTER
EN
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
CBOOT_NB
ON
BOOT_NB
REN2
VIA CONNECTION TO GROUND PLANE
UGATE_NB
V_NB
PHASE_NB
R1_NB
LGATE_NB
ISEN_NBISEN_NB+
COMP_NB
FB_NB
C2_NB
RC_NB
CC_NB
C1_NB
CBULK
CHF
R2_NB
RED COMPONENTS:
LOCATE CLOSE TO IC TO
MINIMIZE CONNECTION PATH
NB
LOAD
BLUE COMPONENTS:
LOCATE NEAR LOAD
(MINIMIZE CONNECTION PATH)
MAGENTA COMPONENTS:
LOCATE CLOSE TO SWITCHING TRANSISTORS
(MINIMIZE CONNECTION PATH)
RFB_NB
FIGURE 28. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
35
FN6879.1
May 12, 2010
ISL6323B
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
4 . 30 )
C
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
36
FN6879.1
May 12, 2010
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