DATASHEET

HIP6018
TM
Data Sheet
April 1999
Advanced PWM and Dual Linear Power
Control
Features
The HIP6018 provides the power control and protection for
three output voltages in high-performance microprocessor
and computer applications. The IC integrates a PWM
controllers, a linear regulator and a linear controller as well
as the monitoring and protection functions into a single
package. The PWM controller regulates the microprocessor
core voltage with a synchronous-rectified buck converter.
The linear controller regulates power for the GTL bus and
the linear regulator provides power for the clock driver circuit.
The HIP6018 includes an Intel-compatible, TTL 5-input
digital-to-analog converter (DAC) that adjusts the core PWM
output voltage from 2.1VDC to 3.5VDC in 0.1V increments
and from 1.8VDC to 2.05VDC in 0.05V steps. The precision
reference and voltage-mode control provide ±1% static
regulation. The linear regulator uses an internal pass device
to provide 2.5V±2.5%. The linear controller drives an
external N-channel MOSFET to provide 1.5V±2.5%.
The HIP6018 monitors all the output voltages. A single
Power Good signal is issued when the core is within ±10% of
the DAC setting and the other levels are above their undervoltage levels. Additional built-in over-voltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM overcurrent function monitors the output current by using the
voltage drop across the upper MOSFET’s rDS(ON),
eliminating the need for a current sensing resistor.
PART NUMBER
HIP6018CB
HIP6018EVAL1
0 to 70
• Provides 3 Regulated Voltages
- Microprocessor Core, Clock and GTL Power
• Drives N-Channel MOSFETs
• Operates from +3.3V, +5V and +12V Inputs
• Simple Single-Loop PWM Control Design
- Voltage-Mode Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratios
• Excellent Output Voltage Regulation
- Core PWM Output: ±1% Over Temperature
- Other Outputs: ±2.5% Over Temperature
• TTL-compatible 5-Bit Digital-to-Analog Core Output
Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . 1.8VDC to 3.5VDC
- 0.1V Steps . . . . . . . . . . . . . . . . . . . . 2.1VDC to 3.5VDC
- 0.05V Steps . . . . . . . . . . . . . . . . . . 1.8VDC to 2.05VDC
• Power-Good Output Voltage Monitor
• Microprocessor Core Voltage Protection Against Shorted
MOSFET
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element,
Uses MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator; Programmable from
50kHz to over 1MHz
Applications
Ordering Information
TEMP. RANGE
(oC)
PACKAGE
24 Ld SOIC
PKG.
NO.
M24.3
• Full Motherboard Power Regulation for Computers
• Low-Voltage Distributed Power Supplies
Pinout
HIP6018 (SOIC)
TOP VIEW
Evaluation Board
VCC 1
24 UGATE1
VID4 2
23 PHASE1
VID3 3
22 LGATE1
VID2 4
21 PGND
VID1 5
20 OCSET1
VID0 6
19 VSEN1
PGOOD
7
FAULT 8
18 FB1
17 COMP1
SS 9
16 FB3
RT 10
15 DRIVE3
FB2 11
VIN2 12
224
FN4497.1
14 GND
13 VOUT2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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225
FAULT
FB2
VOUT2
VIN2
DRIVE3
0.23A
3V
-
+
-
+
-
+
-
+
0.3V
SS
1.26V
VCC
INHIBIT
+
FB3
-
FIGURE 1.
4V
OV
DACOUT
SOFTSTART
AND FAULT
LOGIC
TTL D/A
CONVERTER
(DAC)
OC2
LUV
VID4
VID0
VID2
VID1
VID3
11µA
-
+
-
+
LINEAR
UNDERVOLTAGE
-
+
-
+
-
+
-
+
FB1
OC1
COMP1
ERROR
AMP
115%
90%
110%
VSEN1
PWM
RT
UPPER
DRIVE
RESET (POR)
POWER-ON
VCC
LOWER
DRIVE
GATE
CONTROL
INHIBIT
OSCILLATOR
PWM
COMP
-
+
-
+
200mA
OCSET1
VCC
VCC
3V
GND
PGND
LGATE1
PHASE1
UGATE1
PGOOD
HIP6018
Block Diagram
HIP6018
Simplified Power System Diagram
+5VIN
Q1
+3.3VIN
LINEAR
REGULATOR
VOUT2
PWM1
CONTROLLER
VOUT1
HIP6018
Q2
LINEAR
CONTROLLER
Q3
VOUT3
FIGURE 2.
Typical Application
+12VIN
+5VIN
CIN
VCC
OCSET1
VIN2
+3.3VIN
POWERGOOD
PGOOD
VOUT2
VOUT2
2.5V
FB2
UGATE1
COUT2
Q1
PHASE1
LGATE1
Q3
Q2
CR1
PGND
DRIVE3
HIP6018
VOUT3
FB3
VSEN1
1.5V
FB1
COUT3
COMP1
VID0
VID1
VID2
FAULT
VID3
RT
VID4
SS
GND
FIGURE 3.
226
LOUT1
CSS
COUT1
VOUT1
1.8V TO 3.5V
HIP6018
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
PGOOD, RT, FAULT, and GATE VoltageGND - 0.3V to VCC + 0.3V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
65
SOIC Package (with 3 in2 of copper) . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ICC
UGATE1, DRIVE3, LGATE1, and VOUT2 Open
-
10
-
mA
VCC SUPPLY CURRENT
Nominal Supply
POWER-ON RESET
Rising VCC Threshold
VOCSET = 4.5V
8.6
-
10.4
V
Falling VCC Threshold
VOCSET = 4.5V
8.2
-
10.2
V
2.45
2.55
2.65
V
VIN2 Under-Voltage Hysteresis
-
500
-
mV
Rising VOCSET1 Threshold
-
1.25
-
V
Rising VIN2 Under-Voltage Threshold
OSCILLATOR
Free Running Frequency
RT = OPEN
185
200
215
kHz
Total Variation
6kΩ < RT to GND < 200kΩ
-15
-
+15
%
-
1.9
-
VP-P
DAC(VID0-VID4) Input Low Voltage
-
-
0.8
V
DAC(VID0-VID4) Input High Voltage
2.0
-
-
V
DACOUT Voltage Accuracy
-1.0
-
+1.0
%
1.240
1.265
1.290
V
-2.5
-
2.5
%
-
75
87
%
-
6
-
%
Over-Current Protection
180
230
-
mA
Over-current Protection During Start-Up
560
700
-
mA
-2.5
-
2.5
%
-
75
87
%
∆VOSC
Ramp Amplitude
RT = Open
REFERENCE and DAC
Reference Voltage (Pin FB2 and FB3)
LINEAR REGULATOR
Regulation
10mA < IVOUT2 < 150mA
Under-Voltage Level
FB2UV
FB2 Rising
Under-Voltage Hysteresis
LINEAR CONTROLLER
Regulation
VSEN3 = DRIVE3, 0 < IDRIVE3 < 20mA
Under-Voltage Level
FB3UV
227
FB3 Rising
HIP6018
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
6
-
%
20
40
-
mA
-
88
-
dB
-
15
-
MHz
COMP = 10pF
-
6
-
V/µs
Under-Voltage Hysteresis
DRIVE3 Source Current
VIN2 - DRIVE3 > 0.6V
PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
GBWP
Slew Rate
SR
PWM CONTROLLER GATE DRIVER
Upper Drive Source
IUGATE
VCC = 12V, VUGATE1 (or VGATE2) = 6V
-
1
-
A
Upper Drive Sink
RUGATE
VUGATE1-PHASE1 = 1V
-
1.7
3.5
Ω
Lower Drive Source
ILGATE
VCC = 12V, VLGATE1 = 1V
-
1
-
A
Lower Drive Sink
RLGATE
VLGATE1 = 1V
-
1.4
3.0
Ω
VSEN1 Rising
112
115
118
%
VFAULT = 10V
10
14
-
mA
VOCSET = 4.5VDC
170
200
230
µA
-
11
-
µA
-
-
1.0
V
PROTECTION
VOUT1 Over-Voltage Trip
FAULT Sourcing Current
IOVP
OCSET1 Current Source
IOCSET
Soft-Start Current
ISS
Chip Shutdown Soft-Start Threshold
POWER GOOD
VOUT1 Upper Threshold
VSEN1 Rising
108
-
110
%
VOUT1 Under Voltage
VSEN1 Rising
92
-
94
%
VOUT1 Hysteresis (VSEN1 / DACOUT)
Upper/Lower Threshold
-
2
-
%
IPGOOD = -4mA
-
-
0.5
V
PGOOD Voltage Low
VPGOOD
Typical Performance Curves
100
CUGATE1 = CLGATE1 = CGATE
CGATE = 4800pF
VVCC = 12V, VIN = 5V
80
RT PULLUP
TO +12V
ICC (mA)
RESISTANCE (kΩ)
1000
100
60
CGATE = 3600pF
40
CGATE = 1500pF
10
20
RT PULLDOWN TO VSS
10
100
SWITCHING FREQUENCY (kHz)
FIGURE 4. RT RESISTANCE vs FREQUENCY
228
CGATE = 660pF
1000
0
100
200
300
400
500
600
700
800
900
SWITCHING FREQUENCY (kHz)
FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY
1000
HIP6018
Functional Pin Description
VSEN1 (Pin 19)
This pin is connected to the PWM converter’s output voltage.
The PGOOD and OVP comparator circuits use this signal to
report output voltage status and for over voltage protection.
OCSET1 (Pin 20)
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. R OCSET, an internal 200µA current source
(IOCSET), and the upper MOSFET on-resistance (rDS(ON))
set the PWM converter over-current (OC) trip point
according to the following equation:
PHASE1 (Pin 23)
Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin is used to monitor the voltage
drop across the upper MOSFET for over-current protection.
UGATE1 (Pin 24)
Connect UGATE pin to the PWM converter’s upper
MOSFET gate. This pin provides the gate drive for the upper
MOSFET.
PGND (Pin 21)
This is the power ground connection. Tie the PWM
converter’s lower MOSFET source to this pin.
I OCSET × R OCSET
I PEAK = ---------------------------------------------------r D S ( ON )
LGATE1 (Pin 22)
An over-current trip cycles the soft-start function. Sustaining
an over-current for 2 soft-start intervals shuts down the
controller.
VCC (Pin 1)
SS (Pin 9)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 11µA (typically) current source, sets
the soft-start interval of the converter.
Pulling this pin low with an open drain signal will shut down
the IC.
VID0, VID1, VID2, VID3, VID4 (Pins 6, 5, 4, 3 and 2)
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the core converter
output voltage. It also sets the core PGOOD and OVP
thresholds.
COMP1 and FB1 (Pins 17 and 18)
COMP1 and FB1 are the available external pins of the PWM
error amplifier. The FB1 pin is the inverting input of the error
amplifier. Similarly, the COMP1 pin is the error amplifier
output. These pins are used to compensate the voltagecontrol feedback loop of the PWM converter.
GND (Pin 14)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PGOOD (Pin 7)
PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
core output is not within ±10% of the DACOUT reference
voltage and the other outputs are below their under-voltage
thresholds.
The PGOOD output is open for VID codes that inhibit
operation. See Table 1.
Connect LGATE1 to the PWM converter’s lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.
Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC.
RT (Pin 10)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
6
5 × 10
Fs ≈ 200k Hz + --------------------R T (k Ω)
(RT to GND)
Conversely, connecting a pull-up resistor (RT) from this pin
to VCC reduces the switching frequency according to the
following equation:
7
4 × 10
Fs ≈ 200k Hz – --------------------R T (k Ω)
(RT to 12V)
FAULT (Pin 8)
This pin is low during normal operation, but it is pulled to
VCC in the event of an over-voltage or over-current
condition.
DRIVE3 (Pin 15)
Connect this pin to the gate of an external MOSFET. This
pin provides the drive for the linear controller’s pass
transistor.
FB3 (Pin 16)
Connect this pin to a resistor divider to set the linear
controller output voltage.
VOUT2 (Pin 13)
Output of the linear regulator. Supplies current up to 230mA.
FB2 (Pin 11)
Connect this pin to a resistor divider to set the linear
regulator output voltage.
229
HIP6018
VIN2 (Pin 12)
This pin supplies power to the internal regulator. Connect
this pin to a suitable 3.3V source.
Additionally, this pin is used to monitor the 3.3V supply. If,
following a startup cycle, the voltage drops below 2.05V
(typically), the chip shuts down. A new soft-start cycle is
initiated upon return of the 3.3V supply above the undervoltage threshold.
Description
Operation
The HIP6018 monitors and precisely controls 4 output
voltage levels (Refer to Figures 1, 2, and 3). It is designed
for microprocessor computer applications with 3.3V and 5V
power, and 12V bias input from an ATX power supply. The
IC has one PWM controller, a linear controller, and a linear
regulator. The PWM controller is designed to regulate the
microprocessor core voltage (VOUT1) by driving 2
MOSFETs (Q1 and Q2) in a synchronous-rectified buck
converter configuration. The core voltage is regulated to a
level programmed by the 5-bit digital-to-analog converter
(DAC). An integrated linear regulator supplies the 2.5V clock
power (VOUT2). The linear controller drives an external
MOSFET (Q3) to supply the GTL bus power (VOUT3).
Figure 3 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse-width on the PHASE pin
increases. The interval of increasing pulse-width continues
until each output reaches sufficient voltage to transfer
control to the input reference clamp. If we consider the 2.0V
output (VOUT1) in Figure 3, this time occurs at T2. During
the interval between T2 and T3, the error amplifier
reference ramps to the final value and the converter
regulates the output to a voltage proportional to the SS pin
voltage. At T3 the input clamp voltage exceeds the
reference voltage and the output voltage is in regulation.
PGOOD
(2V/DIV)
0V
SOFT-START
(1V/DIV)
0V
Initialization
The HIP6018 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12VIN) at the VCC pin, the 5V input voltage
(+5VIN) on the OCSET1 pin, and the 3.3V input on the VIN2
pin. The normal level on OCSET1 is equal to +5VIN less a
fixed voltage drop (see over-current protection). The POR
function initiates soft-start operation after all three input supply
voltages exceed their POR thresholds.
Soft-Start
VOUT2 ( = 2.5V)
VOUT1 (DAC = 2V)
OUTPUT
VOLTAGES
(0.5V/DIV)
0V
T0 T1
The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the soft-start interval). Then an internal
11µA current source charges an external capacitor (CSS) on
the SS pin to 4V. The PWM error amplifier reference input (+
terminal) and output (COMP1 pin) is clamped to a level
proportional to the SS pin voltage. As the SS pin voltage
slews from 1V to 4V, the output clamp generates PHASE
pulses of increasing width that charge the output
capacitor(s). After this initial stage, the reference input clamp
slows the output voltage rate-of-rise and provides a smooth
transition to the final set voltage. Additionally both linear
regulator’s reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.
230
VOUT3 ( = 1.5V)
T2
T3
T4
TIME
FIGURE 6. SOFT-START INTERVAL
The remaining outputs are also programmed to follow the
SS pin voltage. Each linear output (VOUT2 and VOUT3)
initially follows a ramp similar to that of the PWM output.
When each output reaches sufficient voltage the input
reference clamp slows the rate of output voltage rise. The
PGOOD signal toggles ‘high’ when all output voltage levels
have exceeded their under-voltage levels. See the Soft-Start
Interval section under Applications Guidelines for a
procedure to determine the soft-start interval.
Fault Protection
All three outputs are monitored and protected against
extreme overload. A sustained overload on any linear
HIP6018
OVER
CURRENT
LATCH
INHIBIT
S Q
OC1
S
R
0.15V
+
COUNTER
-
R
SS
+
4V
FAULT
LATCH
VCC
S Q
UP
-
POR
R
FAULT
OV
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. A comparator indicates when CSS is fully
charged (UP signal), such that an under-voltage event on
either linear output (FB2 or FB3) is ignored until after the
soft-start interval (T4 in Figure 6). At startup, this allows
VOUT2 and VOUT3 to slew up over increased time intervals,
without generating a fault. Cycling the bias input voltage
(+12VIN on the VCC pin) off then on resets the counter and
the fault latch.
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes VOUT1 to increase. When the output exceeds the
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on as required in order to regulate VOUT1 to 1.15 x
DACOUT. This blows the input fuse and reduces VOUT1.
The fault latch raises the FAULT pin close to VCC potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V OUT1 is
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on as
needed to regulate V OUT1 to 1.26V.
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s onresistance, rDS(ON) to monitor the current for protection
against shorted outputs. The linear regulator monitors the
current of the integrated power device and signals an overcurrent condition for currents in excess of 230mA.
Additionally, both the linear regulator and the linear
controller monitor FB2 and FB3 for under-voltage to protect
against excessive currents.
231
FAULT/RT
LUV
Figures 8 and 9 illustrate the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the output inductor (LOUT1). At time
T1, the OVER-CURRENT1 comparator trips when the voltage
across Q1 (ID • rDS(ON)) exceeds the level programmed by
ROCSET. This inhibits all outputs, discharges the soft-start
capacitor (CSS) with a 11µA current sink, and increments the
counter. CSS recharges at T2 and initiates a soft-start cycle
with the error amplifiers clamped by soft-start. With OUT1 still
overloaded, the inductor current increases to trip the overcurrent comparator. Again, this inhibits all outputs, but the
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments to
3. This sets the fault latch to disable the converter. The fault is
reported on the FAULT pin.
INDUCTOR CURRENTSOFT-START
regulator output or an over-voltage on the PWM output
disables all converters and drives the FAULT pin to VCC.
FAULT
REPORTED
10V
0V
COUNT
=1
COUNT
=2
COUNT
=3
4V
2V
0V
OVERLOAD
APPLIED
0A
T0 T1
T2
T3
T4
TIME
FIGURE 8. OVER-CURRENT OPERATION
The linear regulator operates in the same way as PWM1 to
over-current faults. Additionally, the linear regulator and
linear controller monitor the feedback pins for an undervoltage. Should excessive currents cause FB2 or FB3 to fall
below the linear under-voltage threshold, the LUV signal
sets the over-current latch if CSS is fully charged. Blanking the
LUV signal during the CSS charge interval allows the linear
outputs to build above the under-voltage threshold during
normal start-up. Cycling the bias input power off then on
resets the counter and the fault latch.
Resistor ROCSET1 programs the over-current trip level for the
PWM converter. As shown in Figure 9, the internal 200µA
current sink develops a voltage across ROCSET (VSET) that is
referenced to VIN. The DRIVE signal enables the over-current
comparator (OVER-CURRENT1). When the voltage across the
upper MOSFET (VDS(ON)) exceeds VSET, the over-current
comparator trips to set the over-current latch. Both VSET and
VDS are referenced to VIN and a small capacitor across
ROCSET helps VOCSET track the variations of VIN due to
HIP6018
MOSFET switching. The over-current function will trip at a peak
inductor current (IPEAK) determined by:
I OC SET x R OCSET
I PEAK = ----------------------------------------------------r DS ( ON )
OVER-CURRENT TRIP: VDS > VSET
VIN = +5V
(iD • rDS(ON) > I OCSET • ROCSET )
OCSET
I OCSET
200µA
OC1
VSET +
UGATE
+
-
PWM
LGATE
VID3
VID2
VID1
VID0
0
1
X
X
X
INHIBIT
0
0
1
1
X
INHIBIT
0
0
1
0
1
1.80
0
0
1
0
0
1.85
+
0
0
0
1
1
1.90
VDS
0
0
0
1
0
1.95
0
0
0
0
1
2.00
0
0
0
0
0
2.05
1
1
1
1
1
INHIBIT
1
1
1
1
0
2.1
1
1
1
0
1
2.2
1
1
1
0
0
2.3
1
1
0
1
1
2.4
1
1
0
1
0
2.5
1
1
0
0
1
2.6
1
1
0
0
0
2.7
1
0
1
1
1
2.8
VCC
GATE
CONTROL
VID4
NOMINAL
OUT1
VOLTAGE
DACOUT
ID
PHASE
OVERCURRENT1
PIN NAME
ROCSET
VCC
DRIVE
TABLE 1. VOUT1 VOLTAGE PROGRAM
VPHASE = VIN - VDS
VOCSET = VIN - VSET
PGND
HIP6018
FIGURE 9. OVER-CURRENT DETECTION
The OC trip point varies with MOSFET’s temperature. To avoid
over-current tripping in the normal operating load range,
determine the ROCSET resistor from the equation above with:
1. The maximum rDS(ON) at the highest junction
temperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for IPEAK > IOUT(MAX) + (∆I)/2,
where ∆I is the output inductor ripple current.
1
0
1
1
0
2.9
For an equation for the output inductor ripple current see
the section under component guidelines titled ‘Output
Inductor Selection’.
1
0
1
0
1
3.0
1
0
1
0
0
3.1
OUT1 Voltage Program
1
0
0
1
1
3.2
The output voltage of the PWM converter is programmed to
discrete levels between 1.8V DC and 3.5V DC . This output is
designed to supply the microprocessor core voltage. The
voltage identification (VID) pins program an internal voltage
reference (DACOUT) through a TTL-compatible 5-bit
digital-to-analog converter. The level of DACOUT also sets
the PGOOD and OVP thresholds. Table 1 specifies the
DACOUT voltage for the different combinations of
connections on the VID pins. The VID pins can be left open
for a logic 1 input, because they are internally pulled up to
+5V by a 10µA (typically) current source. Changing the VID
inputs during operation is not recommended. The sudden
change in the resulting reference voltage could toggle the
PGOOD signal and exercise the over-voltage protection. All
VID pin combinations resulting in an INHIBIT disable the IC
and the open-collector at the PGOOD pin.
1
0
0
1
0
3.3
1
0
0
0
1
3.4
1
0
0
0
0
3.5
232
NOTE: 0 = connected to GND or VSS, 1 = open or connected to 5V
through pull-up resistors, X = don’t care
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifier’s
output of the PWM converter. After the output voltage
increases to approximately 80% of the set value, the
reference input of the error amplifier is clamped to a voltage
proportional to the SS pin voltage. Both linear outputs follow
a similar start-up sequence. The resulting output voltage
sequence is shown in Figure 6.
HIP6018
+5VIN
+3.3VIN
CIN
COCSET1
ROCSET1
Q1
GATE3 UGATE1
LOUT1
VOUT1
PHASE1
HIP6018
VOUT2 LGATE1
Q2
COUT1
CR1
SS PGND
CSS
VOUT2
LOAD
The VID codes resulting in an INHIBIT as shown in Table 1
also shuts down the IC.
Q3
LOAD
The PWM output does not switch until the soft-start voltage
(VSS) exceeds the oscillator’s valley voltage. Additionally,
the reference on each linear’s amplifier is clamped to the
soft-start voltage. Holding the SS pin low with an open drain
or collector signal turns off all three regulators.
CVCC
VCC
GND
VIN2 OCSET1
VOUT3
Shutdown
+12V
LOAD
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval is
programmed by the soft-start capacitor, CSS. Programming
a faster soft-start interval increases the peak surge current.
The peak surge current occurs during the initial output
voltage rise to 80% of the set value.
COUT2
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turn-off,
the upper MOSFET was carrying the full load current. During
the turn-off, current stops flowing in the upper MOSFET and
is picked up by the lower MOSFET (and/or parallel Schottky
diode). Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes. Contact Intersil for evaluation
board drawings of the component placement and printed
circuit board.
There are two sets of critical components in a DC-DC
converter using a HIP6018 controller. The power
components are the most critical because they switch large
amounts of energy. The critical small signal components
connect to sensitive nodes or supply critical bypassing
current.
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors and
the power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, CSS . Locate
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node because the internal current source is only 11µA.
233
VIA CONNECTION TO GROUND PLANE
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
A multi-layer printed circuit board is recommended. Figure 10
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. The power plane
should support the input power and output power nodes.
Use copper filled polygons on the top and bottom circuit
layers for the phase nodes. Use the remaining printed circuit
layers for small signal wiring. The wiring traces from the
control IC to the MOSFET gate and source should be sized
to carry 1A currents. The traces for OUT2 need only be
sized for 0.2A. Locate C OUT2 close to the HIP6018 IC.
PWM Controller Feedback Compensation
Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller. Apply the methods and
considerations to both PWM controllers.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The reference
voltage level is the DAC output voltage for the PWM
controller. The error amplifier output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of VIN at the PHASE node.
The PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
gain and the output filter, with a double pole break frequency
at F LC and a zero at FESR. The DC gain of the modulator is
simply the input voltage, VIN , divided by the peak-to-peak
oscillator voltage, ∆VOSC .
HIP6018
Compensation Break Frequency Equations
VIN
OSC
∆ VOSC
DRIVER
PWM
COMP
LO
-
DRIVER
+
VOUT
PHASE
CO
ESR
(PARASITIC)
ZFB
VE/A
ZIN
ERROR
AMP
+
REFERENCE
DETAILED FEEDBACK COMPENSATION
ZFB
VOUT
C2
C1
ZIN
C3
R2
R3
R1
COMP
+
HIP6018
1
FP1 = ------------------------------------------------------C1 × C2
2π × R 2 ×  ----------------------
C1 + C2
1
F Z1 = ----------------------------------2π × R 2 × C1
FB
1
F P2 = ----------------------------------2π × R 3 × C3
1
F Z2 = ------------------------------------------------------2π × ( R1 + R3 ) × C3
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a peak due
to the high Q factor of the output filter at FLC, which is not
shown in Figure 12. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 with the capabilities of the error
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 12 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
100
FZ1 FZ2
FP1
FP2
80
REFERENCE
OPEN LOOP
ERROR AMP GAIN
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
1
F LC = ---------------------------------------2π × L O × C O
1
F ESR = ----------------------------------------2π × ESR × C O
The compensation network consists of the error amplifier
internal to the HIP6018 and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with an acceptable 0dB
crossing frequency (f0dB) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f0dB and 180 degrees. The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
234
GAIN (dB)
60
40
20
20LOG
(R 2/R1)
0
20LOG
(VIN/∆VOSC)
MODULATOR
GAIN
-20
COMPENSATION
GAIN
CLOSED LOOP
GAIN
-40
FLC
-60
10
100
1K
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth loop. A
stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output
capacitor to filter the current ripple. The linear regulator is
internally compensated and requires an output capacitor that
meets the stability requirements. The load transient for the
HIP6018
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
0.7
0.6
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and ESL (effective
series inductance) parameters rather than actual capacitance.
0.5
ESR (Ω)
0.4
0.3
0.2
LE
A B IO N
S T AT
ER
OP
0.1
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately,
ESL is not a specified parameter. Work with your capacitor
supplier and measure the capacitor’s impedance with
frequency to select suitable components. In most cases,
multiple electrolytic capacitors of small case size perform
better than a single large case capacitor. For a given transient
load magnitude, the output voltage transient response due to
the output capacitor characteristics can be approximated by
the following equation:
dITRAN
V TRAN = ESL × --------------------- + ESR × ITR AN
dt
Linear Output Capacitors
The output capacitors for the linear regulator and the linear
controller provide dynamic load current. The linear controller
uses dominant pole compensation integrated in the error
amplifier and is insensitive to output capacitor selection.
Capacitor, COUT3 should be selected for transient load
regulation.
The output capacitor for the linear regulator provides loop
stability. The linear regulator (OUT2) requires an output
capacitor characteristic shown in Figure 13. The upper line
plots the 45 phase margin with 150mA load and the lower
line is the 45 phase margin limit with a 10mA load. Select a
COUT2 capacitor with characteristic between the two limits.
Output Inductor Selection
The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
235
10
100
CAPACITANCE (µF)
1000
FIGURE 13. COUT2 OUTPUT CAPACITOR
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
V IN – V OUT V OU T
∆I = -------------------------------- × ---------------VIN
FS × LO
∆V OUT = ∆I × ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6018 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitors. Minimizing the response time can minimize the
output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L O × ITRAN
t RISE = -------------------------------V IN – VOUT
L O × ITRAN
tFALL = ------------------------------VOUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load, and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.
HIP6018
Input Capacitor Selection
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors should be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
thermal resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
2
IO × r DS ( ON ) × V OU T I O × VIN × t SW × F S
P UPPER = ------------------------------------------------------------ + ---------------------------------------------------VIN
2
2
I O × r DS ( ON ) × ( V I N – V OU T )
P LOWER = --------------------------------------------------------------------------------VIN
The rDS(ON) is different for the two previous equations even
if the type device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 14 shows the gate drive where the
upper gate-to-source voltage is approximately VCC less the
input supply. For +5V main power and +12VDC for the bias,
the gate-to-source voltage of Q1 is 7V. The lower gate drive
voltage is +12VDC. A logic-level MOSFET is a good choice
for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the maximum
voltage applied to VCC .
+5V OR LESS
+12V
VCC
HIP6018
MOSFET Selection/Considerations
The HIP6018 requires 3 N-Channel power MOSFETs. Two
MOSFETs are used in the synchronous-rectified buck
topology of the PWM converter. The linear controller drives a
MOSFET as a pass transistor. These should be selected
based upon rDS(ON) , gate supply requirements, and thermal
management requirements.
UGATE
Q1
PHASE
-
+
LGATE
NOTE:
VGS ≈ VCC -5V
Q2
CR1
PGND
NOTE:
VGS ≈ VCC
GND
PWM1 MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the dominant
design factors. The power dissipation includes two loss
components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations below).
The conduction loss is the only component of power
dissipation for the lower MOSFET. Only the upper MOSFET
has switching losses, since the lower device turns on into near
zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverserecovery of the lower MOSFET’s body diode. The gatecharge losses are proportional to the switching frequency
(FS) and are dissipated by the HIP6018, thus not
contributing to the MOSFETs’ temperature rise. However,
large gate charge increases the switching interval, tSW
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
236
FIGURE 14. OUTPUT GATE DRIVERS
Rectifier CR1 is a clamp that catches the negative inductor
voltage swing during the dead time between the turn off of the
lower MOSFET and the turn on of the upper MOSFET. The
diode must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to omit
the diode and let the body diode of the lower MOSFET clamp
the negative inductor swing, but efficiency might drop one or
two percent as a result. The diode's rated reverse breakdown
voltage must be greater than twice the maximum input voltage.
Linear Controller MOSFET Selection
The main criteria for selection of MOSFET for the linear
regulator is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
P LIN EAR = I O × ( VIN – V OUT )
Select a package and heatsink that maintains the junction
temperature below the maximum rating while operating at
the highest expected ambient temperature.
HIP6018
HIP6018 DC-DC Converter Application Circuit
from +3.3VDC , +5V DC and +12VDC . For detailed information
on the circuit, including a Bill-of-Materials and circuit board
description, see Application Note AN9805. Also see Intersil’s
web page (http://www.intersil.com).
Figure 15 shows an application circuit of a power supply for
a microprocessor computer system. The power supply
provides the microprocessor core voltage (V OUT1), the GTL
bus voltage (VOUT3) and clock generator voltage (VOUT2)
+12VIN
L1
F1
+5VIN
15A
1µH
C1-7
6x1000µF
GND
+
C15
1µF
C16
1µF
C18
VCC
1000pF
R2
1
VIN2
+3.3VIN
20
OCSET1 1.1K
12
POWERGOOD
+
7
C19
1000µF
24
23
PGOOD
Q1
HUF76143
UGATE1
PHASE1
VOUT1
(1.8 TO 3.5V)
L3
3.5µH
Q3
RFD3055
DRIVE3
VOUT3
R11
(1.5V)
1.87K
+
C43-46
4x1000µF
R13
(2.5V)
10K
C47
270µF
15
21
16
LGATE1
PGND
R4
4.99K
VSEN1
HIP6018
FB2
18
FB1
13
11
17
COMP1
R14
10K
VID0
VID1
VID1
VID2
VID2
VID3
VID3
VID4
VID4
R8
C40
2.21K
0.68µF
C41
10pF
C42
R10
2200pF 160K
VID0
C24-36 +
7x1000µF
Q2
HUF76143
19
R12
10K
VOUT2
VOUT2
+
FB3
22
8
6
5
10
4
9
732K
FAULT
RT
SS
3
2
R9
C48
0.039µF
14
GND
FIGURE 15. APPLICATION CIRCUIT
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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237
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