DATASHEET

HIP6521
®
Data Sheet
October 16, 2006
FN4837.5
PWM and Triple Linear Power Controller
Features
The HIP6521 provides the power control and protection for
four output voltages in high-performance microprocessor and
computer applications. The IC integrates a voltage-mode
PWM controller and three linear controllers, as well as
monitoring and protection functions into a 16 Ld SOIC
package. The PWM controller is intended to regulate the
microprocessor memory core voltage with a
synchronous-rectified buck converter. The linear controllers
are intended to regulate the computer system’s AGP 1.5V bus
power, the 2.5V clock power, and the 1.8V power for the
North/South Bridge core voltage and/or cache memory
circuits. Both the switching regulator and linear voltage
references provide ±2% of static regulation over line, load,
and temperature ranges. All outputs are user-adjustable by
means of an external resistor divider. All linear controllers
employ bipolar NPNs for the pass transistors.
• Provides 4 Regulated Voltages
- Memory Core, AGP, Clock, and Memory Controller Hub
Power
The HIP6521 monitors all the output voltages. The PWM
controller’s adjustable overcurrent function monitors the
output current by using the voltage drop across the upper
MOSFET’s rDS(ON). The linear regulator outputs are
monitored via the FB pins for undervoltage events.
• Overcurrent Fault Monitors
- Switching Regulator Does Not Require Extra Current
Sensing Element, Uses MOSFET’s rDS(ON)
Ordering Information
PART
NUMBER
PART
TEMP.
PKG.
MARKING RANGE (°C) PACKAGE DWG. #
HIP6521CB
HIP6521CB
0 to 70
16 Ld SOIC
M16.15
HIP6521CBZ
(Note)
6521CBZ
0 to 70
16 Ld SOIC
(Pb-free)
M16.15
• Drives Bipolar Linear Pass Transistors
• Externally Resistor-Adjustable Outputs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Small Converter Size
- 300kHz Constant Frequency Operation
- Small External Component Count
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Motherboard Power Regulation for Computers
Related Literature
HIP6521EVAL1 Evaluation Board
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-02.
Add “-T” suffix for tape and reel.
• ACPI Compatible
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
HIP6521 (SOIC)
TOP VIEW
DRIVE2 1
FB2 2
FB 3
15 DRIVE3
14 FB4
COMP 4
13 DRIVE4
GND 5
12 OCSET
PHASE 6
1
16 FB3
11 VCC
BOOT 7
10 LGATE
UGATE 8
9 PGND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Block Diagram
OCSET
FB3
VCC
VCC
2
EA3
RESET (POR)
+
-
EA4
DRIVE4
40µA
+
DRIVE3
POWER-ON
-
x 0.70
+
-
UV3
+
-
+
0.8V
UV4
BOOT
INHIBIT/SOFT-START
+
-
DRIVE2
DRIVE1
SOFTSTART
AND FAULT
LOGIC
UGATE
++
EA2
OCC
--
+
-
FB2
UV2
+
-
+
EA1
-
PWM
PHASE
GATE
CONTROL
COMP1
VCC
LGATE
GND
OSCILLATOR
SYNC
DRIVE
FB
COMP
PGND
HIP6521
-
FB4
FN4837.5
October 16, 2006
HIP6521
Simplified Power System Diagram
+5VSB (+5VDUAL)
+5VDUAL
+3.3VIN
Q1
LINEAR
CONTROLLER
Q3
VOUT2
+
+
Q2
HIP6521
LINEAR
CONTROLLER
Q4
VOUT3
VOUT1
PWM
CONTROLLER
LINEAR
CONTROLLER
Q5
+
VOUT4
+
Typical Application
+5VSB
+5VDUAL
LIN
CIN
+
VCC
BOOT
+3.3VIN
VOUT2
OCSET
DRIVE2
Q3
2.5V
FB2
+
CBOOT
UGATE
Rs2
PHASE
Rp2
COUT2
LGATE
+3.3VDUAL
PGND
COUT3
HIP6521
FB3
Q2
COUT1
2.5V
+
CR1
FB
Rp3
Rs1
COMP
Rp1
DRIVE4
Q5
VOUT1
LOUT1
Rs3
+
VOUT4
1.5V
COUT4
DRIVE3
Q4
VOUT3
1.8V
Q1
FB4
Rs4
+
Rp4
GND
3
FN4837.5
October 16, 2006
HIP6521
Absolute Maximum Ratings
Thermal Information
UGATE, BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V
VCC, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
DRIVE, LGATE, All Other Pins . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
5
-
mA
Rising VCC Threshold
4.25
-
4.5
V
Falling VCC Threshold
3.75
-
4.0
V
FOSC
275
300
325
kHz
Ramp Amplitude
∆VOSC
-
1.5
-
VP-P
Soft-Start Interval
TSS
6.25
6.83
7.40
ms
VREF
-
0.800
-
V
-2.0
-
+2.0
%
100
120
-
mA
-
70
-
%
-
80
-
dB
15
-
-
MHz
COMP = 10pF
-
6
-
V/µs
VCC SUPPLY CURRENT
Nominal Supply Current
ICC
UGATE, LGATE, DRIVE2, DRIVE3, and
DRIVE4 Open
POWER-ON RESET
OSCILLATOR AND SOFT-START
Free Running Frequency
REFERENCE VOLTAGE
Reference Voltage (All Regulators)
All Outputs Voltage Regulation
LINEAR REGULATORS (OUT2, OUT3, AND OUT4)
Output Drive Current (All Linears)
Undervoltage Level (VFB/VREF)
VCC > 4.5V
VUV
SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
GBWP
Slew Rate
SR
PWM CONTROLLER GATE DRIVERS
UGATE Source
IUGATE
VCC = 5V, VUGATE = 2.5V
-
-1
-
A
UGATE Sink
IUGATE
VUGATE-PHASE = 2.5V
-
1
-
A
LGATE Source
ILGATE
VCC = 5V, VLGATE = 2.5V
-
-1
-
A
LGATE Sink
ILGATE
VLGATE = 2.5V
-
2
-
A
34
40
46
µA
PROTECTION
OCSET Current Source
IOCSET
4
FN4837.5
October 16, 2006
HIP6521
Functional Pin Descriptions
VCC (Pin 11)
Provide a well decoupled 5V bias supply for the IC to this
pin. This pin also provides the gate bias charge for the lower
MOSFET controlled by the PWM section of the IC, as well as
the base current drive for the linear regulators’ external
bipolar transistors. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.
GND (Pin 5)
FB2, 3, 4 (Pins 2, 16, 14)
Connect the output of the corresponding linear regulators to
these pins through properly sized resistor dividers. The
voltage at these pins is regulated to 0.8V. These pins are
also monitored for undervoltage events.
Quickly pulling and holding any of these pins above 1.25V
(using diode-coupled logic devices) shuts off the respective
regulators. Releasing these pins from the pull-up voltage
initiates a soft-start sequence on the respective regulator.
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
Description
PGND (Pin 9)
The HIP6521 monitors and precisely controls 4 output
voltage levels (Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic). It is
designed for microprocessor computer applications with
3.3V, and 5V (5VDUAL) bias input from an ATX power
supply. The IC has a synchronous PWM controller and
three linear controllers. The PWM controller (PWM) is
designed to regulate the 2.5V memory voltage (VOUT1).
The PWM controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter configuration and
regulates the output voltage to a level programmed by a
resistor divider. The linear controllers are designed to
regulate three more of the computer system’s voltages,
typically the 1.5V AGP bus (VOUT4), the 2.5V clock voltage
(VOUT2), and the 1.8V ICH/MCH core voltage (VOUT3). All
linear controllers are designed to employ external NPN
bipolar pass transistors.
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
BOOT (Pin 7)
Connect a suitable capacitor (0.47µF recommended) from
this pin to PHASE. This bootstrap capacitor supplies UGATE
driver the energy necessary to turn and hold the upper
MOSFET on.
OCSET (Pin 12)
Connect a resistor from this pin to the drain of the upper
PWM MOSFET. This resistor, an internal 40µA current
source (typical), and the upper MOSFET’s on-resistance set
the converter overcurrent trip point. An overcurrent trip
cycles the soft-start function.
The voltage at this pin is monitored for power-on reset (POR)
purposes and pulling this pin below 1.25V with an open
drain/collector device will shutdown the switching controller.
PHASE (Pin 6)
Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin is used to monitor the voltage
drop across the upper MOSFET for overcurrent protection.
UGATE (Pin 8)
Connect UGATE pin to the PWM converter’s upper MOSFET
gate. This pin provides the gate drive for the upper MOSFET.
LGATE (Pin 10)
Connect LGATE to the PWM converter’s lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.
COMP and FB (Pins 4, 3)
COMP and FB are the available external pins of the PWM
converter error amplifier. The FB pin is the inverting input of the
error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM converter.
DRIVE2, 3, 4 (Pins 1, 15, 13)
Connect these pins to the base terminals of external bipolar
NPN transistors. These pins provide the base current drive
for the regulator pass transistors.
5
Operation
Initialization
The HIP6521 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltage. The POR monitors
the bias voltage at the VCC pin. The POR function initiates
soft-start operation after the bias supply voltage exceeds its
POR threshold.
Soft-Start
The POR function initiates the soft-start sequence. The
PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s).
Similarly, all linear regulators’ reference inputs are clamped
to a voltage proportional to the soft-start voltage. The
ramp-up of the internal soft-start function provides a
controlled output voltage rise.
Figure 1 shows the soft-start sequence for the typical
application. At T0 the +5VSB bias voltage starts to ramp up
(closely followed by the +5VDUAL voltage) crossing the 4.5V
POR threshold at time T1. On the PWM section, the oscillator’s
triangular waveform is compared to the clamped error amplifier
FN4837.5
October 16, 2006
HIP6521
output voltage. As the internal soft-start voltage increases, the
pulse-width on the PHASE pin increases to reach its
steady-state duty cycle at time T2. At time T3, the 3.3V input
supply starts ramping up; as a result, VOUT2 and VOUT4 start
ramping up on the second attempt (approximately 3.25 SS
cycles wait), at time T4. During the interval between T4 and T5,
the linear controller error amplifiers’ references ramp to the final
value bringing all outputs within regulation limits.
overcurrent event, resulting in an UV condition. Similarly,
after three soft-start periods, the fourth cycle initiates a
ramp-up of this linear output at time T3. One soft-start period
after T3, the linear output is within regulation limits. UV
glitches less than 1µs (typically) in duration are ignored.
VOUT1 (2.5V)
VOUT3 (1.8V)
VOUT4 (1.5V)
VOUT2 (2.5V)
+5VDUAL
+5VSB
0V
(0.5V/DIV.)
+3.3VIN
0V
SOFT-START
FUNCTION
(1V/DIV)
VOUT2 (2.5V)
VOUT1 (2.5V)
VOUT3 (1.8V)
INACTIVE
T0
VOUT4 (1.5V)
0V
(0.5V/DIV)
T0
T1
ACTIVE
UV MONITORING
+3.3VDUAL
T2
T3
TIME
T4
T5
FIGURE 1. SOFT-START INTERVAL
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s
on-resistance, rDS(ON) to monitor the current for protection
against shorted output. All linear controllers monitor their
respective FB pins for undervoltage events to protect against
excessive currents.
A sustained overload (undervoltage on linears or overcurrent
on the PWM) on any output results in an independent
shutdown of the respective output, followed by subsequent
individual re-start attempts performed at an interval equivalent
to 3 soft-start intervals. Figure 2 describes the protection
feature. At time T0, an overcurrent event sensed across the
switching regulator’s upper MOSFET (rDS(ON) sensing)
triggers a shutdown of the VOUT1 output. As a result, its
internal soft-start initiates a number of soft-start cycles. After a
three-cycle wait, the fourth soft-start initiates a ramp-up
attempt of the failed output, at time T2, bringing the output in
regulation at time T4.
To exemplify an UV event on one of the linears, at time T1,
the clock regulator (VOUT2) is also subjected to an
6
T1
TIME
T2
T3 T4
FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION
RESPONSE
As overcurrent protection is performed on the synchronous
switcher regulator on a cycle-by-cycle basis, OC monitoring
is active as long as the regulator is operational. Since the
overcurrent protection on the linear regulators is performed
through undervoltage monitoring at the feedback pins (FB2,
FB3, and FB4), this feature is activated approximately 25%
into the soft-start interval (see Figure 2).
A resistor (ROCSET) programs the overcurrent trip level for
the PWM converter. As shown in Figure 3, the internal
40µA current sink (IOCSET) develops a voltage across
ROCSET (VSET) that is referenced to VIN . The DRIVE
signal enables the overcurrent comparator (OCC). When
the voltage across the upper MOSFET (VDS(ON)) exceeds
VSET , the overcurrent comparator trips to set the
overcurrent latch. Both VSET and VDS(ON) are referenced
to VIN and a small capacitor across ROCSET helps
VOCSET track the variations of VIN due to MOSFET
switching. The overcurrent function will trip at a peak
inductor current (IPEAK) determined by:
I OCSET × R OCSET
I PEAK = --------------------------------------------------r DS ( ON )
The OC trip point varies with MOSFET’s rDS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the ROCSET
resistor from the equation above with:
FN4837.5
October 16, 2006
HIP6521
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for IPEAK > IOUT(MAX) + (∆I)/2, where
∆I is the output inductor ripple current.
OVERCURRENT TRIP:
V
>V
DS
SET
i D × r DS ( ON ) > I OCSET × R OCSET
VIN = +5V
ROCSET
OCSET
IOCSET
40µA
VSET +
iD
VCC
UGATE
DRIVE
OC
+
OCC
PHASE
-
V PHASE = V IN – V DS
V OCSET = V IN – V SET
GATE
CONTROL
PWM
+
VDS(ON)
FIGURE 3. OVERCURRENT DETECTION
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
Output Voltage Selection
The output voltage of the PWM converter can be
resistor-programmed to any level between VIN and 0.8V.
However, since the value of RS1 is affecting the values of
the rest of the compensation components, it is advisable its
value is kept between 2kΩ and 5kΩ.
RS × RP
--------------------- < 5kΩ
RS + RP
There may be a second restriction on the size of the
resistors used to set the linear regulators’ output voltage
based on ACPI functionality. Read the ‘ACPI
Implementation’ section under ‘Application Guidelines’ to
see if this additional constraint concerns your application. To
ensure the parallel combination of the feedback resistors
equals a certain chosen value, RFB, use the following
equations:
V OUT
R S = ---------------- × R FB
V FB
R S × V FB
R P = -------------------------------- , where
V OUT – V FB
VOUT - the desired output voltage,
VFB - feedback (reference) voltage, 0.8V.
Application Guidelines
Soft-Start Interval
The soft-start function controls the output voltages rate of rise
to limit the current surge at start-up. The soft-start function is
integrated on the chip and the soft-start interval is thus fixed.
Layout Considerations
+3.3VIN
DRIVE3
Q4
VOUT3
COUT3
regulators have to meet the following criteria: their value
while in a parallel connection has to be less than 5kΩ, or
otherwise said, the following relationship has to be met:
FB3
RS3
+
RP3
DRIVE4
Q5
VOUT4
COUT4
HIP6521
FB4
+
RS4
RP4
R ⎞
⎛
S
V OUT = 0.8 × ⎜ 1 + --------⎟
R P⎠
⎝
FIGURE 4. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF
THE FOUR REGULATORS (OUTPUTS 3 AND 4
PICTURED)
All linear regulators’ output voltages are set by means of
external resistor dividers as shown in Figure 4. The two
resistors used to set the voltage on each of the three linear
7
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the
turn-off transition of the upper PWM MOSFET. Prior to
turn-off, the upper MOSFET was carrying the full load
current. During the turn-off, current stops flowing in the
upper MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes. See the Application Note
AN9908 for evaluation board drawings of the component
placement and printed circuit board.
There are two sets of critical components in a DC/DC
converter using a HIP6521 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
FN4837.5
October 16, 2006
HIP6521
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the
high-frequency ceramic decoupling capacitors, close to the
power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.
LIN
+
+12V
CVCC
VCC GND
OCSET
LOAD
Q1
LOUT
VOUT1
PHASE
+
COUT2
DRIVE2
Q3
LGATE
COUT1
Q2
+
CR1
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.
Figure 6 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level, 0.8V.
The error amplifier (Error Amp) output (VE/A) is compared
with the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
VIN at the PHASE node. The PWM wave is smoothed by the
output filter (LO and CO).
VIN
DRIVER1
OSC
VOUT3
LOAD
ROCSET
UGATE
VOUT2
+
COCSET
PWM Controller Feedback Compensation
LOAD
CIN
HIP6521
COUT3
VOUT4
+
DRIVE3 DRIVE4
Q4
PGND
Q5
COUT4
LOAD
+5VIN
the stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A peak
currents.
PWM
COMP
LO
SYNC
DRIVER
-
+
∆ VOSC
+3.3VIN
PHASE
KEY
ISLAND ON CIRCUIT OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
VE/A
ZIN
+
0.8V
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
ZFB
C2
The critical small signal components include the bypass
capacitor for VCC and the feedback resistors. Locate these
components close to their connecting pins on the control IC.
A multi-layer printed circuit board is recommended.
Figure 5 shows the connections of the critical components
in the converter. Note that the capacitors CIN and COUT
each represent numerous physical capacitors. Dedicate
one solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages,
8
CO
ESR
(PARASITIC)
ZFB
ISLAND ON POWER PLANE LAYER
VOUT
+
C1
C3
R2
R3
RS1
COMP
FB
+
HIP6521
VOUT
ZIN
RP1
0.8V
FIGURE 6. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain, given by VIN/VOSC , and shaped by the output filter,
with a double pole break frequency at FLC and a zero at
FESR .
FN4837.5
October 16, 2006
HIP6521
Modulator Break Frequency Equations
1
F ESR = ----------------------------------------2π × ESR × C O
The compensation network consists of the error amplifier
(internal to the HIP6521) and the impedance networks ZIN
and ZFB . The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180°. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 6. Use these guidelines for
locating the poles and zeros of the compensation network:
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
1
F Z1 = ----------------------------------2π × R 2 × C1
1
F P1 = -----------------------------------------------------C1 × C2
2π × R 2 × ⎛ ----------------------⎞
⎝ C1 + C2⎠
1
F Z2 = ---------------------------------------------------------2π × ( R S1 + R3 ) × C3
1
F P2 = ----------------------------------2π × R 3 × C3
Figure 7 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 6. Using the above
guidelines should yield a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at FP2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 10 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
9
FP1
FP2
OPEN LOOP
ERROR AMP GAIN
⎛ V IN ⎞
20 log ⎜ ------------⎟
⎝ V PP⎠
60
40
COMPENSATION
GAIN
20
0
-20
⎛ R2 ⎞
20 log ⎜ -------------⎟
⎝ R S1⎠
-40
MODULATOR
GAIN
-60
10
100
FLC
CLOSED LOOP
GAIN
FESR
1K
10K
100K
1M
10M
FREQUENCY (Hz)
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)
FZ2
80
GAIN (dB)
1
F LC = ---------------------------------------2π × L O × C O
FZ1
100
FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
ACPI Implementation
The three linear controllers included within the HIP6521 can
independently be shut down, in order to accommodate
Advanced Configuration and Power Interface (ACPI) power
management features.
To shut down any of the linears, one needs to pull and keep
high the respective FB pin above a typical threshold of
1.25V. One way to achieve this task is by using a logic gate
coupled through a small-signal diode. The diode should be
placed as close to the FB pin as possible to minimize stray
capacitance to this pin. Upon turn-off of the pull-up device,
the respective output undergoes a soft-start cycle, bringing
the output within regulation limits. On the regulators
implementing this feature, the parallel combination of the
feedback resistors has to be sufficiently high to allow ease of
driving from the external device. Considering the other
restriction applying to the upper range of this resistor
combination (see ‘Output Voltage Selection’ paragraph), it is
recommended the values of the feedback resistors on an
ACPI-enabled linear regulator output meet the following
constraint:
RS × RP
2kΩ < ---------------------- < 5kΩ
RS + RP
To turn off the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached ROCSET pull-up) below 1.25V. To minimize the
possibility of OC trips at levels different than predicted, a
COCSET capacitor with a value of an order of magnitude
larger than the output capacitance of the pull-down device,
has to be used in parallel with ROCSET (1nF recommended).
Upon turn-off of the pull-down device, the switching regulator
undergoes a soft-start cycle.
FN4837.5
October 16, 2006
HIP6521
Important
If the collector voltage to a linear regulator pass transistor
(Q3, Q4, or Q5) is lost, the respective regulator has to be
shut down by pulling high its FB pin (i.e., when an input
power rail shuts down as a result of entering a sleep state,
the affected regulator’s FB pin has to be pulled high). This
measure is necessary in order to avoid possible damage to
the HIP6521 as a result of overheating. Overheating can
occur in such situations due to sheer power dissipation
inside the chip’s output linear drivers.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output
capacitor to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop following a high slew-rate
transient’s edge. An aluminum electrolytic capacitor’s ESR
value is related to the case size with lower ESR available in
larger case sizes. However, the equivalent series inductance
(ESL) of these capacitors increases with case size and can
reduce the usefulness of the capacitor to high slew-rate
transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure
the capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
Linear Output Capacitors
The output capacitors for the linear regulators provide
dynamic load current. The linear controllers use dominant
10
pole compensation integrated into the error amplifier and are
insensitive to output capacitor selection. Output capacitors
should be selected for transient load regulation.
PWM Output Inductor Selection
The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
V IN – V OUT V OUT
∆I = -------------------------------- × ---------------FS × L
V IN
∆V OUT = ∆I × ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values increase
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6521 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L O × I TRAN
t RISE = ------------------------------V IN – V OUT
L O × I TRAN
t FALL = -----------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.
FN4837.5
October 16, 2006
HIP6521
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through-hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up.
Given the reduced available gate bias voltage (5V) logiclevel or sub-logic-level transistors have to be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low VGS(ON) characteristics, as the low gate
threshold could be conducive to some shoot-through (due to
the Miller effect), in spite of the counteracting circuitry
present aboard the HIP6521.
+5V OR LESS
+5V
VCC
BOOT
HIP6521
UGATE
Transistors Selection/Considerations
The HIP6521 requires 5 external transistors. Two N-channel
MOSFETs are used in the synchronous-rectified buck
topology of PWM converter. The clock, AGP and MCH/ICH
linear controllers each drive an NPN bipolar transistor as a
pass element. All these transistors should be selected based
upon rDS(ON) , current gain, saturation voltages, gate/base
supply requirements, and thermal management
considerations.
+
CBOOT
Q1
PHASE
NOTE:
VGS ≈ VCC -0.5V
VCC
-
+
LGATE
PGND
GND
Q2
CR1
NOTE:
VGS ≈ VCC
FIGURE 8. MOSFET GATE BIAS
PWM MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the main component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverserecovery of the lower MOSFET’s body diode. The gatecharge losses are dissipated by the HIP6521 and don't heat
the MOSFETs. However, large gate-charge increases the
switching time, tSW which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
2
I O × r DS ( ON ) × V OUT I O × V IN × t SW × F S
P UPPER = ----------------------------------------------------------- + ---------------------------------------------------V IN
2
2
I O × r DS ( ON ) × ( V IN – V OUT )
P LOWER = -------------------------------------------------------------------------------V IN
11
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, providing the body diode
is fast enough to avoid excessive negative voltage swings at
the PHASE pin. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
Linear Controllers Transistor Selection
The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
P LINEAR = I O × ( V IN – V OUT )
Select a package and heatsink that maintains the junction
temperature below the rating with a the maximum expected
ambient temperature.
As bipolar NPN transistors have to be used with the linear
controllers, insure the current gain at the given operating
VCE is sufficiently large to provide the desired maximum
output load current when the base is fed with the minimum
driver output current.
FN4837.5
October 16, 2006
HIP6521
HIP6521 DC/DC Converter Application Circuit
Figure 9 shows an application circuit of a power supply for a
microprocessor computer system. The power supply provides
the system memory voltage (VOUT1), the AGP bus voltage
(VOUT4), the clock voltage (VOUT2), and the chip set core
voltage (VOUT3) from +5VDUAL. For detailed information on
the circuit, including a Bill-of-Materials and circuit board
description, see Application Note AN9908. Also see Intersil’s
web page (www.intersil.com) for the latest information.
L1
+5VDUAL
1.2µH
C1-3 +
3x1200µF
GND
C4
1µF
C5
1000pF
C6
1µF
VCC
+3.3VIN
11
Q3
FZT649
VOUT2
(2.5V)
DRIVE2
R2
FB2
1
7
OCSET
D1
MA732
12K
BOOT
2
12.7K
C8 +
330µF
R1
12
8
R3
5.90K
6
C7
0.47µF
UGATE
L2
2.5µH
U1
+3.3VDUAL
VOUT3
(1.8V)
DRIVE3
Q4
2SD1802
+
R4
9.09K
C13
1000µF
FB3
15
HIP6521
10
9
16
3
R5
7.15K
VOUT4
(1.5V)
+
DRIVE4
R9
7.50K
C16
1000µF
FB4
R10
8.45K
Q1,2
HUF76129D3S
LGATE
PGND
(2.5V)
C9-12 +
4x1000µF
FB
R6
1.50K
4
Q5
2SD1802
VOUT1
PHASE
C14
COMP
10pF
13
C15
22nF
14
5
R7
45.3K
R8
698
GND
To FB2
To FB4
S3
To OCSET
S5
FIGURE 9. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM
12
FN4837.5
October 16, 2006
HIP6521
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN4837.5
October 16, 2006
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