an9995

ISL6225 Dual PWM Controller Provides Complete DDR
Memory Power System Solution
TM
Application Note
December 2001
AN9995
Author: Vladimir A. Muratov, Steven P. Laur
Introduction
As computer memory bandwidth is pushed further and
further to multi-Gb/s levels, new memory technologies are
emerging. The DDR (Dual Data Rate) memory is an
evolutionary step on this path that along with increased data
rate maintains the low cost legacy of SDRAMs and thus will
dominate most PC markets for several years to come [1].
The DDR memory not only increases the memory bandwidth
but also reduces memory power consumption. The major
contributors to reduced power consumption are lower
operating voltage, lower signal voltage swing associated with
SSTL_2 logic, and reduced time spent in an active mode. All
these features make DDR memory a desirable component
for mobile, battery-powered applications [2, 3].
DDR Memory Power Requirements
The new memory comes with some additional requirements.
The increased bandwidth made available by SSTL_2
signaling require special clock techniques, proper layout, a
power source tracking reference signal, and line termination.
The important part of SSTL_2 signaling is that bus signals
are referenced to the reference voltage VREF that is usually
held symmetrically between VDDQ and VSS. It is important
that VREF stays symmetrically positioned between VDDQ
and VSS levels over variations in environmental and supply
parameters, Figure 1. The termination voltage VTT should
be within ±40mV of VREF. The VDDQ voltage, currently 2.5V
nominal value, should have ±200mV tolerance.
VTT=VDDQ/2
VDDQ
RTT=50Ω
RS=22Ω
VDDQ
Line
Receiver
50Ω
Transmitter
VREF=VDDQ/2
FIGURE 1. DDR MEMORY TERMINATION
Each terminated line consumes 16.2 mA. With about 125
lines compliant with SSTL_2 specifications, this theoretically
makes maximum current capability of VTT supply
Imax=2.025A, sourcing or sinking. In reality, the front bus is
operating on frequency of 100MHz, 133MHz and any given
memory state is actively present on the bus for a very short
moment of time of several tens of nanoseconds as DDR
1
memory operates with a double rate. Practically, the VTT
current gets dramatically averaged in output capacitors due
to a low duty factor (~15 to 30%) of read-write states [4]. The
terminating VTT power supply requirements depend only on
the number of lines and value of the terminating resistors
used and does not vary with memory size. Measurements
done in practical circuits show typical current levels in a
range of 0.5A. Tests show that the more memory is engaged
by the software, the lower is VTT current. All these suggests
that the same optimized solution can be used for various
computer applications.
The VDDQ power supply usually provides current not only to
the memory banks, but to a ‘north bridge’ controller and
some other circuitry as well. The current has a permanent
base level in a range of 2.0–3.0A. The base level depends
on how aggressive the power management scheme of a
memory controller isand also varies with memory size. The
bigger memory draws more current on background.
Depending on the computing task performed, the current
can peak up to 4.0A.
ISL6225–Provides Complete Power
Solution for DDR Memory
The ISL6225 dual switcher accomplishes all of the goals
associated with DDR memory power by combining two
synchronous PWM voltage regulators into a single IC. Its
unique design allows the IC to both source and sink current
on one of the channels. This ability allows the IC to be
adapted very effectively to a DDR memory power solution
when the DDR pin is set high.
The first PWM channel is used to regulate 2.5VDC (VDDQ)in
a typical “buck” regulator fashion. The output voltage of the
first channel is set to the required VDDQ level by the external
voltage divider. This makes the chip compatible not only with
current DDR memory specifications, but, also, with future
DDR II requirements. To provide the required tracking
function, the output of this regulated voltage is divided down
to 1.25VDC by an external R/R divider and fed back into the
IC as a tracking reference voltage.The reference voltage
VREF required by the DDR memory chips is provided via the
PG2/REF pin that can source up to 10mA. This output also
serves as a reference for the VTT channel. The second
channel will then regulate to 1.25VDC (VTT) with high
precision.
Please refer to the ISL6225 datasheet, FN9049, for more
information [5].
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
Application Note AN9995
Quick Start Evaluation
Load Connections
Out Of The Box
The ISL6225EVAL1 comes in a “ready-to-test” state. The
board comes equipped with several jumpers pre-populated
for battery operation. Use Table 1, which describes jumper
function, for test setup. Table 2 illustrates the input and
output voltage and current specifications.
NOTE: Note: This Application Note is for the DDR solution only.
Required Test Equipment
To fully test the ISL6225 chip functionality characterized by
this Application Note, the follow equipment is needed:
Connect the first electronic load positive terminal to VDDQ
(J5) and the negative terminal to GND (J6). Connect the
positive terminal of the second electronic load to VTT (J6)
and negative terminal to the nearest GND post (J9).
Performance Characterization
This section will show measured performance data from a
standard bench setup. It will include descriptions of each
experiment performed and how to recreate them.
NOTES:
•Jumper JP1 should be populated.
•Connect JP2 in FCCM mode
• 4 channel oscilloscope with probes
•Connect JP5 in the EN5V position.
• 2 electronic loads
•VIN = 5V, VCC = 5V.
• 2 bench power supplies
Jumper View
JP5
VINPRG
• precision digital multi-meters
• Digital pulse generator
TABLE 1. JUMPER FUNCTIONALITY
Jumper #
State
Function
JP1
POP
Normal Operation
NOP
Measure operating current IVCC
POS1
Enable hysteretic operation
POS2
FCCM mode
POP
Connect EN1 to VCC
NOP
External EN1
POP
Connect EN2 to VCC
NOP
External EN2
POS1
Operate in Battery Mode
POS2
Operate in 5V Mode
JP2
JP3
JP4
JP5
JP2
FCCM
Modes of Operation
Figure 10 shows a typical circuit for One-Step Conversion.
This is accomplished by populating jumper JP5 in POS1. In
this arrangement, VDDQ is converted directly from the
battery voltage. VTT is then converted directly from the
VDDQ output. This setup has the advantage of not requiring
a regulated system voltage to supply the power train.
Power Connections
With the all supplies turned OFF, connect the 0-24V power
supply positive terminal to the VIN post (J2) on the EVAL
board and the negative terminal to the nearest GND post
(J3). Then connect the 0-5V power supply positive terminal
to the VCC post (J4) and the negative terminal to the nearest
GND post (J1)
It should be noted that VIN must be powered up prior to VCC
in all cases.
Two-Step Conversion is also available on the ISL6225 DDR
evaluation board. This approach requires a regulated 5 volt
system rail to provide power to the converters. The VDDQ
converter takes the system rail voltage while the VTT
converter is cascaded from VDDQ. In this case, VIN must be
tied to GND through a 100kOhm resistor. This is done by
populating jumper JP5 in POS2 and tying the VCC and VIN
terminals together on the application board.
Soft-Start
In a start up event, the IC is required to ramp both output
voltages smoothly to their programmed level. To do this, the
chip must disable the undervoltage and pgood circuitry until
the output has risen to within 75% of its target. Only then is
PGOOD released and the part allowed to operate normally.
.
TABLE 2. INPUT/OUTPUT VOLTAGE/CURRENT
OPERATING SPECIFICATIONS.
With IVDDQ = IVTT = 3A, the start up event is captured in
Figure 2.
VIN
VCC
VDDQ
VTT
Voltage
5-24V
5V
2.5V
1.25V
Imax
3A
3A
6A
3A
Inom
-
-
3A
2A
2
• Connect the digital pulse generator to JP3 and JP4 to
allow for external enabling of the chip.
• Set the scope to trigger on EN (J12).
Application Note AN9995
EN, 5V/div
Load Current, 2A/div
0V
VDDQ, 1V/div
0A
2.5V
0V
VDDQ, 50mV/div
VTT, 1V/div
0V
1.25V
PGOOD, 5V/div
0V
VTT, 50mV/div
20us / div
1ms/div
FIGURE 2. INITIAL START UP
FIGURE 4. LOAD TRANSIENT (VTT - GND)
Steady-State Operation
Sinking Mode (VDDQ to VTT)
Under normal operating conditions, the ISL6225 should
regulate 2.5V and 1.25V with minimal effort and output
voltage ripple. Figure 3 illustrates converter waveforms
during normal operating conditions.
The output voltage excursion under a load transient in
sinking mode is shown in Figure 5. The load swings 0-3A
from VDDQ into VTT. Reconfigure the second electronic load
between VDDQ and VTT for this experiment.
0A
VDDQ, 50mV/div
2.5V
Load Current, 2A/div
PHASE_VDDQ, 10V/div
2.5V
0V
VDDQ, 50mV/div
VTT, 50mV/div
1.25V
1.25V
0V
VTT, 50mV/div
PHASE_VTT, 2V/div
20us/div
5us/div
FIGURE 3. NORMAL OPERATION
FIGURE 5. LOAD TRANSIENT (VDDQ - VTT)
Transient Response
Efficiency
The ISL6225 in DDR applications is required to handle load
transients of 0-3A on VTT. For these tests, there is a static
load of 3A from VDDQ to GND.
It is important to illustrate that each channel of the ISL6225
is highly efficient, which contributes to an overall high system
efficiency. Figures 6...9 demonstrate all perspectives of
efficiency for the ISL6225 in DDR mode.
Sourcing Mode (VTT to GND)
The output voltage excursion under a load transient event is
shown in Figure 4. The load swings 0-3A from VTT.
NOTE:
•Measure voltage at board terminals
•Allow thermal equilibrium
•TA = 25C
•No forced air
3
Application Note AN9995
Individual channel efficiency for VTT is captured for both
sinking and sourcing current in Figure 6 and Figure 7
respectively.
95
90
Efficiency (%)
95
Efficiency (%)
90
85
85
80
75
80
70
0.25
0.8
75
1.35
1.9
2.45
3.0
Output Current (A)
FIGURE 8. VDDQ EFFICIENCY
70
0.25
0.6
1.3
0.95
1.65
2
Output Current (A)
Overall efficiency for the ISL6225 in DDR mode can be seen
in Figure 9.
FIGURE 6. VTT EFFICIENCY. SOURCING MODE
95
95
90
Efficiency (%)
Efficiency (%)
90
85
85
80
80
75
75
70
70
0.5
0.8
1.1
1.4
1.7
2
Output Current (A)
0.25
0.6
0.95
1.3
1.65
2
Output Current (A)
FIGURE 9. OVERALL EFFICIENCY
FIGURE 7. VTT EFFICIENCY. SINKING MODE
References
The individual channel efficiency for VDDQ is illustrated in
Figure 8. Both VTT and VDDQ provide efficiency greater than
90% for nearly all loading conditions.
1. JEDEC STANDARD JESD8-9A. Stub Series Terminated
Logic for 2.5V (SSTL_2)
2. L.L. Wang, P. Leung, F. Tabrizi, ‘DDR DRAMs Pare Down
Power for Laptops’, Portable Design, July 2000
3. V. Muratov, S. Wiktor, J. Li, ‘Powering DDR Memory -Mysteries and Realities’, PCIM -- HFPC 2001, pp. 11-18
4. J. Janzen, ‘Calculating Memory System Power for DDR
SDRAM,’ Micron Application Note, 2001
5. ISL6225 Data Sheet, Intersil Corporation, File No.
FN9049
Intersil documents are available on the web at
http://www.intersil.com.
4
ISL6225 EVAL1 Schematic
The evaluation board schematic is shown in Figure 10. The board allows evaluation of ISL6225 performance for DDR memory using either single-step or dual-step power
conversion schemes. The recommended Bill of Materials (BOM) is presented in Table 3.
5
4
3
2
1
J1
J2
Vin
1
GND
2
C3
10u
25V
1
C2 1
10u
25V
2
+
VIN
1
2
R1
100k
JP5
C1
NOP
25V
J3
GND
1
2
1
1
1
3
2
D
JP1
VCC
2
1
1
1
C4
68u (OPT)
16V
+
D1
BAT54WT1
1
2
D2
VOUT1
C5
4.7
10V
1
2
3
R2 0R
2
U1
3
L1
4.7u
TP4
Sumida CDRH124-4R7MC
1
7
8
2
C13
NOP
4V
1
JP2
2
2
2
1
IRF7813
IRF7313
C17
1n
50V
C18
1
2
1
NOP
10V
1
PGND2
4
PHASE1
PHASE2
25
UGATE1
UGATE2
6
BOOT1
BOOT2
23
7
ISEN1
ISEN2
22
8
EN1
EN2
21
9
VOUT1
VOUT2
20
10
VSEN1
VSEN2
19
OCSET2
18
SOFT2
17
PG2/REF
16
PG1
15
11
OCSET1
12
SOFT1
13
DDR
14
VIN
R9
49.9k
R10
10k0
2
1
B
2
J7
PGND1
26
1
2
3
1
+
2
1
C12
220u
4V
R8
17k8
27
3
2
R7
NOP
28
24
1
FCCM
VCC
LGATE2
5
R4 1k00
1
2
1
LGATE1
U3
C20
0.01
10V
VIN
VCC
GND
2
JP3
1
8
1
R6
NOP
2
IRF7813
IRF7313
1
C19
1n
50V
C14
220u
4V
+
2
2
1
2
1
C23
4.7 2
10V
J9
1
C22
2
NOP
10V
1
GND
VOUT1
1
R11
10k0
GND
1
R13
NOP
R12
NOP
2
2
2
1
2
RED
1
R18
680R
1
R14
10k0
2
2
C26
1u
10V
2
GREEN
Building 2A,Suite 105
4020 Stirrup Creek Drive
Durham, NC 27703
Phone: (919) 405 3650
Fax: (919) 405 3651
34
3
A
2
1
1
R19
10k
J12
EN1
2
INTERSIL
R20
10k
1
Q1
BSS123LT1
1
PG1
1
5
1
1
J11
PGOOD
C16
4.7
10V
C15 1
NOP
4V
2
B
C21
NOP
10V
JP4
R17
680R
1 CR1
LXA3025IGC-TR
2
1
+
R16
680R
R15
680R
1
J6
1
1
1
1
1
7
1
2
1
C
VTT
L2
1.5u
Panasonic ELL6SH4R7M
1
2
J10
EN2
2
EN1
2
C10
0.15
16V
TP3
1
C25
4.7
10V
1
PG1
V_REF
5V
C24 1
NOP
4V
2
6
2
1
+
5
3
R5 5k90
1
2
J8
1
5V
4
ISL6225
2
VOUT1
2
1
4
6
GND
2
2
5
1
1
2
1
TP1
Probe Socket
2
C9
0.15
16V
2
1
C11
15n
50V
C7
1.0
10V
R3 0R
2
2
J13
EN2
Title
J14
4
3
FIGURE 10. APPLICATION BOARD SCHEMATIC
ISL6225 EVALUATION BOARD (DDR)
GND
2
Size
B
Document Number
ISL6225eval_DDR
Date:
Tuesday, September 25, 2001
Rev
A
Sheet
1
1
of
1
A
Application Note AN9995
U2
C
VOUT1
1
1
1
+
BAT54WT1
2
2
1
C8
1.0uF
10V
1
J5
C6
4.7
10V
2
TP2
Probe Socket
VDDQ
1
5V
1
3
VCC
J4
2
5
D
Application Note AN9995
Bill of Materials
TABLE 3. BILL OF MATERIALS
Qty
Reference
Description
1
CR1
LED
1
C1
NOP
Sanyo
OSCON 25SP56M
2
C2, C3
10uF
Tayo Yuden
TMK432BJ106KM
1
C4
68uF (OPT)
KEMET
T494D686(1)016AS
5
C5, C6, C16, C23, C25
4.7uF
Tayo Yuden
LMK316BJ475ML
3
C18, C21, C22
NOP
KEMET
C1206C105K8RAC
2
C7, C8
1.0uF
KEMET
C1206C105K8RAC
2
C10, C9
150nF
KEMET
C0805C154K4RAC
1
C11
15nF
KEMET
C0805C102K5RAC
2
C17, C19
1.0nF
KEMET
C0805C102K5RAC
2
C12, C14
220uF
Sanyo
4TPB220ML
1
C20
0.01uF
KEMET
C0805C103K4RAC
1
C26
10nF
KEMET
C0805C103K4RAC
3
C13, C15, C24
NOP
Sanyo
TPB330ML
2
D1, D2
Diode
Motorola
BAT54WT1
3
JP1, JP3, JP4
2-Terminal Jumper
Berg
header# 68000-236
shunt# 71363-102
2
JP2, JP5
3-Terminal Jumper
Berg
header# 68000-236
shunt# 71363-102
14
J1, J2, J3, J4, J5, J6, J7, J8,
J9, J10, J11, J12, J13, J14
Binding Post
Keystone
1502TL-2
1
L1
4.7uH
Sumida
CDRH124-4R7MC
1
L2
1.5uH
Panasonic
ELL6SH1R5M
1
Q1
NMOS Transistor
2
R1
100kΩ
2
R2, R3
0Ω
2
R4
1.00kΩ
2
R5
5.90kΩ
4
R6, R7, R12, R13
NOP
1
R8
17.8kΩ
1
R9
49.9kΩ
3
R10, R11, R14
10kΩ
4
R15, R16, R17, R18
680Ω
2
R19, R20
10kΩ
2
TP1, TP2
Probe Socket
2
TP3, TP4
Probe Socket
1
U1
Power Controller IC
2
U2, U3
Dual Bridged NMOS FETs
6
Package
Vendor
Part No.
LXA3025IGC-TR
BSS123LT1
28-Ld SSOP
Intersil Corp.
ISL6225
IRF7313
Application Note AN9995
ISL6225EVAL1 Layout
FIGURE 11. SILKSCREEN TOP
FIGURE 12. TOP LAYER
FIGURE 13. SILKSCREEN BOTTOM
FIGURE 14. BOTTOM LAYER
7
Application Note AN9995
FIGURE 15. POWER INTERNAL
FIGURE 16. GROUND INTERNAL
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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