an1081

WLAN - 802.11 Chipset Power Supply
Implementation Using the ISL6413
®
Application Note
PRELIMINARY
October 2003
AN1081.1
Author: Manisha Pandya
ISL6413 Triple Output Regulator with
Single Synchronous Buck and Dual LDO
The ISL6413 is a highly integrated triple output regulator
which provides a single chip solution for wireless chipset
power management. The device integrates a high efficiency
synchronous buck regulator with two ultra low noise LDO
regulators and a RESET. It accepts an input voltage range of
3.0V to 3.6V and provides three regulated output voltages:
1.8V (PWM), 2.84V (LDO1), and another ultra low noise
2.84V (LDO2). The PWM output maintains regulator down to
2.7V input voltage.
The PWM regulator is a current mode control synchronous
buck regulator with integrated N- and P- channel power
MOSFETs. It’s output is pre-set to 1.8V for the BBP/MAC
core supply. Synchronous rectification with internal
MOSFETs achieves >92% efficiency. The operating
frequency is typically 750kHz allowing the use of smaller
inductor and capacitor values. The device can be
synchronized to an external clock signal in the range of
500kHz to 1MHz. The PG_PWM output indicates any loss of
regulation on the PWM output.
The ISL6413 also has two LDO regulators which use internal
PMOS transistors as the pass devices. LDO2 features ultra
low noise that typically does not exceed 30µVRMS to aid
VCO stability. The EN_LDO pin controls LDO1 and LDO2
outputs. The ISL6413 also integrates a RESET function,
eliminating the need for an additional RESET IC usually
required in WLAN applications. This function asserts a
RESET signal whenever the VIN supply voltage drops below
a preset threshold, keeping it asserted for at least 25ms after
VIN has risen above the reset threshold. The PG_LDO
output indicates loss of regulation on either of the two LDO
outputs. Additional features include over current protection
for all three outputs and thermal shutdown.
High integration , excellent efficiency and the thin, Quad Flat
No-lead (QFN) package makes the ISL6413 an ideal choice
to power many of today’s small form factor industry standard
wireless cards such as PCMCIA, mini-PCI and Cardbus-32.
ISL6413 Reference Design
The ISL6413 evaluation board highlights the operation of the
IC in an embedded application.
TABLE 1. EVALUATION BOARDS
BOARD NAME
ISL6413EVAL1
IC
ISL6413IR
1
PACKAGE
Quick Start Evaluation
The evaluation board is shipped “ready to use” right from the
box. The board accepts a 3.3V input from a standard power
supply. The output can be exercised through the use of an
external load.
There are posts available on the board for introducing power,
for drawing current from the regulated output, and also for
testing other functions like RESET, SYNC, Power Good and
Shutdown.
Recommended Test Equipment
•
•
•
•
A 3.3V, 2A capable power supply
An electronic load 3 channels
A four-channel oscilloscope
Precision digital multimeters
Power and Load Connections
There are 2 sets of terminals that are used for supplying the
input power and 3 sets of terminals used for loading the 3
outputs (1 PWM and 2 Linear regulators).
Input Voltage - Connect the positive lead of the power
supply to VIN (P1) post and VIN_LDO (P11) post and the
ground lead of the supply to the PGND (P2) post and the
GND_LDO (P10) post.
Output Loading, Sourcing Current - To load the PWM
output, connect the positive lead of the electronic load to the
VOUT (P6) post and the return terminal of the same load
channel to the PGND (P7) post. Similarly, connect the
positive terminal of the second load channel to the
VOUT1(P9) post and the return terminal to the GND_LDO
(P12) post to load the output of LDO1. The ultra low noise
LDO2 output can be loaded by connecting the positive
terminal of a third channel of the electronic load to the
VOUT2 (P8) post and the return terminal to the GND_LDO
(P12) post.
Startup
There are two distinct start up methods for the ISL6413. The
first method is by the application of power to the inputs of the
IC. A controlled turn on of the outputs is allowed by the softstart feature of the IC. The soft start duration for the PWM is
typically 5.5ms with 750kHz switching frequency. The softstart duration for LDOs is 120µs.
24 Ld QFN
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Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1081
1V/DIV
VIN
VOUT
0.5V/DIV
0V
1V/DIV
0V
VOUT
0V
TIME (ms)
(2ms/DIV)
FIGURE 3. PWM SHUTDOWN WITH EN_PWM
FIGURE 1. PWM SOFT-START WAVEFORM
Shutdown
As discussed in the previous section, the PWM regulator can
be shutdown by pulling the EN_PWM pin to ground; the LDO
regulators can be shutdown by pulling the EN_LDO pin to
ground.
VIN
1V/DIV
1V/DIV
The second method of startup is by using the Enable feature
on the PWM and LDO outputs. The output of the PWM is
enabled when the EN_PWM pin is floating or pulled HIGH
and disabled when the pin is pulled to ground. Similarly,
holding the EN_LDO pin on the ISL6413 LOW or pulled to
ground will disable both LDO outputs. Releasing the pin
allows the LDOs to start up.
0V
VOUT1
0V
VOUT2
0V
TIME (ms)
(5ms/DIV)
FIGURE 4. LDO SHUTDOWN WITH VIN
VIN
1V/DIV
0V
VOUT
1V/DIV
0V
VOUT1
1V/DIV
0V
FIGURE 2. PWM SHUTDOWN WITH VIN
VOUT2
1V/DIV
0V
FIGURE 5. LDO SHUTDOWN WITH EN_LDO
2
Application Note 1081
Output Performance
The PWM switching frequency is typically 750kHz and the
device can be synchronized to an external frequency in the
range of 500kHz to 1MHz by connecting an external clock
source to the SYNC pin. The PWM output ripple is as shown
in figure 6. The LDO2 output features ultra low noise,
typically <30µV RMS, to facilitate VCO stability.
PWM OUTPUT VOLTAGE
1.82
The ISL6413 provides fixed output voltages for use in
Wireless Chipset applications. Internal trimmed resistor
networks set the typical output voltages as VOUT_PWM =
1.8V; VOUT1 = 2.84V and VOUT2 = 2.84V. All three outputs
have excellent line/load regulation and transient response as
shown in figure 7 to 12.
1.815
1.81
1.805
1.8
0
0.05
0.1
0.15
0.2
0.25
LOAD CURRENT (A)
OUTPUT
VOLTAGE (mV)
FIGURE 8. PWM LOAD REGULATION
20mV/
DIV
VOUT = 2.84V
20
LOAD = 50mA
0
INPUT
VOLTAGE (V)
4
TIME (µs)
(2µs/DIV)
FIGURE 6. PWM OUTPUT RIPPLE WAVEFORMS
3
TIME (1ms/DIV)
FIGURE 9. LINE REGULATION RESPONSE (VOUT1)
1.816
OUTPUT
VOLTAGE (mV)
1.812
1.81
1.808
VOUT = 2.84V
20
LOAD = 50mA
0
1.806
4
1.804
1.802
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
INPUT VOLTAGE
3.5
3.6
INPUT
VOLTAGE (V)
PWM OUTPUT VOLTAGE
1.814
3
FIGURE 7. PWM LINE REGULATION
TIME (1ms/DIV)
FIGURE 10. LINE REGULATION RESPONSE (VOUT2)
3
0.3
Application Note 1081
LOAD
CURRENT (mA)
OUTPUT VOLTAGE
DEVIATION (mV)
Power Saving with PWM Supply for BBP/MAC
VOUT1 = 2.84V
10
VIN = 3.3V
5
0
The ISL6413 offers significant power savings compared to a
LDO based 1.8V BBP/MAC power supply. Figure 14 shows
the efficiency comparison between PWM and LDO outputs
for 1.8V supply.
For a typical 300mA current drawn from the 1.8V output by
the BBP/MAC on the 1.8V output, the PWM efficiency will be
close to 92% and the Input current drawn from the 3.3V
supply will be:
100
IIN(PWM) = (1.8V x 300mA) / (3.3V x 0.92) = 178mA
0
TIME (2ms/DIV)
FIGURE 11. LOAD REGULATION RESPONSE (VOUT1)
For the same 300mA output current drawn by BBP/MAC on
LDO based 1.8V output supply, the LDO efficiency will be
54% and the Input current drawn from the 3.3V supply will
be 300mA.
LOAD
CURRENT (mA)
10
VIN = 3.3V
5
0
100
PWM
90
VOUT2 = 2.84V
EFFICIENCY (%)
OUTPUT VOLTAGE
DEVIATION (mV)
100
80
70
60
LDO
50
0
0
0.1
0.2
0.3
0.4
LOAD CURRENT (A)
TIME (2ms/DIV)
FIGURE 12. LOAD REGULATION RESPONSE (VOUT2)
1V/DIV
FIGURE 14. PWM AND LDO EFFICIENCY vs LOAD CURRENT
Hence, the ISL6413 reduces the supply current by about
120mA, saving 400mW of power compared to the LDO
option for the 1.8V BBP/MAC power supply at a typical
300mA load. This power saving and efficiency improvement
not only improves system battery life but offers better
thermal performance due to reduced on-chip power
dissipation.
For high efficiency applications where battery life is critical,
the ISL6413 is recommended, whereas the ISL6411 is
recommended for low cost applications.
Functional Description
Synchronous Buck Regulator
0V
TIME (0.5µs/DIV)
FIGURE 13. PWM PHASE NODE SWITCHING
4
The synchronous buck regulator with integrated N- and
P-channel power MOSFETs provides pre-set 1.8V for
BBP/MAC core supply. Synchronous rectification with
internal MOSFETs is used to achieve higher efficiency and
reduced number of external components. Operating
frequency is typically 750kHz, allowing the use of smaller
inductor and capacitor values. The device can be
synchronized to an external clock signal in the range of
Application Note 1081
500kHz to 1MHz. The PG_PWM output indicates loss of
regulation on the PWM output.
The PWM architecture uses a peak current mode control
scheme with internal slope compensation. At the beginning
of each clock cycle, the high side P-channel MOSFET is
turned on. The current in the inductor ramps up and is
sensed via an internal circuit. The error amplifier sets the
threshold for the PWM comparator. The high side switch is
turned off when the sensed inductor current reaches this
threshold. After a minimum dead time, preventing shoot
through current, the low side N-channel MOSFET will be
turned on and the current ramps down again. As the clock
cycle is completed, the low side switch will be turned off and
the next clock cycle starts.
The control loop is internally compensated, reducing the
amount of external components. The PWM section includes
an anti-ringing switch to reduce noise at light loads.
The switch current is internally sensed and the minimum
current limit is 550mA.
Frequency Synchronization
The typical operating frequency for the converter is 750kHz
if no clock signal is applied to the SYNC pin. It is possible to
synchronize the converter to an external clock within a
frequency range from 500kHz to 1MHz. The device
automatically detects the rising edge of the first clock and
will synchronize immediately to the external clock. If the
clock signal is stopped, the converter automatically switches
back to the internal clock and continues operation without
interruption. The switch over will be initiated if no rising edge
on the SYNC pin is detected for a duration of two internal
1.3µs clock cycles.
"rollover" or count below 0000). If >33% of the PWM cycles
go into overcurrent, the counter rapidly reaches count 1111
and the PWM output is shut down and the softstart counter is
reset. After 16 clocks the PWM output is enabled and the SS
cycle is started.
If VOUT exceeds the overvoltage limit for 32 consecutive
clock cycles, the PWM output is shut off and the SS counters
reset. The softstart cycle will not be started until EN or VIN
are toggled.
LDO Regulators
Each LDO consists of a 1.184V reference, error amplifier,
MOSFET driver, P-Channel pass transistor, dual-mode
comparator and internal feedback voltage divider.
The band gap reference is connected to the error amplifier’s
inverting input. The error amplifier compares this reference
to the selected feedback voltage and amplifies the
difference. The MOSFET driver reads the error signal and
applies the appropriate drive to the P-Channel pass
transistor. If the feedback voltage is lower than the reference
voltage, the pass transistor gate is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the
pass transistor gate is driven higher, allowing less current to
pass to the output. The output voltage is fed back through an
internal resistor divider connected to VOUT1/VOUT2 pins.
PG_LDO
PG_LDO is an open drain pulldown NMOS output that will
sink 1mA at 0.4V max. It goes to the active low state if either
LDO output is out of regulation by more than 15%. When the
LDO is disabled, the output is active low.
PWM Soft Start
Internal P-Channel Pass Transistors
As the EN_PWM (Enable) pin goes high, the soft-start
function will generate an internal voltage ramp. This causes
the start-up current to slowly rise preventing output voltage
overshoot and high inrush currents. The soft-start duration is
typically 5.5ms with 750kHz switching frequency. When the
soft-start is completed, the error amplifier will be connected
directly to the internal voltage reference. The SYNC input is
ignored during soft start.
Both ISL6413 LDO Regulators feature a typical 0.5Ω
rDS(ON) P-channel MOSFET pass transistor. This provides
several advantages over similar designs using PNP bipolar
pass transistors. The P-Channel MOSFET requires no base
drive, which reduces quiescent current considerably. PNP
based regulators waste considerable current in dropout
when the pass transistor saturates. They also use high base
drive currents under large loads. The ISL6413 does not
suffer from these problems.
Power Good (PG_PWM)
When the chip is enabled, this output is HIGH when VOUT is
within 8% of 1.8V and active low outside this range. When
the PWM is disabled, the output is active low. PG_PWM is
the complement of PG_PWM.
Leave the PG_PWM pin unconnected when not used.
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM
cycle. Should it exceed the overcurrent limit, a 4 bit up/down
counter counts up two LSB. Should it not be in overcurrent
the counter counts down one LSB (but the counter will not
5
Integrator Circuitry
Both ISL6413 LDO Regulators use external 33nF
compensation capacitors for minimizing load and line
regulation errors and for lowering output noise. When the
output voltage shifts due to varying load current or input
voltage, the integrator capacitor voltage is raised or lowered
to compensate for the systematic offset at the error amplifier.
Compensation is limited to ±5% to minimize transient
overshoot when the device goes out of dropout, current limit,
or thermal shutdown.
Application Note 1081
Current Limit
The ISL6413 monitors and controls the pass transistor’s
gate voltage to limit the output current. The current limit for
LDO1 is 330mA and LDO2 is 250mA. The output can be
shorted to ground without damaging the part due to the
current limit and thermal protection features.
Integrated RESET for MAC/Baseband
Processors
The ISL6413 includes a microprocessor supervisory block.
This block eliminates the extra RESET IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the VIN supply voltage decreases below a preset
threshold, keeping it asserted for a programmable time (set
by external capacitor CT) after the VIN pin voltage has risen
above the RESET threshold.
The push pull output stage of the reset circuit provides both
an active-Low and an active-High output. The RESET
threshold for ISL6413 is 2.630V typical.
UVLO Reset threshold is always lower than the RESET
threshold. This insures that as VIN falls, the reset goes low
before the LDOs and PWM are shut off.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL6413. When the junction temperature (TJ) exceeds
+150°C, the thermal sensor sends a signal to the shutdown
logic, turning off the pass transistor and allowing the IC to
cool. The pass transistor turns on again after the IC’s
junction temperature typically cools by 20°C, resulting in a
pulsed output during continuous thermal overload
conditions. Thermal overload protection protects the
ISL6413 against fault conditions. For continuous operation,
do not exceed the absolute maximum junction temperature
rating of +150°C.
Operating Region and Power Dissipation
The maximum power dissipation of ISL6413 depends on the
thermal resistance of the IC package and circuit board, the
temperature difference between the die junction and ambient
air, and the rate of air flow. The power dissipated in the
device is:
PT = P1 + P2 + P3, where
Where Tjmax = 150oC, TA = ambient temperature, and θJA
is the thermal resistance from the junction to the surrounding
environment.
The ISL6413 package features an exposed thermal pad on
its underside. This pad lowers the thermal resistance of the
package by providing a direct heat conduction path from the
die to the PC board. Additionally, the ISL6413’s ground
(GND_LDO and PGND) performs the dual function of
providing an electrical connection to system ground and
channeling heat away. Connect the exposed backside pad
direct to the GND_LDO ground plane.
Application Information
LDO Regulator Capacitor Selection and Regulator
Stability
Capacitors are required at the ISL6413 LDO regulators’
input and output for stable operation over the entire load
range and the full temperature range. Use >1µF capacitor at
the input of LDO regulators, VIN_LDO pins. The input
capacitor lowers the source impedance of the input supply.
Larger capacitor values and lower ESR provide better PSRR
and line transient response. The input capacitor must be
located at a distance of not more than 0.5 inches from the
VIN pins of the IC and returned to a clean analog ground.
Any good quality ceramic capacitor can be used as an input
capacitor.
The output capacitor must meet the requirements of
minimum amount of capacitance and ESR for both LDO’s.
The ISL6413 is specifically designed to work with small
ceramic output capacitors. The output capacitor’s ESR
affects stability and output noise. Use an output capacitor
with an ESR of 50mΩ or less to insure stability and optimum
transient response. For stable operation, a ceramic
capacitor, with a minimum value of 3.3µF, is recommended
for VOUT1 for 300mA output current, and 3.3µF is
recommended for VOUT2 at 200mA load current. There is no
upper limit to the output capacitor value. A larger capacitor
can reduce noise and improve load transient response,
stability and PSRR. A higher value of output capacitor
(10µF) is recommended for LDO2 when used to power VCO
circuitry in wireless chipsets. The output capacitor should be
located very close to VOUT pins to minimize impact of PC
board inductances and the other end of the capacitor should
be returned to a clean analog ground.
P1 = (IOUT x VOUT) x n, n is efficiency of the PWM
PWM Regulator Component Selection
P2 = IOUT1 (VIN - VOUT1)
Inductor Selection
P3 = IOUT2 (VIN - VOUT2)
The maximum power dissipation is:
Pmax = (Tjmax – TA)/θJA
6
A 10µH typical output inductor is used with the ISL6413
PWM section. Values larger than 15µH or less than 8µH may
cause stability problems because of the internal
compensation of the regulator. The important parameters of
the inductor that need to be considered are the current rating
of the inductor and the DC resistance of the inductor. The
DC resistance of the inductor will influence the efficiency of
Application Note 1081
the converter directly. Therefore, an inductor with lowest DC
resistance should be selected for highest efficiency.
In order to avoid saturation of the inductor, the inductor
should be rated at least for the maximum output current plus
the inductor ripple current.
TABLE 2. RECOMMENDED INDUCTORS
OUTPUT INDUCTOR
CURRENT
VALUE
0mA to
600mA
10µH
VENDOR PART #
COMMENTS
Coilcraft DO3316P-103 High
Efficiency
Coilcraft DT3316P-103
Sumida CDR63B-100
Sumida CDRH5D28-100
Coilcraft DO1608C-100 Smallest
Sumida CDRH4D28-100 Solution
0mA to
300mA
10µH
Coilcraft DS1608C-103
High
Efficiency
Murata LQH4C100K04
Smallest
Solution
Output Capacitor Selection
For best performance, a low ESR output capacitor is
needed. If an output capacitor is selected with an ESR value
≤120mΩ, its RMS ripple current rating will always meet the
application requirements. The RMS ripple current is
calculated as:
VO
1 – -------VI
1
I RMS ( C ) = V O × ----------------- × ----------------L
×
f
O
2× 3
The overall output ripple voltage is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage
ripple caused by charge and discharging the output
capacitor:
O
1 – V
------
VI 
1
∆V O = V O ×  ----------------- ×  -------------------------- + ESR
 L × f  8 × C × f

O




Because of the nature of the buck converter having a
pulsating input current, a low ESR input capacitor is required
for best input voltage filtering and minimizing the
interference with other circuits caused by high input voltage
spikes.
The input capacitor should have a minimum value of 10µF
and can be increased without any limit for better input
voltage filtering. The input capacitor should be rated for the
maximum input ripple current calculated as:
V O
VO 
I RMS = I O ( max ) × -------- ×  1 – --------
VI 
VI 
The worst case RMS ripple current occurs at 50% duty
cycle.
Ceramic capacitors show good performance because of
their low ESR value, and because they are less sensitive to
voltage transients, compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin
of the IC for best performance.
Layout Considerations
As for all switching power supplies, the layout is an important
step in the design of ISL6413 based power supply due to
high switching frequency and low noise LDO
implementations.
Allocate two board levels as ground planes, with many vias
between them to create a low impedance, high-frequency
plane. Tie all the device ground pins through multiple vias
each to this ground plane, as close to the device as possible.
Also tie the exposed pad on the bottom of the device to this
ground plane.
Use wide and short traces for the high current paths. The
input capacitor should be placed as close as possible to the
IC pins as well as the inductor and output capacitor. Use a
common ground node to minimize the effects of ground
noise.
Where the highest output voltage ripple occurs at the highest
input voltage.
TABLE 3. RECOMMENDED CAPACITORS
CAPACITOR
VALUE
ESR/mΩ
10µF
50
Taiyo Yuden
JMK316BJ106KL
Ceramic
47µF
100
Sanyo 6TPA47M
POSCAP
68µF
100
Sprague
594D686X0010C2T
Tantalum
VENDOR PART #
Input Capacitor Selection
COMMENTS
Conclusion
The ISL6413 is a system electronic regulator for 802.11
wireless chipset power management. The IC offers a
significant power savings compared to LDO options and
features small footprint and high integration, which make it
an ideal single chip power solution for various 802.11 chipset
power supplies.
References
For Intersil documents available on the web, see
http://www.intersil.com/
[1] ISL6413 Data Sheet, Intersil Corporation, File No.
FN9129.
7
Evaluation Board Schematic ISL6413
VIN
3.3V
L5
P1
BEAD
C1A
10µF
PGND
C1B
10µF
C2
1µF
P2
L1
C3
0.1µF
P6
10µH
8
PGND
C4A
10µF
D1
DNP*
C4B
10µF
C11
0.01µF
24 23 22 21 20 19
P3
EN
RESET
R1
10K
P4
VIN
3.3V
PG_LDO
RESET
PG_PWM
PG_PWM
SYNC
NC
EN_PWM
PG_LDO
25
R2
10K
7
R3
10K
TP3
VIN_LDO
0.033µF
P8
BEAD
C13
10µF
C7
10µF
C15
0.1µF
P12
0.01µF
VOUT2
GND_LDO
8 9 10 11 12
P9
BEAD
C12
C14
10µF
0.1µF
10µF
C6
0.033µF
L2
BEAD
10µF
TP5
P5
P11
L3
L4
C10A
TP4
R4
10K
EN_LDO
C5
C9
C10B
RESET
U1
ISL6413IR
18
VOUT
17
CC2
16
VOUT2
15
GND_LDO
14
VOUT1
CC1 13
CT
VIN_LDO
VIN_LDO
RESET
EN_LDO
1
2
3
4
5
6
PGND
* Do not populate
C8
10µF
VOUT1
C16
0.1µF
P10
GND_LDO
Application Note 1081
PG_PWM
SYNC
TP1
TP2
P7
SGND
VIN
PVCC
LX
PGND
GND
PG_PWM
VOUT
Application Note 1081
ISL6413 Evaluation Board Bill of Materials
ITEM
REFERENCE
QTY
PART NUMBER
1
U1
1
ISL6413IR
2
L1
1
3
L2, L3, L4, L5
4
PART TYPE
PACKAGE VENDOR
Regulator, Integrated Wireless
Chipset
4x4 QFN
Intersil
LQH32CN100K51L-T Inductor
10µH, 10%
SM_1210
muRata
4
BLM21PG300SN1
Ferrite Bead
Chip EMI Filter
SM_0805
muRata
C1A, C1B,
C4A, C7, C8,
C10A, C10B,
C13, C14
9
1210ZC106KAT2A
Capacitor, Ceramic, X7R
10µF, 10%, 10V
SM_1210
AVX
5
C2
1
0805ZC105KAT2A
Capacitor, Ceramic, X7R
1µF,10%,10V
SM_0805
AVX
6
C3, C12, C15,
C16
4
0603ZC104KAT2A
Capacitor, Ceramic, X7R
0.1µF,10%,10V
SM_0603
AVX
7
C5, C6
2
0603ZC333JAT2A
Capacitor, Ceramic, X7R
0.033µF, 5%, 10V
SM_0603
AVX
8
C9, C11
2
0603ZC103KAT2A
Capacitor, Ceramic, X7R
0.01µF, 10%, 10V
SM_0603
AVX
9
C4B (DNP)
10
R1 - R4
4
11
D1 (DNP)
1
DNP
Diode Schottkey
12
P1 - P12
12
1514-2
13
TP1 - TP5
5
5002
14
IC, Linear, Multi-Output
DESCRIPTION
DNP
DO214
Resistor, Film
4
10kΩ, 5%, 0.1W
SM_0603
Digi-Key
Turrett Post
Terminal post, through hole, 1/4 inch
tall
PTH
Keystone
TEST POINT vertical,
white
PC test jack
PTH
Keystone
Bumpers
9
Application Note 1081
ISL6413 Evaluation Board Layout
FIGURE 15. TOP SILK PRINT
FIGURE 16. TOP LAYER
10
Application Note 1081
ISL6413 Evaluation Board Layout (Continued)
FIGURE 17. LAYER 2
FIGURE 18. LAYER 3
11
Application Note 1081
ISL6413 Evaluation Board Layout (Continued)
FIGURE 19. LAYER 4
FIGURE 20. ISL6413 ENG1 - BOTTOM LAYER
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
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