DATASHEET

ISL6432
TM
Data Sheet
June 2001
PWM and Triple Linear Power Controller
for Home Gateway Applications
The ISL6432 monitors all the output voltages. The PWM
controller’s adjustable overcurrent function monitors the
output current by using the voltage drop across the upper
MOSFET’s rDS(ON). The linear regulator outputs are
monitored via the FB pins for undervoltage events.
Ordering Information
ISL6432CB
ISL6432EVAL1
0 to 70
9019
Features
The ISL6432 provides the power control and protection for
four output voltages for use with high-performance
microprocessor and embedded controller based
communications chip sets. The IC integrates a voltage-mode
PWM controller and three linear controllers, as well as
monitoring and protection functions into a 16-lead SOIC
package. The PWM controller is intended to regulate the
microprocessor memory core voltage with a synchronousrectified buck converter. The linear controllers can be
configured to generate DSP power, as well as upstream and
downstream voltages. Both the switching regulator and
linear voltage references provide ±2% of static regulation
over line, load, and temperature ranges. All outputs are useradjustable by means of an external resistor divider. All linear
controllers employ bipolar NPNs for the pass transistors.
PART NUMBER TEMP. RANGE ( oC)
File Number
• Provides 4 Regulated Voltages
- Memory Core, Embedded Controller/DSP, Tuner
• Drives Bipolar Linear Pass Transistors
• Externally Resistor-Adjustable Outputs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Overcurrent Fault Monitors
- Switching Regulator Does Not Require Extra Current
Sensing Element, Uses MOSFET’s rDS(ON)
• Small Converter Size
- 300kHz Constant Frequency Operation
- Small External Component Count
• ACPI Compatible
• Voltage Sequencing
PKG.
NO.
PACKAGE
16 Ld SOIC
Pinout
ISL6432 (SOIC)
TOP VIEW
M16.15
Evaluation Board
DRIVE2 1
Applications
FB2 2
• Low-Power Distributed DC-DC Conversion
• Cable Modem and DSL Modem Power Regulation
• High Performance Memory Applications
1
FB 3
16 FB3
15 DRIVE3
14 FB4
COMP 4
13 DRIVE4
GND 5
12 OCSET
PHASE 6
11 VCC
BOOT 7
10 LGATE
UGATE 8
9 PGND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
Block Diagram
OCSET
FB3
VCC
VCC
2
EA3
RESET (POR)
+
40µA
-
DRIVE3
POWER-ON
-
+
EA4
DRIVE4
x 0.70
+
UV3
-
+
-
+
UV4
0.8V
-
INHIBIT/SOFT-START
+
-
DRIVE2
DRIVE1
SOFTSTART
AND FAULT
LOGIC
UGATE
++
--
EA2
+
-
FB2
PHASE
OCC
UV2
+
-
+
EA1
-
PWM
GATE
CONTROL
COMP1
VCC
LGATE
GND
OSCILLATOR
PGND
SYNC
DRIVE
FB
COMP
ISL6432
BOOT
FB4
ISL6432
Simplified Power System Diagram
+5V
+3.3V
Q1
VOUT1
LINEAR
CONTROLLER
Q3
VOUT2
+
+
Q2
ISL6432
LINEAR
CONTROLLER
Q4
VOUT3
PWM
CONTROLLER
LINEAR
CONTROLLER
Q5
+
VOUT4
+
Typical Application
+5V
VCC
BOOT
+3.3VIN
VOUT2
OCSET
DRIVE2
Q3
2.5V
FB2
CBOOT
UGATE
Rs2
+
LGATE
+3.3VDUAL
PGND
COUT3
DRIVE3
Q4
VOUT3
1.8V
COUT1
CR1
Rp1
FB4
+
COUT4
Rp4
GND
3
Rs1
COMP
DRIVE4
Rs4
+
FB
Rp3
Q5
2.5V
ISL6432
FB3
VOUT4
1.5V
Q2
Rs3
+
VOUT1
LOUT1
PHASE
Rp2
COUT2
Q1
ISL6432
Absolute Maximum Ratings
Thermal Information
UGATE, BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 15V
VCC , PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V
DRIVE, LGATE, All Other Pins. . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 fordetails.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
5
-
mA
Rising VCC Threshold
4.25
-
4.5
V
Falling VCC Threshold
3.75
-
4.0
V
FOSC
275
300
325
kHz
Ramp Amplitude
∆VOSC
-
1.5
-
VP-P
Soft-Start Interval
TSS
6.25
6.83
7.40
ms
VREF
-
0.800
-
V
-2.0
-
+2.0
%
100
120
-
mA
-
70
-
%
-
80
-
dB
15
-
-
MHz
COMP = 10pF
-
6
-
V/µs
VCC SUPPLY CURRENT
Nominal Supply Current
ICC
UGATE, LGATE, DRIVE2, DRIVE3, and
DRIVE4 Open
POWER-ON RESET
OSCILLATOR AND SOFT-START
Free Running Frequency
REFERENCE VOLTAGE
Reference Voltage (All Regulators)
All Outputs Voltage Regulation
LINEAR REGULATORS (OUT2, OUT3, AND OUT4)
Output Drive Current (All Linears)
Undervoltage Level (VFB/VREF)
VCC > 4.5V
VUV
SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
GBWP
Slew Rate
SR
PWM CONTROLLER GATE DRIVERS
UGATE Source
IUGATE
VCC = 5V, VUGATE = 2.5V
-
-1
-
A
UGATE Sink
IUGATE
VUGATE-PHASE = 2.5V
-
1
-
A
LGATE Source
ILGATE
VCC = 5V, VLGATE = 2.5V
-
-1
-
A
LGATE Sink
ILGATE
VLGATE = 2.5V
-
2
-
A
34
40
46
µA
PROTECTION
OCSET Current Source
IOCSET
4
ISL6432
Functional Pin Descriptions
VCC (Pin 11)
Provide a well decoupled 5V bias supply for the IC to this
pin. This pin also provides the gate bias charge for the lower
MOSFET controlled by the PWM section of the IC, as well as
the base current drive for the linear regulators’ external
bipolar transistors. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.
voltage at these pins is regulated to 0.8V. These pins are
also monitored for undervoltage events.
Quickly pulling and holding any of these pins above 1.25V
(using diode-coupled logic devices) shuts off the respective
regulators. Releasing these pins from the pull-up voltage
initiates a soft-start sequence on the respective regulator.
Description
Operation
GND (Pin 5)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
PGND (Pin 9)
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
BOOT (Pin 7)
Connect a suitable capacitor (0.47µF recommended) from
this pin to PHASE. This bootstrap capacitor supplies UGATE
driver the energy necessary to turn and hold the upper
MOSFET on.
The ISL6432 monitors and precisely controls 4 output
voltage levels (Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic). The IC has a
synchronous PWM controller and three linear controllers.
The PWM controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter configuration and
regulates the output voltage to a level programmed by a
resistor divider. The linear controllers are designed to
regulate three more of the communication chip set
voltages. All linear controllers are designed to employ
external NPN bipolar pass transistors.
Initialization
OCSET (Pin 12)
Connect a resistor from this pin to the drain of the upper
PWM MOSFET. This resistor, an internal 40µA current
source (typical), and the upper MOSFET’s on-resistance set
the converter overcurrent trip point. An overcurrent trip
cycles the soft-start function.
The voltage at this pin is monitored for power-on reset (POR)
purposes and pulling this pin below 1.25V with an open
drain/collector device will shutdown the switching controller.
PHASE (Pin 6)
Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin is used to monitor the voltage
drop across the upper MOSFET for overcurrent protection.
UGATE (Pin 8)
Connect UGATE pin to the PWM converter’s upper MOSFET
gate. This pin provides the gate drive for the upper MOSFET.
LGATE (Pin 10)
Connect LGATE to the PWM converter’s lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.
COMP and FB (Pins 4, 3)
COMP and FB are the available external pins of the PWM
converter error amplifier. The FB pin is the inverting input of the
error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM converter.
DRIVE2, 3, 4 (Pins 1, 15, 13)
Connect these pins to the base terminals of external bipolar
NPN transistors. These pins provide the base current drive
for the regulator pass transistors.
FB2, 3, 4 (Pins 2, 16, 14)
Connect the output of the corresponding linear regulators to
these pins through properly sized resistor dividers. The
5
The ISL6432 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltage. The POR monitors
the bias voltage at the VCC pin. The POR function initiates
soft-start operation after the bias supply voltage exceeds its
POR threshold.
Soft-Start
The POR function initiates the soft-start sequence. The
PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s).
Similarly, all linear regulators’ reference inputs are clamped
to a voltage proportional to the soft-start voltage. The rampup of the internal soft-start function provides a controlled
output voltage rise.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s
on-resistance, rDS(ON) to monitor the current for protection
against shorted output. All linear controllers monitor their
respective FB pins for undervoltage events to protect against
excessive currents.
A sustained overload (undervoltage on linears or overcurrent
on the PWM) on any output results in an independent
shutdown of the respective output, followed by subsequent
individual re-start attempts performed at an interval equivalent
to 3 soft-start intervals. Figure 1 describes the protection
feature. At time T0, an overcurrent event sensed across the
switching regulator’s upper MOSFET (rDS(ON) sensing)
triggers a shutdown of the VOUT1 output. As a result, its
internal soft-start initiates a number of soft-start cycles. After a
ISL6432
three-cycle wait, the fourth soft-start initiates a ramp-up
attempt of the failed output, at time T2, bringing the output in
regulation at time T4.
To exemplify an UV event on one of the linears, at time T1,
the clock regulator (VOUT2) is also subjected to an
overcurrent event, resulting in an UV condition. Similarly,
after three soft-start periods, the fourth cycle initiates a
ramp-up of this linear output at time T3. One soft-start period
after T3, the linear output is within regulation limits. UV
glitches less than 1µs (typically) in duration are ignored.
VOUT1 (2.5V)
The OC trip point varies with MOSFET’s r DS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the R OCSET
resistor from the equation above with:
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for IPEAK > IOUT(MAX) + (∆I)/2, where
∆I is the output inductor ripple current.
OVERCURRENT TRIP:
V
>V
DS
SET
i ×r
>I
×R
D
DS ( ON ) OCSET
OCSET
OCSET
ROCSET
IOCSET
40µA
VOUT3 (1.8V)
DRIVE
VOUT4 (1.5V)
OC
VOUT2 (2.5V)
0V
VIN = +5V
VSET +
VCC
UGATE
+
ACTIVE
UV MONITORING
V
= V –V
PHA SE
IN
DS
V OCSET = V IN – V SET
GATE
CONTROL
PWM
+
VDS(ON)
PHASE
-
OCC
(0.5V/DIV.)
iD
FIGURE 2. OVERCURRENT DETECTION
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
SOFT-START
FUNCTION
+3.3VIN
DRIVE3
Q4
VOUT3
FB3
INACTIVE
T0
T1
TIME
T2
T3 T4
FIGURE 1. OVERCURRENT/UNDERVOLTAGE PROTECTION
RESPONSE
As overcurrent protection is performed on the synchronous
switcher regulator on a cycle-by-cycle basis, OC monitoring
is active as long as the regulator is operational. Since the
overcurrent protection on the linear regulators is performed
through undervoltage monitoring at the feedback pins (FB2,
FB3, and FB4), this feature is activated approximately 25%
into the soft-start interval (see Figure 1).
A resistor (ROCSET) programs the overcurrent trip level for
the PWM converter. As shown in Figure 2, the internal
40µA current sink (I OCSET) develops a voltage across
ROCSET (VSET) that is referenced to V IN . The DRIVE
signal enables the overcurrent comparator (OCC). When
the voltage across the upper MOSFET (V DS(ON)) exceeds
VSET, the overcurrent comparator trips to set the
overcurrent latch. Both V SET and VDS(ON) are referenced
to VIN and a small capacitor across ROCSET helps VOCSET
track the variations of VIN due to MOSFET switching. The
overcurrent function will trip at a peak inductor current
(IPEAK) determined by:
I OC SET × R OCSET
I PEAK = --------------------------------------------------r D S ( ON )
COUT3
+
RS3
RS4
ISL6432
FB4
+
COUT4
RP4
R S

VOUT = 0.8 ×  1 + -------
R P

FIGURE 3. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF
THE FOUR REGULATORS (OUTPUTS 3 AND 4
PICTURED)
Output Voltage Selection
The output voltage of the PWM converter can be resistorprogrammed to any level between V IN and 0.8V. However,
since the value of RS1 is affecting the values of the rest of
the compensation components, it is advisable its value is
kept between 2kΩ and 5kΩ.
All linear regulators’ output voltages are set by means of
external resistor dividers as shown in Figure 3. The two
resistors used to set the voltage on each of the three linear
regulators have to meet the following criteria: their value
while in a parallel connection has to be less than 5kΩ, or
otherwise said, the following relationship has to be met:
R S × RP
--------------------- < 5 kΩ
RS + RP
6
DRIVE4
Q5
VOUT4
RP3
ISL6432
LIN
+5VIN
+
+12V
CIN
CVCC
VCC GND
OCSET
ROCSET
VFB - feedback (reference) voltage, 0.8V.
Application Guidelines
COUT2
VOUT3
+
+
COUT1
DRIVE2
Q3
LGATE
Q2
CR1
VOUT4
ISL6432
COUT3
+
COUT4
DRIVE3 DRIVE4
Q4
PGND
LOAD
LOAD
VOUT - the desired output voltage,
VOUT1
PHASE
+
LOAD
R S × VFB
- , where
R P = -------------------------------VOUT – V FB
Q1
LOUT
UGATE
VOUT2
VOUT
R S = --------------- × R FB
VFB
COCSET
Q5
LOAD
There may be a second restriction on the size of the
resistors used to set the linear regulators’ output voltage
based on ACPI functionality. Read the ‘ACPI
Implementation’ section under ‘Application Guidelines’ to
see if this additional constraint concerns your application.To
ensure the parallel combination of the feedback resistors
equals a certain chosen value, RFB, use the following
equations:
Soft-Start Interval
The soft-start function controls the output voltages rate of rise
to limit the current surge at start-up. The soft-start function is
integrated on the chip and the soft-start interval is thus fixed.
Layout Considerations
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turn-off,
the upper MOSFET was carrying the full load current.
During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using a ISL6432 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the highfrequency ceramic decoupling capacitors, close to the power
switches. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.
7
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
The critical small signal components include the bypass
capacitor for VCC and the feedback resistors. Locate these
components close to their connecting pins on the control IC.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that the capacitors C IN and COUT each
represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. The power plane should
support the input power and output power nodes. Use copper
filled polygons on the top and bottom circuit layers for the
PHASE nodes, but do not unnecessarily oversize these
particular islands. Since the PHASE nodes are subjected to
very high dV/dt voltages, the stray capacitor formed between
these islands and the surrounding circuitry will tend to couple
switching noise. Use the remaining printed circuit layers for
small signal wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A peak
currents.
PWM Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level, 0.8V. The
ISL6432
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of VIN at the
PHASE node. The PWM wave is smoothed by the output
filter (LO and CO).
VIN
DRIVER1
OSC
PWM
COMP
LO
SYNC
DRIVER
-
+
∆ VOSC
VOUT
PHASE
CO
+
ESR
(PARASITIC)
ZFB
VE/A
ZIN
+
0.8V
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
ZFB
C2
C1
VOUT
ZIN
C3
R2
R3
RS1
COMP
FB
+
RP1
ISL6432
0.8V
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain, given by VIN/VOSC , and shaped by the output filter, with
a double pole break frequency at F LC and a zero at FESR .
Modulator Break Frequency Equations
1
F LC = ---------------------------------------2π × LO × C O
1
FESR = ----------------------------------------2π × ESR × CO
The compensation network consists of the error amplifier
(internal to the ISL6432) and the impedance networks ZIN
and ZFB . The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 6. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
8
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
1
FZ1 = ----------------------------------2π × R 2 × C1
1
F P1 = ------------------------------------------------------C1 × C2
2π × R 2 ×  ----------------------
 C1 + C2
1
FZ2 = ---------------------------------------------------------2π × ( R S1 + R3 ) × C3
1
F P2 = ----------------------------------2π × R 3 × C3
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 6. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at FP2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 10 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
ACPI Implementation
The three linear controllers included within the ISL6432 can
independently be shut down, in order to accommodate
Advanced Configuration and Power Interface (ACPI) power
management features.
To shut down any of the linears, one needs to pull and keep
high the respective FB pin above a typical threshold of 1.25V.
One way to achieve this task is by using a logic gate coupled
through a small-signal diode. The diode should be placed as
close to the FB pin as possible to minimize stray capacitance
to this pin. Upon turn-off of the pull-up device, the respective
output undergoes a soft-start cycle, bringing the output within
regulation limits. On the regulators implementing this feature,
the parallel combination of the feedback resistors has to be
sufficiently high to allow ease of driving from the external
device. Considering the other restriction applying to the upper
range of this resistor combination (see ‘Output Voltage
Selection’ paragraph), it is recommended the values of the
feedback resistors on an ACPI-enabled linear regulator output
meet the following constraint:
RS × RP
- < 5k Ω
2k Ω < --------------------RS + RP
To turn off the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached ROCSET pull-up) below 1.25V. To minimize the
possibility of OC trips at levels different than predicted, a
ISL6432
COCSET capacitor with a value of an order of magnitude
larger than the output capacitance of the pull-down device,
has to be used in parallel with ROCSET (1nF recommended).
Upon turn-off of the pull-down device, the switching regulator
undergoes a soft-start cycle.
FZ1
FZ2
FP1
FP2
100
OPEN LOOP
ERROR AMP GAIN
 V IN 
20 log  ------------ 
 V PP 
80
GAIN (dB)
60
40
COMPENSATION
GAIN
20
0
-20
 R2 
20 log  ------------
 R S1
-40
MODULATOR
GAIN
FLC
FESR
1K
10K
CLOSED LOOP
GAIN
-60
10
100
100K
1M
10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Important
If the collector voltage to a linear regulator pass transistor
(Q3, Q4, or Q5) is lost, the respective regulator has to be
shut down by pulling high its FB pin (i.e., when an input
power rail shuts down as a result of entering a sleep state,
the affected regulator’s FB pin has to be pulled high). This
measure is necessary in order to avoid possible damage to
the ISL6432 as a result of overheating. Overheating can
occur in such situations due to sheer power dissipation
inside the chip’s output linear drivers.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and
voltage rating requirements rather than actual capacitance
requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
9
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop following a high slew-rate transient’s
edge. An aluminum electrolytic capacitor’s ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter. Work
with your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Linear Output Capacitors
The output capacitors for the linear regulators provide
dynamic load current. The linear controllers use dominant
pole compensation integrated into the error amplifier and are
insensitive to output capacitor selection. Output capacitors
should be selected for transient load regulation.
PWM Output Inductor Selection
The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
V I N – V OU T V OUT
- × ---------------∆I = ------------------------------V IN
FS × L
∆V OUT = ∆I × ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values increase
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6432 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L O × I TRAN
t R ISE = ------------------------------V I N – V OU T
L O × ITRAN
tFALL = -----------------------------VOUT
ISL6432
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through-hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Transistors Selection/Considerations
The ISL6432 requires 5 external transistors. Two N-channel
MOSFETs are used in the synchronous-rectified buck topology
of PWM converter. The clock, AGP and MCH/ICH linear
controllers each drive an NPN bipolar transistor as a pass
element. All these transistors should be selected based upon
rDS(ON) , current gain, saturation voltages, gate/base supply
requirements, and thermal management considerations.
PWM MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the main component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverserecovery of the lower MOSFET’s body diode. The gatecharge losses are dissipated by the ISL6432 and don't heat
the MOSFETs. However, large gate-charge increases the
switching time, tSW which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
10
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
2
IO × r D S ( ON ) × VOUT I O × V IN × t SW × FS
P U PPER = ----------------------------------------------------------- + ---------------------------------------------------VIN
2
2
I O × r DS ( ON ) × ( VIN – V OUT )
P LOWER = -------------------------------------------------------------------------------VIN
Given the reduced available gate bias voltage (5V) logiclevel or sub-logic-level transistors have to be used for both NMOSFETs. Caution should be exercised with devices
exhibiting very low VGS(ON) characteristics, as the low gate
threshold could be conducive to some shoot-through (due to
the Miller effect), in spite of the counteracting circuitry
present aboard the ISL6432.
+5V OR LESS
+5V
VCC
BOOT
+
CBOOT
ISL6432
UGATE
Q1
PHASE
NOTE:
VGS ≈ VCC -0.5V
VCC
+
LGATE
PGND
Q2
CR1
NOTE:
VGS ≈ VCC
GND
FIGURE 7. MOSFET GATE BIAS
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, providing the body diode
is fast enough to avoid excessive negative voltage swings at
the PHASE pin. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
Linear Controllers Transistor Selection
The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
P LIN EAR = I O × ( VIN – V OUT )
Select a package and heatsink that maintains the junction
temperature below the rating with a the maximum expected
ambient temperature.
As bipolar NPN transistors have to be used with the linear
controllers, insure the current gain at the given operating
VCE is sufficiently large to provide the desired maximum
output load current when the base is fed with the minimum
driver output current.
ISL6432
ISL6432 DC-DC Converter Application Circuit
Figure 8 shows an application circuit. For detailed information
on the circuit, including a Bill-of-Materials and circuit board
description, please refer to the Power Management Home
Gateway section on Intersil’s web page (www.intersil.com)
+5V
C1
+
C4
1µF
GND
C5
1000pF
C6
1µF
VCC
+3.3VIN
11
Q3
FZT649
VOUT2
DRIVE2
R2
FB2
R1
OCSET
1
7
C8 +
330µF
12K
BOOT
2
12.7K
(2.5V)
D1
MA732
12
8
R3
5.90K
6
C7
0.47µF
UGATE
VOUT1
L2
PHASE
2.5µH
U1
+3.3V
VOUT3
(1.8V)
DRIVE3
Q4
2SD1802
R4
+
9.09K
C10
1000µF
FB3
15
ISL6432
10
9
16
3
R5
7.15K
Q1,2
HUF76129D3S
LGATE
(2.5V)
C9 +
PGND
FB
R6
1.50K
4
C14
COMP
10pF
Q5
2SD1802
VOUT4
(1.5V)
DRIVE4
R9
7.50K
+
C2
1000µF
FB4
R10
8.45K
13
C3
22nF
14
R7
45.3K
R8
698
5
GND
FIGURE 8. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM
11
ISL6432
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µα
e
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
A1
B S
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
0.2284
0.2440
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
α
5.80
-
H
N
NOTES:
MILLIMETERS
SYMBOL
16
0o
6.20
-
16
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web sit ewww.intersil.com
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Intersil SA
Mercure Center
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TEL: (32) 2.724.2111
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TEL: (321) 724-7000
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12
ASIA
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