DATASHEET

[ /Title
(HIP60
04)
/Subject
(Buck
and
SynchronousRectifier
(PWM
)Controller
and
Output
Voltage
Monitor)
/Autho
r ()
/Keywords
(Intersil
Corporation,
Intelligent
Power,
Computer
Power,
Pentium
Power,
HIP6004
Data Sheet
March 2000
Buck and Synchronous-Rectifier (PWM)
Controller and Output Voltage Monitor
The HIP6004 provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6004 integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004 includes a 5-input
digital-to-analog converter (DAC) that adjusts the output
voltage from 2.1VDC to 3.5VDC in 0.1V increments and from
1.3VDC to 2.1VDC in 0.05V steps. The precision reference
and voltage-mode regulator hold the selected output voltage
to within ±1% over temperature and line voltage variations.
The HIP6004 provides simple, single feedback loop,
voltage-mode control with fast transient response. It includes
a 200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/μs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
The HIP6004 monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within ±10%. The HIP6004
protects against over-current conditions by inhibiting PWM
operation. Built-in over-voltage protection triggers an
external SCR to crowbar the input supply. The HIP6004
monitors the current by using the rDS(ON) of the upper
MOSFET which eliminates the need for a current sensing
resistor.
HIP6004CB
TEMP.
RANGE (oC)
0 to 70
PACKAGE
20 Ld SOIC
• Drives Two N-Channel MOSFETs
• Operates from +5V or +12V Input
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- ±1% Over Line Voltage and Temperature
• 5-Bit Digital-to-Analog Output Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . 1.3VDC to 3.5VDC
- 0.1V Binary Steps. . . . . . . . . . . . . . . 2.1VDC to 3.5VDC
- 0.05V Binary Step. . . . . . . . . . . . . . . 1.3VDC to 2.1VDC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element,
Uses MOSFETs rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
Applications
• Power Supply for Pentium®, Pentium Pro, PowerPC™
and Alpha™ Microprocessors
• High-Power 5V to 3.xV DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Pinout
This data sheet describes a pre-released product.
Alpha Micro™ is a trademark of Digital Computer Equipment Corporation.
Pentium® is a registered trademark of Intel Corporation.
PowerPC™ is a registered trademark of IBM.
1
HIP6004
(SOIC)
TOP VIEW
PKG.
NO.
M20.3
4275.2
Features
Ordering Information
PART NUMBER
File Number
VSEN
1
20 RT
OCSET
2
19 OVP
SS
3
18 VCC
VID0
4
17 LGATE
VID1
5
16 PGND
VID2
6
15 BOOT
VID3
7
14 UGATE
VID4
8
13 PHASE
COMP
9
12 PGOOD
FB 10
11 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright © Intersil Corporation 2000
HIP6004
Typical Application
+12V
VIN = +5V or +12V
VCC
PGOOD
OCSET
MONITOR AND
PROTECTION
SS
EN
BOOT
OVP
RT
VID0
VID1
VID2
VID3
VID4
OSC
UGATE
PHASE
HIP6004
+VOUT
D/A
FB
-
LGATE
+
+
-
COMP
PGND
GND
VSEN
Block Diagram
VCC
VSEN
POWER-ON
RESET (POR)
110%
+
-
PGOOD
90%
+
-
115%
+
OVERVOLTAGE
10μA
OVP
-
SOFTSTART
+
-
OCSET
REFERENCE
200μA
OVERCURRENT
SS
BOOT
UGATE
4V
PHASE
VID0
VID1
VID2
VID3
VID4
D/A
CONVERTER
(DAC)
DACOUT
PWM
COMPARATOR
+
-
+
-
ERROR
AMP
FB
GATE
INHIBIT CONTROL
LOGIC
PWM
LGATE
PGND
COMP
GND
OSCILLATOR
RT
2
HIP6004
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . .+15V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
118
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UGATE and LGATE Open
-
5
-
mA
Rising VCC Threshold
VOCSET = 4.5V
-
-
10.4
V
Falling VCC Threshold
VOCSET = 4.5V
8.2
-
-
V
-
1.26
-
V
VCC SUPPLY CURRENT
Nominal Supply
ICC
POWER-ON RESET
Rising VOCSET Threshold
OSCILLATOR
Free Running Frequency
RT = OPEN
185
200
215
kHz
Total Variation
6kΩ < RT to GND < 200kΩ
-15
-
+15
%
-
1.9
-
VP-P
-1.0
-
+1.0
%
-
88
-
dB
-
15
-
MHz
-
6
-
V/μs
350
500
-
mA
ΔVOSC
Ramp Amplitude
RT = Open
REFERENCE AND DAC
DACOUT Voltage Accuracy
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
COMP = 10pF
GATE DRIVERS
Upper Gate Source
IUGATE
VBOOT - VPHASE = 12V, VUGATE = 6V
Upper Gate Sink
RUGATE
ILGATE = 0.3A
Lower Gate Source
ILGATE
VCC = 12V, VLGATE = 6V
Lower Gate Sink
RLGATE
ILGATE = 0.3A
-
115
120
%
OCSET Current Source
IOCSET
VOCSET = 4.5VDC
170
200
230
μA
OVP Sourcing Current
IOVP
VSEN = 5.5V, VOVP = 0V
60
-
-
mA
-
10
-
μA
VSEN Rising
106
-
111
%
Lower Threshold (VSEN / DACOUT)
VSEN Falling
89
-
94
%
Hysteresis (VSEN / DACOUT)
Upper and Lower Threshold
-
2
-
%
IPGOOD = -5mA
-
0.5
-
V
-
5.5
10
Ω
300
450
-
mA
-
3.5
6.5
Ω
PROTECTION
Over-Voltage Trip (VSEN/DACOUT)
Soft Start Current
ISS
POWER GOOD
Upper Threshold (VSEN / DACOUT)
PGOOD Voltage Low
VPGOOD
3
HIP6004
Typical Performance Curves
80
CGATE = 3300pF
70
60
RT PULLUP
TO +12V
ICC (mA)
RESISTANCE (kΩ)
1000
100
50
CUPPER = CLOWER = CGATE
40
CGATE = 1000pF
30
10
20
RT PULLDOWN TO VSS
CGATE = 10pF
10
10
100
1000
0
100
200
SWITCHING FREQUENCY (kHz)
FIGURE 1. RT RESISTANCE vs FREQUENCY
Functional Pin Description
VSEN
1
OCSET
2
19 OVP
SS
3
18 VCC
VID0
4
17 LGATE
VID1
5
16 PGND
VID2
6
15 BOOT
VID3
7
14 UGATE
VID4
8
13 PHASE
COMP
9
12 PGOOD
20 RT
FB 10
11 GND
300
400
500
600
700
800
SWITCHING FREQUENCY (kHz)
900
1000
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
VID0-4 (Pins 4-8)
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the 32 combinations of DAC inputs.
COMP (Pin 9) and FB (Pin 10)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
VSEN (Pin 1)
This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
OCSET (Pin 2)
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. ROCSET, an internal 200μA current source
(IOCS), and the upper MOSFET on-resistance (rDS(ON)) set
the converter over-current (OC) trip point according to the
following equation:
I OCS • R OCSET
I PEAK = -------------------------------------------r DS ( ON )
PGOOD (Pin 12)
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within ±10% of the
DACOUT reference voltage.
PHASE (Pin 13)
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for over-current protection. This pin also provides the return
path for the upper gate drive.
UGATE (Pin 14)
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10μA current source, sets the softstart interval of the converter.
4
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
BOOT (Pin 15)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
HIP6004
PGND (Pin 16)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
of increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2 . With sufficient
output voltage, the clamp on the reference input controls the
output voltage. This is the interval between t2 and t3 in Figure 3.
At t3 the SS voltage exceeds the DACOUT voltage and the
output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within ±5% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition.
RT (Pin 20)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
PGOOD
(2V/DIV.)
0V
SOFT-START
(1V/DIV.)
6
5 • 10
Fs ≈ 200kHz + --------------------R T ( kΩ )
OUTPUT
VOLTAGE
(1V/DIV.)
(RT to GND)
Conversely, connecting a pull-up resistor (RT) from this pin
to VCC reduces the switching frequency according to the
following equation:
0V
0V
t1
(RT to 12V)
t3
Initialization
The HIP6004 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages. The POR monitors the bias
voltage at the VCC pin and the input voltage (VIN) on the
OCSET pin. The level on OCSET is equal to VIN less a fixed
voltage drop (see over-current protection). The POR
function initiates soft start operation after both input supply
voltages exceed their POR thresholds. For operation with a
single +12V power source, VIN and VCC are equivalent and
the +12V power source must exceed the rising VCC
threshold before POR initiates operation.
Soft Start
The POR function initiates the soft start sequence. An internal
10μA current source charges an external capacitor (CSS) on
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft start interval with
CSS = 0.1μF. Initially the clamp on the error amplifier (COMP
pin) controls the converter’s output voltage. At t1 in Figure 3,
the SS voltage reaches the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE pulses
5
Over-Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFETs on-resistance,
rDS(ON) to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
SOFT-START
Functional Description
FIGURE 3. SOFT START INTERVAL
4V
2V
0V
OUTPUT INDUCTOR
4 • 10
Fs ≈ 200kHz – --------------------R T ( kΩ )
t2
TIME (5ms/DIV.)
7
15A
10A
5A
0A
TIME (20ms/DIV.)
FIGURE 4. OVER-CURRENT OPERATION
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the over-current trip level. An internal 200μA current
sink develops a voltage across ROCSET that is referenced to
VIN . When the voltage across the upper MOSFET (also
HIP6004
referenced to VIN) exceeds the voltage across ROCSET , the
over-current function initiates a soft-start sequence. The softstart function discharges CSS with a 10μA current sink and
inhibits PWM operation. The soft-start function recharges CSS ,
and PWM operation resumes with the error amplifier clamped
to the SS voltage. Should an overload occur while recharging
CSS, the soft start function inhibits PWM operation while fully
charging CSS to 4V to complete its cycle. Figure 4 shows this
operation with an overload condition. Note that the inductor
current increases to over 15A during the CSS charging interval
and causes an over-current trip. The converter dissipates very
little power with this method. The measured input power for the
conditions of Figure 4 is 2.5W.
I OCSET • R OCSET
I PEAK = --------------------------------------------------r DS ( ON )
where IOCSET is the internal OCSET current source (200μA
typical). The OC trip point varies mainly due to the MOSFETs
rDS(ON) variations. To avoid over-current tripping in the
normal operating load range, find the ROCSET resistor from
the equation above with:
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for I PEAK > I OUT ( MAX ) + ( ΔI ) ⁄ 2 ,
where ΔI is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
The over-current function will trip at a peak inductor current
(IPEAK) determined by:
TABLE 1. OUTPUT VOLTAGE PROGRAM
PIN NAME
PIN NAME
VID4
VID3
VID2
VID1
VID0
NOMINAL
OUTPUT
VOLTAGE
DACOUT
VID4
VID3
VID2
VID1
VID0
NOMINAL
OUTPUT
VOLTAGE
DACOUT
0
1
1
1
1
1.30
1
1
1
1
1
2.0
0
1
1
1
0
1.35
1
1
1
1
0
2.1
0
1
1
0
1
1.40
1
1
1
0
1
2.2
0
1
1
0
0
1.45
1
1
1
0
0
2.3
0
1
0
1
1
1.50
1
1
0
1
1
2.4
0
1
0
1
0
1.55
1
1
0
1
0
2.5
0
1
0
0
1
1.60
1
1
0
0
1
2.6
0
1
0
0
0
1.65
1
1
0
0
0
2.7
0
0
1
1
1
1.70
1
0
1
1
1
2.8
0
0
1
1
0
1.75
1
0
1
1
0
2.9
0
0
1
0
1
1.80
1
0
1
0
1
3.0
0
0
1
0
0
1.85
1
0
1
0
0
3.1
0
0
0
1
1
1.90
1
0
0
1
1
3.2
0
0
0
1
0
1.95
1
0
0
1
0
3.3
0
0
0
0
1
2.00
1
0
0
0
1
3.4
0
0
0
0
0
2.05
1
0
0
0
0
3.5
NOTE: 0 = connected to GND or VSS, 1 = OPEN.
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
presence of switching noise on the input voltage.
Output Voltage Program
The output voltage of a HIP6004 converter is programmed
to discrete levels between 1.3VDC and 3.5VDC . The
voltage identification (VID) pins program an internal voltage
reference (DACOUT) with a 5-bit digital-to-analog
converter (DAC). The level of DACOUT also sets the
PGOOD and OVP thresholds. Table 1 specifies the
DACOUT voltage for the 32 combinations of open or short
6
connections on the VID pins. The output voltage should not
be adjusted while the converter is delivering power.
Remove input power before changing the output voltage.
Adjusting the output voltage during operation could toggle
the PGOOD signal and exercise the overvoltage protection.
The DAC function is a precision non-inverting summation
amplifier shown in Figure 5. The resistor values shown are
only approximations of the actual precision values used.
Grounding any combination of the VID pins increases the
DACOUT voltage. The ‘open’ circuit voltage on the VID pins
is the band gap reference voltage, 1.26V.
HIP6004
Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, Css
close to the SS pin because the internal current source is
only 10μA. Provide local VCC decoupling between VCC and
GND pins. Locate the capacitor, CBOOT as close as
practical to the BOOT and PHASE pins.
BAND GAP
REFERENCE
1.26V
12kΩ
3.6kΩ
VID4
VID3
2.7kΩ
5.4kΩ
VID2
VID1
VID0
ERROR
AMPLIFIER
DACOUT
+
-
+
COMP
-
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (VE/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of VIN at the
PHASE node. The PWM wave is smoothed by the output
filter (LO and CO).
1.7kΩ
10.7kΩ
21.5kΩ
DAC
Feedback Compensation
FB
2.9kΩ
FIGURE 5. DAC FUNCTION SCHEMATIC
BOOT
Application Guidelines
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
VIN
HIP6004
VCC
SS
VOUT
PHASE
+12V
GND
FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
OSC
Q1
LO
PHASE
PWM
COMPARATOR
VOUT
CIN
CO
LO
-
DRIVER
+
PGND
VE/A
RETURN
ZFB
-
FIGURE 6. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 6 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors CIN
and CO each represent numerous physical capacitors.
Locate the HIP6004 within 3 inches of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the HIP6004 must be sized to
handle up to 1A peak current.
ERROR
AMP
VOUT
CO
ESR
(PARASITIC)
ZIN
+
7
PHASE
LOAD
D2
VIN
DRIVER
Δ VOSC
Q2
CO
Q2
CVCC
CSS
HIP6004
LGATE
Q1 LO
CBOOT
Layout Considerations
UGATE
+VIN
D1
LOAD
12kΩ
REFERENCE
DETAILED COMPENSATION COMPONENTS
C2
C1
ZFB
VOUT
ZIN
C3
R2
R3
R1
COMP
-
FB
+
HIP6004
DACOUT
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
HIP6004
Modulator Break Frequency Equations
1
F LC = --------------------------------------2π • L O • C O
1
F ESR = ---------------------------------------2π • ESR • C O
The compensation network consists of the error amplifier
(internal to the HIP6004) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1STZero Below Filter’s Double Pole (~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
1
F Z1 = ---------------------------------2π • R2 • C1
1
F P1 = -----------------------------------------------------C1 • C2
2π • R 2 • ⎛ ----------------------⎞
⎝ C1 + C2⎠
F Z2 = 2π • ( R1 + R3 ) • C3
1
F P2 = ---------------------------------2π • R3 • C3
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 9. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 9 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
8
100
FZ1 FZ2
FP1
FP2
80
OPEN LOOP
ERROR AMP GAIN
60
GAIN (dB)
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ΔVOSC .
40
20
20LOG
(R2/R1)
0
20LOG
(VIN/ΔVOSC)
MODULATOR
GAIN
-20
-40
-60
COMPENSATION
GAIN
CLOSED LOOP
GAIN
FLC
10
100
1K
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1μF ceramic
capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
HIP6004
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
ΔI =
VIN - VOUT VOUT
•
Fs x L
VIN
ΔVOUT = ΔI x ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6004 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
level equal to DACOUT, tFALL is the longest response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
9
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The HIP6004 requires 2 N-Channel power MOSFETs.
These should be selected based upon rDS(ON) , gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor (see the
equations below). Only the upper MOSFET has switching
losses, since the Schottky rectifier clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not
adequately model power loss due the reverse-recovery of the
lower MOSFETs body diode. The gate-charge losses are
dissipated by the HIP6004 and don't heat the MOSFETs.
However, large gate-charge increases the switching interval,
tSW which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature and air flow.
PUPPER = Io2 x rDS(ON) x D + 1 Io x VIN x tSW x FS
2
2
PLOWER = Io x rDS(ON) x (1 - D)
Where: D is the duty cycle = VOUT / VIN ,
tSW is the switching interval, and
FS is the switching frequency.
Standard-gate MOSFETs are normally recommended for
use with the HIP6004. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-tosource voltage rating determine whether logic-level
MOSFETs are appropriate.
HIP6004
+12V
VCC
HIP6004
+12V
DBOOT
BOOT
CBOOT
UGATE
HIP6004
Q1
-
Q2
PGND
D2
NOTE:
VG-S ≈ VCC
GND
FIGURE 10. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from VCC. The boot capacitor, CBOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of VCC
less the boot diode drop (VD) when the lower MOSFET, Q2
turns on. Logic-level MOSFETs can only be used if the
MOSFETs absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC .
Figure 11 shows the upper gate drive supplied by a direct
connection to VCC . This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak upper gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and +12VDC
for the bias, the gate-to-source voltage of Q1 is 7V. A logiclevel MOSFET is a good choice for Q1 and a logic-level
MOSFET can be used for Q2 if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to VCC .
10
Q1
PHASE
NOTE:
VG-S ≈ VCC -VD
LGATE
BOOT
UGATE
PHASE
+
+5V OR LESS
VCC
+5V or +12V
+ VD -
-
+
LGATE
PGND
GND
NOTE:
VG-S ≈ VCC -5V
Q2
D2
NOTE:
VG-S ≈ VCC
FIGURE 11. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
HIP6004
HIP6004 DC-DC Converter Application Circuit
Materials and circuit board description, can be found in
Application Note AN9672.
Figure 12 shows an application circuit of a DC-DC Converter
for an Intel Pentium Pro microprocessor. Detailed
information on the circuit, including a complete Bill-of-
VIN =
L1 - 1μH
F1
+5V
OR
+12V
C1
5x 1000μF
2x 1μF
2N6394
+12V
2K
D1
0.1μF
1000pF
VSEN 1
RT
VID0
VID1
VID2
VID3
VID4
FB
OVP
18
19
2 OCSET
MONITOR
AND
PROTECTION
SS 3
0.1μF
VCC
20
4
5
6
7
8
1K
12 PGOOD
15 BOOT
OSC
14 UGATE
13 PHASE
HIP6004
-
-
17 LGATE
+
+
16 PGND
9
11
COMP
2.2nF
GND
20K
8.2nF
0.1μF
15
Component Selection Notes;
C0 - 9 Each 1000μF 6.3W VDC, Sanyo MV-GX or Equivalent
C1 - 5 Each 330μF 25W VDC, Sanyo MV-GX or Equivalent
L2 - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG
L1 - Core: Micrometals T50-52; Winding: 5 Turns of 18AWG
D1 - 1N4148 or Equivalent
D2 - 3A, 40V Schottky, Motorola MBR340 or Equivalent
Q1, Q2 - Intersil MOSFET; RFP70N03
FIGURE 12. PENTIUM PRO DC-DC CONVERTER
11
L2
3μH
D/A
10
1.33K
0.1μF
Q1
Q2
D2
CO
9x 1000μF
+VO
HIP6004
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
N
INDEX
AREA
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
0.25(0.010) M
H
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
e
µα
B S
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
20
0o
20
8o
0o
7
8o
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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12
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