SIGNS NEW DE R O F D NT NDE LACEME at COMME P E E R R T D O E N r D rt Cente OMMEN N O REC al Suppo il.com/tsc ic n h c e T s ter our Sheet January 3, 2006 r www.in contact Data ERSIL o T N -I 8 8 1-8 ACPI Regulator/Controller for Dual Channel DDR Memory Systems ISL6548 FN9188.2 Features The ISL6548 provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply VDDQ during S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. Two LDO controllers are also integrated for the GMCH core voltage regulation and for the GMCH/CPU VTT termination voltage regulation. The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of 2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V. An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH/CPU VTT termination voltage is within spec and operational. Each output is monitored for undervoltage events. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated. • Generates 4 Regulated Voltages - Synchronous Buck PWM Controller for DDR VDDQ - 3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference for DDR VTT - LDO Regulator for GMCH Core - Sink/Source LDO Regulator for CPU/GMCH VTT Termination • ACPI Compliant Sleep State Control • Glitch-free Transitions During State Changes • PWM Controller Drives Low Cost N-Channel MOSFETs • 250kHz Constant Frequency Operation • Tight Output Voltage Regulation - All Outputs: 2% Over Temperature • Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications • Simple Single-Loop Voltage-Mode PWM Control Design • Fast PWM Converter Transient Response • Under and Overvoltage Monitoring on All Outputs • OCP on the Switching Regulator • Integrated Thermal Shutdown Protection • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs Pinout ISL6548 (6x6 QFN) TOP VIEW LGATE GND UGATE BOOT PHASE S5# OCSET • Graphics Cards - GPU and Memory Supplies 28 27 26 25 24 23 22 • ASIC Power Supplies • Embedded Processor and I/O Supplies • DSP Supplies 5VSBY 1 21 DRIVE4 S3# 2 20 REFADJ4 P12V 3 19 DRIVE3 PART PART NUMBER MARKING GND 4 18 FB3 DDR_VTT 5 DDR_VTT VDDQ GND 29 Ordering Information TEMP. RANGE (°C) PACKAGE PKG. DWG. # 7 15 FB 28 Ld 6x6 QFN L28.6x6 Tape and Reel (Pb-free) 8 9 10 11 12 13 14 VREF_IN 0 to 70 DRIVE2_L ISL6548CRZA-T ISL6548CRZ (Note) VIDPGD 16 COMP FB2 6 DRIVE2_U 28 Ld 6x6 QFN L28.6x6 (Pb-free) DDR_VTTSNS 0 to 70 VDDQ ISL6548CRZ 17 FB4 ISL6548CRZA (Note) 1 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Block Diagram 5VSBY S3# S5# FB COMP VDDQ P12V BOOT RGU EA4 EA1 DRIVE4 2 RGL FB4 P12V POR GMCH DUAL LDO UGATE PWM REFADJ4 5VSBY P12V MONITOR AND CONTROL EA3 FAULT DRIVE3 250kHz P12V EA2 DRIVE2_U PHASE OC COMP VOLTAGE REFERENCE OCSET 20A S3 0.800V VTTSNS 0.680V (-15%) 0.920V (+15%) FB2 P12V VDDQ(2) VTT REG VTT(2) UV/OV RU UV UV VREF_IN UV/OV RL VIDPGD GND PAD GND(2) ISL6548 SOFTSTART & ENABLE A SOFTSTART & ENABLE B SOFTSTART & ENABLE C ENABLE VIDPGD ENABLE DDR_VTT FB3 DRIVE2_L LGATE OSCILLATOR FN9188.2 January 3, 2006 ISL6548 Simplified Power System Diagram 12V 5VSBY VDDQ 5VDUAL SLEEP STATE LOGIC SLP_S3 SLP_S5 Q1 VDDQ PWM CONTROLLER Q3 Q2 TWO STAGE LINEAR CONTROLLER Q4 + VGMCH ISL6548 + VREF VTT REGULATOR LINEAR CONTROLLER Q5 VTT VTT_GMCH/CPU + + Q6 Typical Application 5VSBY 12V SLP_S5 SLP_S3 S5# DBOOT BOOT ROCSET OCSET S3# DRIVE4 Q3 P12V VIDPGD VDDQ_DDR 5VSBY 5VDUAL FB4 ISL6548 CBOOT Q1 UGATE VDDQ_DDR PHASE + REFADJ4 DRIVE3 Q4 VGMCH R5 DDR_VDDQ(x2) COMP FB3 Q2 LGATE R2 C1 C2 R3 C3 R6 FB R4 DRIVE2_U Q5 R7 VTT_GMCH/CPU VREF_IN FB2 R8 DDR_VTT(x2) DRIVE2_L Q6 R1 VTT_DDR DDR_VTTSNS GND 3 FN9188.2 January 3, 2006 ISL6548 Absolute Maximum Ratings Thermal Information 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance JA (°C/W) JC (°C/W) QFN Package (Notes 1, 2) . . . . . . . . . 32 4 Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C Recommended Operating Conditions Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10% Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 5.50 7.00 8.00 mA - 700 850 A Rising 5VSBY POR Threshold 4.10 - 4.45 V Falling 5VSBY POR Threshold 3.60 - 3.95 V Rising P12V POR Threshold 10.0 - 10.5 V Falling P12V POR Threshold 8.80 - 9.75 V 5VSBY SUPPLY CURRENT Nominal Supply Current ICC_S0 S3# & S5# HIGH, UGATE/LGATE Open ICC_S5 S5# LOW, S3# Don’t Care, UGATE/LGATE Open POWER-ON RESET OSCILLATOR AND SOFT-START PWM Frequency fOSC 220 250 280 kHz Ramp Amplitude VOSC - 1.5 - V Soft-Start Interval tSS 6.5 8.2 9.5 ms VREF - 0.800 - V -2.0 - +2.0 % - 80 - dB GBWP 15 - - MHz SR - 6 - V/s Low Level Input Threshold 0.75 - - V High Level Input Threshold - - 2.2 V REFERENCE VOLTAGE Reference Voltage System Accuracy VDDQ PWM CONTROLLER ERROR AMPLIFIER DC Gain Guaranteed By Design Gain-Bandwidth Product Slew Rate CONTROL I/O (S3# and S5#) 4 FN9188.2 January 3, 2006 ISL6548 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER GATE DRIVERS UGATE and LGATE Source IGATE - -0.8 - A UGATE and LGATE Sink IGATE - 0.8 - A Upper Divider Impedance RU - 2.5 - k Lower Divider Impedance RL - 2.5 - k Periodic load applied with 30% duty cycle and 10ms period using ISL6548_6506EVAL1 evaluation board (see Application Note AN1123) -3 - 3 A Guaranteed By Design - 80 - dB GBWP 15 - - MHz SR - 6 - V/s 9.75 10.0 - V - 0.16 0.50 V VTT REGULATOR Maximum VTT Load Current IVTT_MAX LINEAR REGULATORS DC GAIN Gain Bandwidth Product Slew Rate DRIVEn High Output Voltage DRIVEn unloaded DRIVEn Low Output Voltage DRIVEn High Output Source Current VFB = 770mV; VDRIVEn = 0V - 1.7 - mA DRIVEn Low Output Sink Current VFB = 830mV; VDRIVEn = 10V - 1.2 - mA VIDPGD VTT_GMCH/CPU Rising Threshold S0 0.725 0.74 - V VTT_GMCH/CPU Falling Threshold S0 - 0.70 0.715 V 18 20 22 A -3.3 - 3.3 A PROTECTION OCSET Current Source IOCSET VTT_DDR Current Limit By Design VDDQ OV Level VFB/VREF S0/S3 - 115 - % VDDQ UV Level VFB/VREF S0/S3 - 85 - % VTT_DDR OV Level VTT/VVREF_IN S0 - 115 - % VTT_DDR UV Level VTT/VVREF_IN S0 - 85 - % VGMCH UV Level VFB4/VREF S0 - 85 - % VTT_GMCH/CPU UV Level VFB2/VREF S0 - 85 - % By Design - 140 - °C Thermal Shutdown Limit TSD 5 FN9188.2 January 3, 2006 ISL6548 Functional Pin Description 5VSBY (Pin 1) PHASE (Pin 24) 5VSBY is the bias supply of the ISL6548. It is typically connected to the 5V standby rail of an ATX power supply. During S4/S5 sleep states the ISL6548 enters a reduced power mode and draws less than 1mA (ICC_S5) from the 5VSBY supply. The supply to 5VSBY should be locally bypassed using a 0.1F capacitor. Connect this pin to the upper MOSFET’s source. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection. P12V (Pin 3) The VTT regulation circuit and the Linear Drivers are powered by P12V. P12V is not required during S3/S4/S5 operation. P12V is typically connected to the +12V rail of an ATX power supply. GND (Pins 4, 27, 29) OCSET (Pin 22) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 20A current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter overcurrent (OC) trip point according to the following equation: I OCSET xR OCSET I PEAK = ------------------------------------------------r DS ON An overcurrent trip cycles the soft-start function. The GND terminals of the ISL6548 provide the return path for the VTT LDO, and switching MOSFET gate drivers. High ground currents are conducted directly through the exposed paddle of the QFN package which must be electrically connected to the ground plane through a path as low in inductance as possible. The VDDQ pins should be connected externally together to the regulated VDDQ output. During S0/S1 states, the VDDQ pins serve as inputs to the VTT regulator and to the VTT Reference precision divider. UGATE (Pin 26) DDR_VTT (Pins 5, 6) Connect this pin to the upper MOSFET’s gate. This pin provides the PWM-controlled gate drive for the upper MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the upper MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective. The DDR_VTT pins should be connect externally together. During S0/S1 states, the DDR_VTT pins serve as the outputs of the VTT linear regulator. During S3 state, the VTT regulator is disabled. LGATE (Pin 28) Connect this pin to the lower MOSFET’s gate. This pin provides the PWM-controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the lower MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the lower MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective. FB (Pin 15) and COMP (Pin 16) The VDDQ switching regulator employs a single voltage control loop. FB is the negative input to the voltage loop error amplifier. The VDDQ output voltage is set by an external resistor divider connected to FB. With a properly selected divider, VDDQ can be set to any voltage between the power rail (reduced by converter losses) and the 0.8V reference. Loop compensation is achieved by connecting an AC network across COMP and FB. The FB pin is also monitored for under and overvoltage events. 6 VDDQ (Pins 7, 8) DDR_VTTSNS (Pin 9) VTTSNS is used as the feedback for control of the VTT linear regulator. Connect this pin to the VTT output at the physical point of desired regulation. VREF_IN (Pin 14) A capacitor, CSS, connected between VREF_IN and ground is required. This capacitor and the parallel combination of the Upper and Lower Divider Impedance (RU||RL), sets the time constant for the start up ramp when transitioning from S3/S4/S5 to S0/S1/S2. The minimum value for CSS can be found through the following equation: C VTTOUT V DDQ C SS -----------------------------------------------10 2A R U R L The calculated capacitance, CSS, will charge the output capacitor bank on the VTT rail in a controlled manner without reaching the current limit of the VTT LDO. BOOT (Pin 25) This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-channel MOSFET. FN9188.2 January 3, 2006 ISL6548 Functional Description FB2 (Pin 11) Connect the output of the VTT_GMCH/CPU linear regulator to this pin through a properly sized resistor divider. The voltage at this pin is regulated to 0.8V. This pin is monitored for undervoltage events. DRIVE2 _U (Pin 10) This pin provides the gate voltage for the VTT_GMCH/CPU linear regulator upper pass transistor. Connect this pin to the gate terminal of an external N-Channel MOSFET transistor. DRIVE2 _L (Pin 13) This pin provides the gate voltage for the VTT_GMCH/CPU linear regulator lower pass transistor. Connect this pin to the gate terminal of an external N-Channel MOSFET transistor. FB3 (Pin 18) Connect the output of the lower VGMCH linear regulator to this pin through a properly sized resistor divider. The voltage at this pin is regulated to 0.8V. This pin is monitored for undervoltage events. DRIVE3 (Pin 19) This pin provides the gate voltage for the lower VGMCH linear regulator pass transistor. Connect this pin to the gate terminal of an external N-Channel MOSFET transistor. Overview The ISL6548 provides complete control, drive, protection and ACPI compliance for a regulator powering DDR memory systems and the GMCH core and GMCH/CPU termination rails. It is primarily designed for computer applications powered from an ATX power supply. A 250kHz Synchronous Buck Regulator with a precision 0.8V reference provides the proper Core voltage to the system memory of the computer. An internal LDO regulator with the ability to both sink and source current tracks the VDDQ output by 50% and provides the VTT termination voltage. A dual stage LDO controller provides the GMCH core voltage. A third LDO controller is included for the regulation of the GMCH/CPU termination rail. ACPI compliance is realized through the SLP_S3 and SLP_S5 sleep signals and through monitoring of the 12V ATX bus. Initialization Connect the output of the upper VGMCH linear regulator to this pin. The voltage at this pin is regulated via the RAFADJ4 pin. The ISL6548 automatically initializes upon receipt of input power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input bias supply voltages. The POR monitors the bias voltage at the 5VSBY and P12V pins. The POR function initiates soft-start operation after the bias supply voltages exceed their POR thresholds. DRIVE4 (Pin 21) ACPI State Transitions This pin provides the gate voltage for the upper VGMCH linear regulator pass transistor. Connect this pin to the gate terminal of an external N-Channel MOSFET transistor. Figure 1 shows how the individual regulators are controlled during all state transitions. All references to timing in this section are in reference to Figure 1. REFADJ4 (Pin 20) Cold Start (S4/S5 to S0 Transition) This pin controls the reference for the upper VGMCH linear regulator. To insure that both upper and lower pass transistors dissipate the same power, tie this pin to the VGMCH output rail. At the onset of a mechanical start, time t0 in Figure 1, the ISL6548 receives its bias voltage from the 5V Standby bus (5VSBY). Once the 5VSBY rail has exceeded the POR threshold, the ISL6548 will remain in an internal S5 state until both the SLP_S3 and SLP_S5 signal have transitioned high and the 12V POR threshold has been exceeded by the +12V rail from the ATX, which occurs at time t1. FB4 (Pin 17) VIDPGD (Pin 12) The VIDPGD pin is an open-drain logic output that changes to a logic low if the VTT_GMCH/CPU linear regulator is out of regulation in S0/S1/S2 state. VIDPGD will always be low in any state other than S0/S1/S2. S5# (Pin 23) This pin accepts the SLP_S5# sleep state signal. S3# (Pin 2) This pin accepts the SLP_S3# sleep state signal. Once all of these conditions are met, the PWM error amplifier will first be reset by internally shorting the COMP pin to the FB pin. This reset lasts for three soft-start cycles, which is typically 24ms (one soft-start cycle is typically 8.2ms). The digital soft-start sequence will then begin. Each regulator is enabled and soft-started according to a preset sequence. At time t2, the 3 soft-start cycle reset has ended and the VDDQ_DDR rail and the upper VGMCH LDO are digitally softstarted. 7 FN9188.2 January 3, 2006 SLP_S3# SLP_S5# 8 12V POR 12V 0V VDDQ_DDR 0V VTT_DDR Soft-Start Rise Time Dependent Upon Capacitor On VREF_IN Pin VDDQ_DDR VTT_DDR ISL6548 VTT_DDR FLOATING 0V VGMCH_UPPER 0V VGMCH 0V VTT_GMCH/CPU 0V VIDPGD t0 (3 SOFTSTART CYCLES) t1 t2 t3 t4 t5 t6 t7 t8 (3 SOFTSTART CYCLES) t10 t9 FN9188.2 January 3, 2006 FIGURE 1. ISL6548 TIMING DIAGRAM t11 t12 t13 t14 t15 ISL6548 The digital soft-start for the PWM regulator is accomplished by clamping the error amplifier reference input to a level proportional to the internal digital soft-start voltage. As the softstart voltage slews up, the PWM comparator generates PHASE pulses of increasing width that charge the output capacitor(s). This method provides a rapid and controlled output voltage rise. The linear regulators, with the exception of the internal VTT_DDR LDO, are soft-started in a similar manner. The error amplifier reference is clamped to the internal digital soft-start voltage. As the soft-start voltage ramps up, the respective DRIVE pin voltages increase, thus enhancing the N-MOSFETs and charging the output capacitors in a controlled manner. At time t3, the VDDQ_DDR and upper VGMCH LDO output rails are in regulation and the lower VGMCH LDO is softstarted. At time t4, the VGMCH rail is in regulation and the VTT_GMCH/CPU linear regulator is soft-started. At time t5, the VTT_GMCH/CPU rail is in regulation and the VTT_DDR internal regulator is soft-started. The VTT_DDR LDO soft-starts in a manner unlike the other regulators. When the VTT_DDR regulator is disabled, the reference is internally shorted to the VTT_DDR output. This allows the termination voltage to float during the S3 sleep state. When the ISL6548 enables the VTT_DDR regulator or enters S0 state from a sleep state, this short is released and the internal divide down resistors which set the VTT_DDR voltage to 50% of VDDQ_DDR will provide a controlled voltage rise on the capacitor that is tied to the VREF_IN pin. The voltage on this capacitor is the reference for the VTT_DDR regulator and the output will track it as it settles to 50% of the VDDQ voltage. The combination of the internal resistors and the VREF_IN capacitor will determine the rise time of the VTT_DDR regulator (see the Functional Pin Description section for proper sizing of the VREF_IN capacitor). At time t6, a full soft-start cycle has passed from the time that the VTT_DDR regulator was enabled. At this time the VIDPGD comparator is enabled. Once enabled if the VTT_GMCH/CPU output is within regulation, the VIDPGD pin will be forced to a high impedance state. Active to Sleep (S0 to S3 Transition) When SLP_S3 goes LOW with SLP_S5 still HIGH, the ISL6548 will disable all the regulators except for the VDDQ regulator, which is continually supplied by the 5VDUAL rail. VIDPGD will also transition LOW. When VTT is disabled, the internal reference for the VTT regulator is internally shorted to the VTT rail. This allows the VTT rail to float. When floating, the voltage on the VTT rail will depend on the leakage characteristics of the memory and MCH I/O pins. It is important to note that the VTT rail may not bleed down to 0V. Figure 1 shows how the individual regulators are affected by the S3 state at time t7. 9 Sleep to Active (S3 to S0 Transition) When SLP_S3 transitions from LOW to HIGH with SLP_S5 held HIGH and after the 12V rail exceeds POR, the ISL6548 will initiate the soft-start sequence. This sequence is very similar to the mechanical start soft-start sequencing. The transition from S3 to S0 is represented in Figure 1 between times t8 and t14. At time t8, the SLP_S3 signal transitions HIGH. This enables the ATX, which brings up the 12V rail. At time t9, the 12V rail has exceeded the POR threshold and the ISL6548 enters a reset mode that lasts for 3 soft-start cycles. At time t10, the 3 soft-start cycle reset is ended and the individual regulators are enabled and soft-started in the same sequence as the mechanical cold start sequence, with the exception that the VDDQ regulator is already enabled and in regulation. Active to Shutdown (S0 to S5 Transition) When the system transitions from active, S0, state to shutdown, S4/S5, state, the ISL6548 IC disables all regulators and forces the VIDPGD pin LOW. This transition is represented on Figure 1 at time t15. Fault Protection The ISL6548 monitors the VDDQ regulator for under and overvoltage events. The VDDQ regulator also has overcurrent protection. The internal VTT_DDR LDO regulator is monitored for under and overvoltage events. All other regulators are monitored for undervoltage events. An overvoltage event on either the VDDQ or VTT_DDR regulator will cause an immediate shutdown of all regulators. This can only be cleared by toggling the SLP_S5 signal such that the system enters the S5 sleep state and then transitions back to the active, S0, state. If a regulator experiences any other fault condition (an undervoltage or an overcurrent on VDDQ), then that regulator, and only that regulator, will be disabled and an internal fault counter will be incremented by 1. If the disabled regulator is used as the input for another regulator, then that cascoded regulator will also experience a fault condition due to a loss of input. The cascoded regulator will be disabled and the fault counter incremented by 1. At every fault occurrence, the internal fault counter is incremented by 1 and an internal Fault Reset Counter is cleared to zero. The Fault Reset Counter will increment once for every clock cycle (1 clock cycle is typically 1/250kHz, or 4s). If the Fault Reset Counter reaches a count of 16384 before another fault occurs, then the Fault Counter is cleared to 0. If a fault occurs prior to the Fault Reset Counter reaching a count of 16384, then the Fault Reset Counter is set back to zero. The ISL6548 will immediately shut down when the Fault Counter reaches a count of 4 when the system is restarting from an S5 state into the active, or S0, state. The ISL6548 FN9188.2 January 3, 2006 ISL6548 will immediately shut down when the Fault Counter reaches a count of 5 at any other time. The 16384 counts that are required to reset the Fault Reset Counter represent 8 soft-start cycles, as one soft-start cycle is 2048 clock cycles. This allows the ISL6548 to attempt at least one full soft-start sequence to restart the faulted regulators. When attempting to restart a faulted regulator, the ISL6548 will follow the preset start up sequencing. If a regulator is already in regulation, then it will not be affected by the start up sequencing. VDDQ Overcurrent Protection The overcurrent function protects the switching converter from a shorted output by using the upper MOSFET on-resistance, rDS(ON), to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the overcurrent trip level (see Typical Application diagrams on page 3). An internal 20A (typical) current sink develops a voltage across ROCSET that is referenced to the converter input voltage. When the voltage across the upper MOSFET (also referenced to the converter input voltage) exceeds the voltage across ROCSET, the overcurrent function initiates a soft-start sequence. The initiation of soft-start may affect other regulators. The VTT_DDR regulator is directly affected as it receives it’s reference and input from VDDQ. The overcurrent function will trip at a peak inductor current (IPEAK) determined by: I OCSET x R OCSET I PEAK = ---------------------------------------------------r DS ON Thermal Protection (S0/S3 State) If the ISL6548 IC junction temperature reaches a nominal temperature of 140°C, all regulators will be disabled. The ISL6548 will not re-enable the outputs until the junction temperature drops below 110°C and either the bias voltage is toggled in order to initiate a POR or the SLP_S5 signal is forced LOW and then back to HIGH. Shoot-Through Protection A shoot-through condition occurs when both the upper and lower MOSFETs are turned on simultaneously, effectively shorting the input voltage to ground. To protect from a shootthrough condition, the ISL6548 incorporates specialized circuitry on the VDDQ regulator which insures that complementary MOSFETs are not ON simultaneously. The adaptive shoot-through protection utilized by the VDDQ regulator looks at the lower gate drive pin, LGATE, and the upper gate drive pin, UGATE, to determine whether a MOSFET is ON or OFF. If the voltage from UGATE or from LGATE to GND is less than 0.8V, then the respective MOSFET is defined as being OFF and the other MOSFET is allowed to turned ON. This method allows the VDDQ regulator to both source and sink current. Since the voltage of the MOSFET gates are being measured to determine the state of the MOSFET, the designer is encouraged to consider the repercussions of introducing external components between the gate drivers and their respective MOSFET gates before actually implementing such measures. Doing so may interfere with the shootthrough protection. Application Guidelines Layout Considerations where IOCSET is the internal OCSET current source (20A typical). The OC trip point varies mainly due to the MOSFET rDS(ON) variations. To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. I 3. Determine IPEAK for I PEAK > I OUT MAX + ---------- , 2 whereI is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. Layout is very important in high frequency switching converter design. With power devices switching efficiently at 250kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes these voltage spikes. As an example, consider the turn-off transition of the control MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in the ISL6548 switching converter. The switching components are the most 10 FN9188.2 January 3, 2006 ISL6548 A multi-layer printed circuit board is recommended. Figure 2 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the GATE pins to the MOSFET gates should be kept short and wide enough to easily handle the 1A of drive current. 12VATX P12V GNDP CBP 5VDUAL 5VSBY 5VSBY CIN CBP ISL6548 UGATE Q1 LGATE COMP Q2 C2 R1 FB C3 R3 R4 VDDQ VDDQ(2) VTT(2) VTT LOAD COUT2 Q3 DRIVE4 FB4 COUT3 Q4 DRIVE3 VGMCH R5 FB3 COUT4 LOAD R6 The critical small signal components include any bypass capacitors, feedback components, and compensation components. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors should be located as close as possible to the FB pin with vias tied straight to the ground plane as required. REFADJ4 Q5 DRIVE2_U VTT_GMCH/CPU R7 FB2 DRIVE2_L Q6 COUT4 LOAD R8 Feedback Compensation - PWM Buck Converter 11 COUT1 C1 R2 The switching components should be placed close to the ISL6548 first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible. Position the output inductor and output capacitors between the upper and lower MOSFETs and the load. The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC . VDDQ PHASE In order to dissipate heat generated by the internal VTT LDO, the ground pad, pin 29, should be connected to the internal ground plane through at least four vias. This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. Figure 3 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). L1 LOAD critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. GND PAD KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 2. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS FN9188.2 January 3, 2006 ISL6548 PWM COMPARATOR LO - VOSC Compensation Break Frequency Equations VIN DRIVER OSC DRIVER + PHASE VDDQ CO ESR (PARASITIC) ZFB VE/A - ZIN + REFERENCE ERROR AMP DETAILED COMPENSATION COMPONENTS ZFB C1 C2 VDDQ ZIN C3 R2 R3 R1 COMP FB + R4 ISL6548 REFERENCE R V DDQ = 0.8 1 + ------1- R 4 FIGURE 3. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN AND OUTPUT VOLTAGE SELECTION 1 F Z1 = -----------------------------------2 x R 2 x C 1 1 F P1 = -------------------------------------------------------- C 1 x C 2 2 x R 2 x ---------------------- C1 + C2 1 F Z2 = ------------------------------------------------------2 x R 1 + R 3 x C 3 1 F P2 = -----------------------------------2 x R 3 x C 3 Figure 4 shows an asymptotic plot of the DC/DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 4. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 4 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. 100 FZ1 FZ2 FP1 FP2 80 Modulator Break Frequency Equations 1 F ESR = -------------------------------------------2 x ESR x C O The compensation network consists of the error amplifier (internal to the ISL6548) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC). 3. Place 2ND Zero at Filter’s Double Pole. 4. Place 1ST Pole at the ESR Zero. 5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier’s Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary. 12 GAIN (dB) 1 F LC = ------------------------------------------2 x L O x C O OPEN LOOP ERROR AMP GAIN 60 40 20 20LOG (R2/R1) 20LOG (VIN/VOSC) 0 COMPENSATION GAIN MODULATOR GAIN -20 -40 -60 CLOSED LOOP GAIN FLC 10 100 1K FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN Output Voltage Selection The output voltage of the all the external voltage regulators converter can be programmed to any level between their individual input voltage and the internal reference, 0.8V. An external resistor divider is used to scale the output voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier, refer to the Typical Application on page 3. FN9188.2 January 3, 2006 ISL6548 The output voltage programming resistor will depend on the value chosen for the feedback resistor and the desired output voltage of the particular regulator. impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. R1 0.8V R4 = ----------------------------------V DDQ – 0.8V Output Capacitor Selection - LDO Regulators The output capacitors used in LDO regulators are used to provide dynamic load current. The amount of capacitance and type of capacitor should be chosen with this criteria in mind. R5 0.8V R6 = ---------------------------------------V GMCH – 0.8V Output Inductor Selection R7 0.8V R8 = ------------------------------------------------------------V TT_GMCH/CPU – 0.8V If the output voltage desired is 0.8V, simply route the output voltage back to the respective FB pin through the feedback resistor and do not populate the output voltage programming resistor. The output voltage for the internal VTT_DDR linear regulator is set internal to the ISL6548 to track the VDDQ voltage by 50%. There is no need for external programming resistors. Component Selection Guidelines Output Capacitor Selection - PWM Buck Converter An output capacitor is required to filter the inductor current and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. DDR memory systems are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s 13 The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: I = VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6548 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection - PWM Buck Converter Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the upper MOSFET FN9188.2 January 3, 2006 ISL6548 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of upper MOSFET and the source of lower MOSFET. The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. The maximum RMS current required by the regulator may be closely approximated through the following equation: I RMS MAX = V IN – V OUT V OUT 2 V OUT 2 1 -------------- I OUT + ------ ----------------------------- -------------- V IN V IN 12 L f s MAX For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. MOSFET Selection - PWM Buck Converter The ISL6548 requires 2 N-Channel power MOSFETs for switching power. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see the equations below). These equations assume linear voltage-current transitions 14 and do not adequately model power loss due the reverserecovery of the upper and lower MOSFET’s body diode. The gate-charge losses are dissipated in part by the ISL6548 and do not significantly heat the MOSFETs. However, large gatecharge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Approximate Losses while Sourcing current 2 1 P UPPER = Io r DS ON D + --- Io V IN t SW f s 2 PLOWER = Io2 x rDS(ON) x (1 - D) Approximate Losses while Sinking current PUPPER = Io2 x rDS(ON) x D 2 1 P LOWER = Io r DS ON 1 – D + --- Io V IN t SW f s 2 Where: D is the duty cycle = VOUT / VIN , tSW is the combined switch ON and OFF time, and fs is the switching frequency. MOSFET Selection - LDO The main criteria for selection of the linear regulator pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature. The power dissipated in the linear regulator is: P LINEAR I O V IN – V OUT where IO is the maximum output current and VOUT is the nominal output voltage of the linear regulator. FN9188.2 January 3, 2006 ISL6548 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L28.6x6 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJC ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 9 A3 b 0.20 REF 0.23 D 0.35 5, 8 6.00 BSC D1 D2 0.28 9 - 5.75 BSC 3.95 4.10 9 4.25 7, 8 E 6.00 BSC - E1 5.75 BSC 9 E2 3.95 e 4.10 4.25 7, 8 0.65 BSC - k 0.25 - - - L 0.35 0.60 0.75 8 L1 - - 0.15 10 N 28 2 Nd 7 3 Ne 7 3 P - - 0.60 9 - - 12 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN9188.2 January 3, 2006