2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter ISL85402 Features The ISL85402 is a synchronous buck controller with a 125mΩ high-side MOSFET and low-side driver integrated. The ISL85402 supports a wide input voltage range from 3V to 36V. Regarding the output current capability from the thermal perspective, the ISL85402 can typically support continuous load of 2.5A under conditions of 5V VOUT, VIN range of 8V to 30V, 500kHz, +85°C ambient temperature with still air. For any specific application, the actual maximum output current depends upon the die temperature not exceeding +125°C with the power dissipated in the IC, which is related to input voltage, output voltage, duty cycle, switching frequency, board layout and ambient temperature, etc. Refer to “Output Current” on page 13 for more details. The ISL85402 has flexible selection of operation modes of forced PWM mode and PFM mode. In PFM mode, the quiescent input current is as low as 180µA (AUXVCC connected to VOUT). The load boundary between PFM and PWM can be programmed to cover wide applications. • Ultra Wide Input Voltage Range 3V to 36V • Optional Mode Operation - Forced PWM Mode - Selectable PFM with Programmable PFM/PWM Boundary • 300µA IC Quiescent Current (PFM, No Load); 180µA Input Quiescent Current (PFM, No Load, VOUT Connected to AUXVCC) • Less than 3µA Standby Input Current (IC Disabled) • Operational Topologies - Synchronous Buck - Non-Synchronous Buck - Two-Stage Boost Buck • Programmable Frequency from 200kHz to 2.2MHz and Frequency Synchronization Capability • ±1% Tight Voltage Regulation Accuracy The low-side driver can be either used to drive an external low-side MOSFET for a synchronous buck, or left unused for a standard non-synchronous buck. The low-side driver can also be used to drive a boost converter as a pre-regulator followed by a buck controlled by the same IC, which greatly expands the operating input voltage range down to 3V or lower (Refer to “Typical Application Schematic III - Boost Buck Converter” on page 5). • Reliable Overcurrent Protection - Temperature Compensated Current Sense - Cycle-by-Cycle Current Limiting with Frequency Foldback - Hiccup Mode for Worst Case Short Condition • 20 Ld 4x4 QFN Package • Pb-Free (RoHS Compliant) The ISL85402 offers the most robust current protections. It uses peak current mode control with cycle-by-cycle current limiting. It is implemented with frequency foldback under current limit condition; besides that, the hiccup overcurrent mode is also implemented to guarantee reliable operations under harsh short conditions. The ISL85402 has comprehensive protections against various faults including overvoltage and over-temperature protections, etc. Applications • General Purpose • 24V Bus Power • Battery Power • Point of Load • Embedded Processor and I/O Supplies 100 95 VIN BOOT ISL85402 PHASE ILIMIT LGATE SS EXT_BOOST FS SGND VOUT EFFICIENCY (%) VIN SYNC AUXVCC VCC 6V VIN 90 PGOOD EN MODE 85 80 36V VIN 75 24V VIN 70 65 PGND 60 FB 55 COMP 12V VIN 50 0.1m 1m 10m 100m 1.0 2.5 LOAD CURRENT (A) FIGURE 1. TYPICAL APPLICATION September 29, 2011 FN7640.0 1 FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE, VOUT 5V, TA = +25°C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL85402 Pin Configuration AUXVCC VCC SGND VIN VIN ISL85402 (20 LD QFN) TOP VIEW 20 19 18 17 16 EN 1 15 BOOT 14 PGND 13 LGATE FS 2 SS 3 FB 4 12 SYNC COMP 5 11 EXT_BOOST 7 8 9 MODE PGOOD PHASE 10 PHASE 6 ILIMIT 21Pad Thermal 21 PAD Functional Pin Descriptions PIN NAME PIN # DESCRIPTION EN 1 The controller is enabled when this pin is left floating or pulled HIGH. The IC is disabled when this pin is pulled LOW. Range: 0V to 5.5V. FS 2 To connect this pin to VCC, or GND, or left open will force the IC to have 500kHz switching frequency. The oscillator switching frequency can also be programmed by adjusting the resistor from this pin to GND. SS 3 Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start interval of the converter. Also this pin can be used to track a ramp on this pin. FB 4 This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from VOUT to FB, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin is also monitored for overvoltage events. COMP 5 Output of the voltage feedback error amplifier. ILIMIT 6 Programmable current limit pin. With this pin connected to VCC pin, or to GND, or left open, the current limiting threshold is the set to default 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND. MODE 7 Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode when the peak inductor current is below the default threshold 700mA. The current boundary threshold between PFM and PWM can also be programmed with a resistor at this pin to ground. Check for more details in the “PFM Mode Operation” on page 12. PGOOD 8 PGOOD is an open drain output that will be pulled low immediately under the events when the output is out of regulation (OV or UV) or EN pin pulled low. PGOOD is equipped with a fixed delay of 1000 cycles upon output power-up (VO > 90%). PHASE 9, 10 EXT_BOOST 11 These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected the source of the high-side N-channel MOSFET. This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the controller will detect the voltage on this pin, if voltage on this pin is below 200mV, the controller is set in synchronous/non-synchronous buck mode and latch in this state unless VCC is below POR falling threshold; if the voltage on this pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state. In boost mode the low-side driver output PWM with same duty cycle with upper-side driver to drive the boost switch. In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled. In boost mode operation, PFM is disabled when boost PWM is enabled. Check the “Boost Converter Operation” on page 13 for more details. 2 FN7640.0 September 29, 2011 ISL85402 Functional Pin Descriptions PIN NAME (Continued) PIN # DESCRIPTION 12 This pin can be used to synchronize two or more ISL85402 controllers. Multiple ISL85402 can be synchronized with their SYNC pins connected together. 180 degree phase shift is automatically generated between the master and slave ICs. The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns). Range: 0V to 5.5V. This pin should be left floating if not used. LGATE 13 In synchronous buck mode, this Pin is used to drive the lower side MOSFET to improve efficiency. In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to VCC before VCC startup to have low-side driver (LGATE) disabled. In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is same with the buck control PWM. PGND 14 This pin is used as the ground connection of the power flow including driver. Connect it to large ground plane. BOOT 15 This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A 1µF ceramic capacitor is recommended to be used between BOOT and PHASE pin. SYNC Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET as well as the source for the internal linear regulator that provides the bias of the IC. Range: 3V to 36V. With the part switching, the operating input voltage applied to the VIN pins must be under 36V. This recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding Absolute Maximum Ratings. VIN 16, 17 SGND 18 This pin provides the return path for the control and monitor portions of the IC. Connect it to quite ground plane. VCC 19 This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF decoupling ceramic capacitor is recommended between VCC to ground. AUXVCC 7 PAD 21 This pin is the input of the auxiliary internal linear regulator which can be supplied by the regulator output after power-up. With such configuration, the power dissipation inside of the IC is reduced. The input range for this LDO is 3V to 20V. In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a resistor divider. When voltage on this pin is above 0.8V, the boost PWM disabled; and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled. Range: 0V to 20V. Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground copper plane with area as large as possible to effectively reduce the thermal impedance. Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL85402IRZ 85 402IRZ ISL85402EVAL1Z Evaluation Board TEMP. RANGE (°C) -40 to +85 PACKAGE (PB-Free) 20 Ld 4x4 QFN PKG. DWG. # L20.4x4C NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85402. For more information on MSL please see techbrief TB363. 3 FN7640.0 September 29, 2011 Block Diagram AUXVCC VCC PGOOD VIN (x2) VIN CURRENT MONITOR AUXILARY LDO BIAS LDO 4 ILIMIT POWER-ON RESET SGND VCC BOOT OCP, OVP, OTP PFM LOGIC BOOST MODE CONTROL EN EXT_BOOST PFM/FPWM PHASE (x2) GATE DRIVE VOLTAGE MONITOR SYNC FS SLOPE COMPENSATION LGATE OSCILLATOR + SOFT-START LOGIC VCC BOOT REFRESH 0.8V REFERENCE 5 µA EA SS + FB COMPARATOR COMP PGND ISL85402 MODE FN7640.0 September 29, 2011 ISL85402 Typical Application Schematic I PGOOD EN MODE SYNC AUXVCC VCC PGOOD EN MODE VIN VIN SYNC AUXVCC BOOT ISL85402 VIN V OUT PHASE BOOT VCC ILIMIT VIN ISL85402 V OUT PHASE ILIMIT LGATE SS EXT_BOOST FS SGND LGATE SS PGND PGND EXT_BOOST FS SGND FB COMP FB COMP (b) NON-SYNCHRONOUS BUCK (a) SYNCHRONOUS BUCK Typical Application Schematic II - VCC Switch-Over to VOUT PGOOD EN MODE SYNC AUXVCC VCC PGOOD EN MODE VIN VIN SYNC AUXVCC BOOT ISL85402 VCC VOUT PHASE EXT_BOOST FS SGND VIN BOOT ISL85402 PHASE V OUT ILIMIT ILIMIT SS VIN LGATE LGATE SS PGND PGND EXT_BOOST FS SGND FB COMP (a) SYNCHRONOUS BUCK FB COMP (b) NON-SYNCHRONOUS BUCK Typical Application Schematic III - Boost Buck Converter Battery + + R1 R2 PGOOD EN MODE EXT_BOOST AUXVCC SYNC VCC ILIMIT SS FS SGND 5 R3 LGATE R4 VIN ISL85402 BOOT PHASE V OUT PGND COMP FB FN7640.0 September 29, 2011 ISL85402 Absolute Maximum Ratings Thermal Information VIN, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +44V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.0V AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22V Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0V Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . +6.0V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V Latchup Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance θJA (°C/W) θJC (°C/W) ISL85402 QFN 4x4 Package (Notes 4, 5). . . . . . 40 3.5 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Supply Voltage on VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 36V AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20V Ambient Temperature Range (Industrial). . . . . . . . . . . . . . . . . . -40°C to +85°C Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +85°C. Typical are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS VIN PIN SUPPLY VIN Pin Voltage Range Operating Supply Current IQ Standby Supply Current IQ_SBY VIN Pin 3.05 36 V VIN Pin connected to VCC 3.05 5.5 V MODE = VCC/FLOATING (PFM), no load at the output 300 µA MODE = GND (Forced PWM), VIN = 12V, Non-switching 1.2 mA EN connected to GND, VIN = 12V 1.8 3 µA 4.5 4.8 V VIN = 4.2V, IVCC = 35mA 0.3 0.5 V VIN = 3V, IVCC = 25mA 0.25 0.3 V INTERNAL MAIN LINEAR REGULATOR MAIN LDO VCC Voltage VCC MAIN LDO Dropout Voltage VDROPOUT_MAIN VIN > 5V 4.2 VCC Current Limit of MAIN LDO 60 mA INTERNAL AUXILIARY LINEAR REGULATOR AUXVCC Input Voltage Range VAUXVCC AUX LDO VCC Voltage VCC LDO Dropout Voltage VDROPOUT_AUX 3 20 V 4.5 4.8 V VAUXVCC = 4.2V, IVCC = 35mA 0.3 0.5 V VAUXVCC = 3V, IVCC = 25mA 0.25 0.3 V VAUXVCC > 5V 4.2 Current Limit of AUX LDO 60 AUX LDO Switch-over Rising Threshold VAUXVCC_RISE AUXVCC voltage rise; Switch to Auxiliary LDO AUX LDO Switch-over Falling Threshold Voltage VAUXVCC_FALL AUXVCC voltage fall; Switch back to main BIAS LDO AUX LDO Switch-over Hysteresis VAUXVCC_HYS AUXVCC Switch-over Hysteresis 6 mA 3 3.1 3.2 V 2.73 2.87 2.97 V 0.2 V FN7640.0 September 29, 2011 ISL85402 Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +85°C. Typical are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 2.82 2.9 3.05 V 2.8 V POWER-ON RESET Rising VCC POR Threshold VPORH_RISE Falling VCC POR Threshold VPORL_FALL 2.6 VCC POR Hysteresis VPORL_HYS 0.3 V ENABLE Required Enable On Voltage VENH Required Enable Off voltage VENL 2 V 0.8 V OSCILLATOR PWM Frequency FOSC RFS = 665kΩ 160 200 240 kHz RFS = 51.1kΩ 1950 2200 2450 kHz FS Pin Connected to VCC or Floating or GND 450 500 550 kHz MIN ON Time tMIN_ON 130 225 ns MIN OFF Time tMIN_OFF 210 325 ns VREF 0.8 REFERENCE VOLTAGE Reference Voltage System Accuracy -1.0 FB Pin Source Current V +1.0 5 % nA SOFT-START Soft-Start Current ISS 3 5 7 µA ERROR AMPLIFIER Unity Gain-Bandwidth CLOAD = 50pF 10 MHz DC Gain CLOAD = 50pF 88 dB Maximum Output Voltage 3.6 V Minimum Output Voltage 0.5 V 5 V/µs 700 mA Slew Rate SR CLOAD = 50pF PFM MODE CONTROL Default PFM Current Threshold MODE = VCC or Floating INTERNAL HIGH-SIDE MOSFET Upper MOSFET rDS(ON) rDS(ON)_UP 125 180 mΩ LOW-SIDE MOSFET GATE DRIVER LGate Source Resistance 100mA Source Current 3.5 Ω LGATE Sink Resistance 100mA Sink Current 3.3 Ω BOOST CONVERTER CONTROL EXT_BOOST Boost_Off Threshold Voltage EXT_BOOST Hysteresis Sink Current IEXT_BOOST_HYS AUXVCC Boost Turn-Off Threshold Voltage AUXVCC Hysteresis Sink Current IAUXVCC_HYS 7 0.74 0.8 0.86 V 2.4 3.2 3.8 µA 0.74 0.8 0.86 V 2.4 3.2 3.8 µA FN7640.0 September 29, 2011 ISL85402 Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +85°C. Typical are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP 104 110 MAX (Note 6) UNITS POWER-GOOD MONITOR Overvoltage Rising Trip Point VFB/VREF Percentage of Reference Point Overvoltage Rising Hysteresis VFB/VOVTRIP Percentage Below OV Trip Point Undervoltage Falling Trip Point VFB/VREF Percentage of Reference Point Undervoltage Falling Hysteresis VFB/VUVTRIP Percentage Above UV Trip Point 3 % fOSC = 500kHz 2 ms PGOOD HIGH, VPGOOD = 4.5V 10 nA 0.10 V PGOOD Rising Delay tPGOOD_DELAY PGOOD Leakage Current 116 % 3 84 % 90 96 % VPGOOD PGOOD LOW, IPGOOD = 0.2mA Default Cycle-by-Cycle Current Limit Threshold IOC_1 ILIMIT = GND or VCC or Floating Hiccup Current Limit Threshold IOC_2 Hiccup, IOC_2/IOC_1 115 % Percentage of Reference Point 120 % 110 % 102.5 % Over-Temperature Trip Point 155 °C Over-Temperature Recovery Threshold 140 °C PGOOD Low Voltage OVERCURRENT PROTECTION 3 3.6 4.2 A OVERVOLTAGE PROTECTION OV Latching-off Trip Point LG = UG = LATCH LOW OV Non-Latching-off Trip Point Percentage of Reference Point LG = UG = LOW OV Non-Latching-off Release Point Percentage of Reference Point OVER-TEMPERATURE PROTECTION NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.0 100 95 24V VIN 12V VIN 6V VIN 90 36V VIN EFFICIENCY (%) EFFICIENCY (%) Performance Curves 6V VIN 85 12V VIN 80 36V VIN 75 24V VIN 70 65 60 55 0.5 1.0 1.5 2.0 LOAD CURRENT (A) FIGURE 3. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM MODE, 500kHz, VOUT 5V, TA = +25°C 8 2.5 50 0.1m 1m 10m 100m 1.0 2.5 LOAD CURRENT (A) FIGURE 4. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE, VOUT 5V, TA = +25°C FN7640.0 September 29, 2011 ISL85402 4.970 4.970 4.968 4.968 4.966 4.966 4.964 4.964 IO = 0A 4.962 IO = 2A 4.960 4.958 4.956 4.962 VOUT (V) VOUT (V) Performance Curves (Continued) 4.954 4.952 5 10 15 20 25 INPUT VOLTAGE (V) 30 0.5 95 2.5 6V VIN 90 12V VIN 12V VIN 85 24V VIN 36V VIN 6V VIN 80 36V VIN 75 24V VIN 70 65 60 55 50 45 0.5 1.0 1.5 2.0 40 0.1m 2.5 FIGURE 7. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM MODE, 500kHz, VOUT 3.3V, TA = +25°C 1m 10m 100m LOAD CURRENT (A) 1.0 2.5 FIGURE 8. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE, VOUT 3.3V, TA = +25°C 85 200 80 180 IC DIE TEMPERATURE (°C) VIN = 12V 160 INPUT CURRENT (µA) 2.0 100 LOAD CURRENT (A) 140 120 VIN = 24V 100 80 60 40 20 0 -50 1.0 1.5 LOAD CURRENT (A) FIGURE 6. LOAD REGULATION, VOUT 5V, TA = +25°C EFFICIENCY (%) EFFICIENCY (%) 12V VIN 4.950 0.0 36 FIGURE 5. LINE REGULATION, VOUT 5V, TA = +25°C 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.0 36V VIN 4.956 4.952 0 6V VIN 4.958 IO = 1A 4.954 4.950 24V VIN 4.960 75 70 VO = 20V 65 60 55 50 45 VO = 12V VO = 5V 40 35 30 -25 0 25 50 75 100 AMBIENT TEMPERATURE (°C) FIGURE 9. INPUT QUIESCENT CURRENT UNDER NO LOAD, PFM MODE, VOUT = 5V 9 125 25 0 5 10 15 20 VIN (V) 25 30 35 40 FIGURE 10. IC DIE TEMPERATURE UNDER +25°C AMBIENT TEMPERATURE, STILL AIR, 500kHz, IO = 2A FN7640.0 September 29, 2011 ISL85402 Performance Curves (Continued) 85 IC DIE TEMPERATURE (°C) 80 VO = 20V 75 VOUT 2V/DIV 70 65 VO = 12V 60 VO = 5V 55 50 PHASE 20V/DIV 45 40 35 30 25 0 5 10 15 20 25 30 35 40 VIN (V) FIGURE 11. IC DIE TEMPERATURE UNDER +25°C AMBIENT TEMPERATURE, STILL AIR, 500kHz, IO = 2.5A 2ms/DIV FIGURE 12. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A, ENABLE ON VOUT 2V/DIV VOUT 2V/DIV PHASE 20V/DIV PHASE 20V/DIV 2ms/DIV FIGURE 13. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A, ENABLE OFF 2ms/DIV FIGURE 14. VIN 36V, PREBIASED START-UP VOUT 20mV/DIV (5V OFFSET) VOUT 100mV/DIV (5V OFFSET) IOUT 1A/DIV PHASE 20V/DIV PHASE 20V/DIV 5µs/DIV FIGURE 15. SYNCHRONOUS BUCK WITH FORCE PWM MODE, VIN 36V, IO 2A 10 1ms/DIV FIGURE 16. VIN 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE FN7640.0 September 29, 2011 ISL85402 Performance Curves (Continued) VOUT 200mV/DIV (5V OFFSET) VOUT 70mV/DIV (5V OFFSET) VOUT 1V/DIV LGATE 5V/DIV LGATE 5V/DIV IOUT 1A/DIV PHASE 20V/DIV PHASE 20V/DIV 100µs/DIV 1ms/DIV FIGURE 17. VIN 24V, 80mA LOAD, PFM MODE FIGURE 18. VIN 24V, 0 TO 2A STEP LOAD, PFM MODE VOUT 10mV/DIV (5V OFFSET) VOUT 10mV/DIV (5V OFFSET) PHASE 5V/DIV PHASE 10V/DIV 20µs/DIV 5µs/DIV FIGURE 19. NON-SYNCHRONOUS BUCK, FORCE PWM MODE, VIN 12V, NO LOAD VOUT BUCK 100mV/DIV (5V OFFSET) FIGURE 20. NON-SYNCHRONOUS BUCK, FORCE PWM MODE, VIN 12V, 2A VOUT BUCK 100mV/DIV (5V OFFSET) VIN_BOOST_INPUT 5V/DIV VIN_BOOST_INPUT 5V/DIV PHASE_BOOST 10V/DIV PHASE_BUCK 10V/DIV PHASE_BOOST 10V/DIV PHASE_BUCK 10V/DIV 20ms/DIV FIGURE 21. BOOST BUCK MODE, BOOST INPUT STEP FROM 36V TO 3V, VOUT BUCK = 5V, IOUT_BUCK = 1A 11 10ms/DIV FIGURE 22. BOOST BUCK MODE, BOOST INPUT STEP FROM 3V TO 36V, VOUT BUCK = 5V, IOUT_BUCK = 1A FN7640.0 September 29, 2011 ISL85402 Performance Curves (Continued) VOUT 5V/DIV IL_BOOST 2A/DIV PHASE_BOOST 20V/DIV PHASE_BUCK 20V/DIV 10ms/DIV FIGURE 23. BOOST BUCK MODE, VO = 9V, IO= 1.8A, BOOST INPUT DROPS FROM 16V TO 9V DC Functional Description PWM Control Initialization Pulling the MODE pin to GND will set the IC in forced PWM mode. The ISL85402 employ the peak current mode PWM control for fast transient response and cycle-by-cycle current limiting. See “Block Diagram” on page 4. Initially the ISL85402 continually monitors the voltage at EN pin. When the voltage on EN pin exceeds its rising ON threshold, the internal LDO will start up to build up VCC. After Power-On Reset (POR) circuits detect that VCC voltage has exceeded the POR threshold, the soft-start will be initiated. Soft-Start The soft-start (SS) ramp is built up in the external capacitor on the SS pin that is charged by an internal 5µA current source. C SS [ μF ] = 6.5 ⋅ t SS [ S ] (EQ. 1) The SS ramp starts from 0 to voltage above 0.8V. Once SS reaches 0.8V, the bandgap reference takes over and IC gets into steady state operation. The SS plays a vital role in the hiccup mode of operation. The IC works as cycle-by-cycle peak current limiting at over load condition. When a harsh con dit on occurs and the current in upper side MOSFET reach the second overcurrent threshold, the SS pin is pulled to ground and a dummy soft-start cycle is initiated. At dummy SS cycle, the current to charge soft-start cap is cut down to 1/5 of its normal value. So a dummy SS cycle takes 5x of the regular SS cycle. During the dummy SS period, the control loop is disabled and no PWM output. At the end of this cycle, it will start the normal SS. The hiccup mode persist until the second overcurrent threshold is no longer reached. The ISL85402 is capable of starting up with prebiased output. The PWM operation is initialized by the clock from the oscillator. The upper MOSFET is turned on by the clock at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current sense signal and the slope compensation signal reaches the error amplifier output voltage level, the PWM comparator is trigger to shut down the PWM logic to turn off the high-side MOSFET. The high-side MOSFET stays off until the next clock signal comes for next cycle. The output voltage is sensed by a resistor divider from VOUT to FB pin. The difference between FB voltage and 0.8V reference is amplified and compensated to generate the error voltage signal at COMP pin. Then the COMP pin signal is compared with the current ramp signal to shut down the PWM. PFM Mode Operation To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating will set the IC to have PFM (Pulse Frequency Modulation) operation in light load. In PFM mode, the switching frequency is dramatically reduced to minimize the switching loss. The ISL85402 enters PFM mode when the MOSFET peak current is lower than the PWM/PFM boundary current threshold. This threshold is 700mA as default when there is no programming resistor at MODE pin. The current threshold for PWM/PFM boundary can be programmed by choosing the MODE pin resistor value calculated from Equation 2, where IPFM is the desired PWM/PFM boundary current threshold and RMODE is the programming resistor. 118500 R MODE = ---------------------------------------IPFM + 0.2 12 (EQ. 2) FN7640.0 September 29, 2011 ISL85402 output current. The output current should be derated under any conditions causing the die temperature exceeding +125°C. 500 RMODE (kΩ) 400 300 200 100 0 0.0 0.2 0.4 0.6 0.8 IPFM (A) 1.0 1.2 1.4 FIGURE 24. RMODE vs IPFM Synchronous and Non-Synchronous Buck The ISL85402 supports both Synchronous and non-synchronous buck operations. For a non-synchronous buck operation when a power diode is used as the low-side power device, the LGATE driver can be disabled with LGATE connected to VCC (before IC start-up). Input Voltage With the part switching, the operating ISL85402 input voltage must be under 36V. This recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to part switching while not exceeding the 44V as Absolute Maximum Ratings. Output Voltage The ISL85402 output voltage can be programmed down to 0.8V by a resistor divider from VOUT to FB. The maximum achievable voltage is (VIN*DMAX - VDROP), where VDROP is the voltage drop in the power path including mainly the MOSFET rDS(ON) and inductor DCR. The maximum duty cycle DMAX is decided by (1/Fs - tMIN(OFF)). Output Current With the high-side MOSFET integrated, the maximum output current, which the ISL85402 can support is decided by the package and many operating conditions. Thus, including input voltage, output voltage, duty cycle, switching frequency and temperature, etc. Note the following points. • The maximum DC output current is 5A limited by the package. • From the thermal perspective, the die temperature shouldn’t exceed +125°C with the power loss dissipated inside of the IC. Figures 10 and 11 show the thermal performance of this part operating at different conditions. Figures 10 and 11 shows 2A and 2.5A applications under +25°C still air conditions over VIN range. The temperature rise data in these Figures can be used to estimate the die temperature at different ambient temperatures under various operating conditions. Note that more temperature rise is expected at higher ambient temperature due to more conduction loss caused by rDS(ON) increase. Generally, the part can output 2.5A in typical application condition VIN 8~30V, VO 5V, 500kHz, still air and +85°C ambient conditions. For any other operating conditions, refer to the previous mentioned thermal curves to estimate the maximum 13 Basically, the die temperature equals to the sum of ambient temperature and the temperature rise resulting from the power dissipated the IC package with a certain junction to ambient thermal impedance θJA. The power dissipated in the IC is related to the MOSFET switching loss, conduction loss and the internal LDO loss. Besides the load, these losses are also related to input voltage, output voltage, duty cycle, switching frequency and temperature. With exposed pad at bottom, the heat of the IC mainly goes through the bottom pad and θJA is greatly reduced. The θJA is highly related to layout and air flow conditions. In layout, multiple vias (≥9) are strongly recommended in the IC bottom pad. And the bottom pad with its vias should be placed in ground copper plane with area as large as possible multiple layers. The θJA can be reduced further with air flow. Refer to Figures 8 and 9 for the thermal performance with 100 CFM air flow. Boost Converter Operation “Typical Application Schematic III - Boost Buck Converter” on page 5, shows the circuits where the boost works as a pre-stage to provide input to the following Buck stage. This is for applications when the input voltage could drop to a very low voltage in some constants (in some battery powered systems as for example), causing the output voltage drops out of regulation. The boost converter can be enabled to boost the input voltage up to keep the output voltage in regulation. When system input voltage recovers back to normal, the boost stage is disabled while only the buck stage is switching. EXT_BOOST pin is used to set boost mode and monitor the boost input voltage. At IC start-up before soft-start, the controller will be latched in boost mode when the voltage is on above 200mV; it will latch in synchronous buck mode if voltage on this pin is below 200mV. In boost mode the low-side driver output PWM has the same PWM signal with the buck regulator. In boost mode, the EXT_BOOST pin is used to monitor boost output voltage to turn on and turn off the boost PWM. The AUXVCC pin is used to monitor the boost output voltage to turn on and turn off the boost PWM. Referring to Figure 25 on page 14, a resistor divider from boost input voltage to EXT_BOOST pin is used to detect the boost input voltage. When the voltage on EXT_BOOST pin is below 0.8V, the boost PWM is enabled with a fixed 500µs soft-start and the boost duty cycle increase linearly from tMIN(ON)*Fs to ~50%, and a 3µA sinking current is enabled at EXT_BOOST pin for hysteresis purpose. When the voltage on the EXT_BOOST pin recovers to be above 0.8V, the boost PWM is disabled immediately. Use Equation 3 to calculate the upper resistor RUP (R1 in Figure 25) for a desired hysteresis VHYS at boost input voltage. VHYS R UP [ MΩ ] = ---------------------3 [ μA ] (EQ. 3) Use Equation 4 to calculate the lower resistor RLOW (R2 in Figure 25) according to a desired boost enable threshold. R UP ⋅ 0.8 R LOW = --------------------------------------VFTH – 0.8 (EQ. 4) FN7640.0 September 29, 2011 ISL85402 Where VFTH is the desired falling threshold on boost input voltage to turn on the boost, 3µA is the hysteresis current, and 0.8V is the reference voltage to be compared with. Note the boost start-up threshold has to be selected in a way that the buck is operating working well and kept in close loop regulation before boost start-up. Otherwise, large in-rush current at boost start-up could occur at boost input due to the buck open loop saturation. Similarly, a resistor divider from boost output voltage to AUXVCC pin is used to detect the boost output voltage. When the voltage on AUXVCC pin is below 0.8V, the boost PWM is enabled with a fixed 500µs soft-start, and a 3µA sinking current is enabled at AUXVCC pin for hysteresis purposes. When the voltage on the AUXVCC pin recovers to be above 0.8V, the boost PWM is disabled immediately. Use Equation 3 to calculate the upper resistor RUP (R3 in Figure 25) according to a desired hysteresis VHY at boost output voltage. Use Equation 4 to calculate the lower resistor RLOW (R4 in Figure 25) according to a desired boost enable threshold at boost output. Assuming VBAT is the boost input voltage, VOUTBST is the boost output voltage and VOUT is the buck output voltage, the steady state transfer function are: 1 V OUTBST = ------------------ ⋅ V BAT 1–D (EQ. 5) D V OUT = D ⋅ V OUTBST = ------------------ ⋅ V BAT 1–D (EQ. 6) the boost output voltage that is 5.2V (Equation 7), meaning the VIN pin (buck input) still sees 5.2V to keep the IC working. Note in the previous mentioned case, the boost input current could be high because the input voltage is very low (VIN*IIN = VOUT*IOUT*Efficiency). If the design is to achieve the low input operation with full load, the inductor and MOSFET have to be selected to be with enough current ratings to handle the high current appearing at boost input. The boost inductor current are the same with the boost input current, which can be estimated as Equation 8, where POUT is the output power, VBAT is the boost input voltage, EFF is the estimated efficiency of the whole boost and buck stages. P OUT IL IN = ------------------------------------V BAT ⋅ EFF (EQ. 8) Based on the same concerns of boost input current, the IC should be disabled before the boost input voltage rise above a certain level. PFM is not available in boost mode. Oscillator and Synchronization The oscillator has a default frequency of 500kHz with FS pin connected to VCC, or ground, or floating. The frequency can be programmed to any frequency between 200kHz and 2.2MHz with a resistor from FS pin to GND. 145000 – 16 ⋅ FS [ kHz ] R FS [ kΩ ] = -----------------------------------------------------------------------------------FS [ kHz ] (EQ. 9) From Equations 5 and 6, Equation 7 can be derived to estimate the steady state boost output voltage as function of VBAT and VOUT: (EQ. 7) V OUTBST = V BAT + V OUT After the IC starts up, the boost buck converters can keep working when the battery voltage drops extremely low because the IC’s bias (VCC) LDO is powered by the boost output. For example, a 3.3V output application, battery drops to 2V, VIN pin voltage is powered by BATTERY VOUT_BST + + R1 EXT_BOOST 0.8V R2 I_HYS = 3µA R3 LOGIC LGATE AUXVCC R4 0.8V PWM LGATE DRIVE I_HYS = 3µA FIGURE 25. BOOST CONVERTER CONTROL 14 FN7640.0 September 29, 2011 1200 370 1000 320 800 270 RLIM (kΩ) RFS (kΩ) ISL85402 600 220 400 170 200 120 0 0 500 1000 1500 FS (kHz) 2000 2500 With an external square pulse waveform (with frequency 10% higher than the local frequency, 10% to 90% duty cycle and pulse width higher than 150ns) on SYNC pin. Thus, the ISL85402 will synchronize its switching frequency to the fundamental frequency of the input waveform. The internal oscillator synchronizes with the leading edge of the input signal. The rising edge of UGATE PWM is delayed by 180° from the leading edge of the external clock signal. Fault Protection 2.0 3.0 IOC1 (A) 4.0 5.0 6.0 Overvoltage Protection If the voltage detected on the FB pin is over 110% of reference, the high-side and low-side driver shuts down immediately and won’t be allowed on until FB voltage drops to 0.8V. When the FB voltage drops to 0.8V, the drivers are released to ON. If the 120% overvoltage threshold is reached, the high-side and low-side driver shuts down immediately and the IC is latched off. The IC has to be reset for restart. Thermal Protection The ISL85402 PWM will be disabled if the junction temperature reaches +155°C. A +15°C hysteresis insures that the device will not restart until the junction temperature drops below +140°C. Overcurrent Protection The overcurrent function protects against any overload condition and output short at worst case, by monitoring the current flowing through the upper MOSFET. There are 2 current limiting thresholds. The first one IOC1 is to limit the high-side MOSFET peak current cycle-by-cycle. The current limit threshold is set to default at 3.6A with ILIMIT pin connected to GND or VCC, or left open. The current limit threshold can also be programmed by a resistor RLIM at ILIMIT pin to ground. Use Equation 10 to calculate the resistor. (EQ. 10) Note that IOC1 is higher with lower RLIM. IOC1 reaches its maximum 5.4A with RLIM at 54.9k (TYP). With RLIM lower than 54.9k (TYP), the OC limit goes to its default value of 3.6A (TYP). The second current protection threshold IOC2 is 15% higher than IOC1 mentioned previously. Upon instant when the high-side MOSFET current reaches IOC2, the PWM is shut off after 2-cycle delay and the IC enters hiccup mode. In hiccup mode, the PWM is disabled for dummy soft-start duration equaling to 5 regular soft-start periods. After this dummy soft-start cycle, the true soft-start cycle is attempted again. The IOC2 offers a robust and reliable protections against the worst case conditions. The frequency foldback is implemented for the ISL85402. When overcurrent limiting, the switching frequency is reduced to be proportional to output voltage in order to keep the inductor current under limit threshold during overload condition. The low limit of frequency under frequency foldback operation is 40kHz. 15 1.0 FIGURE 27. RLIM vs IOC1 FIGURE 26. RFS vs FREQUENCY With the SYNC pins simply connected together, multiple ISL85402s can be synchronized. The slave ICs automatically have 180° phase shift with respective to the master IC. 300000 R LIM = -----------------------------------------------------I OC [ A ] + 0.018 70 0.0 Component Selections Output Capacitors Output capacitors are required to filter the inductor current and supply the load transient current. All ceramic output capacitors are achievable with this IC. Also in some applications, the aluminum electrolytic type capacitors are added to the output to provide better load transient and longer holdup time for the load. When low cost, high ESR aluminum capacitor is used at output, a ceramic capacitor (2.2µF to 10µF) is recommended to handle the ripple current and reduce the total equivalent ESR effectively. Input Capacitors Depending on the system input power rail conditions, the aluminum electrolytic type capacitor is normally needed to provide the stable input voltage. Thus, restrict the switching frequency pulse current in small area over the input traces for better EMC performance. The input capacitor should be able to handle the RMS current from the switching power devices. Ceramic capacitors must be used at VIN pin of the IC and multiple capacitors including 1µF and 0.1µF are recommended. Place these capacitors as closely as possible to the IC. FN7640.0 ISL85402 Buck Output Inductor Boost Output Capacitor Generally the inductor should filter the current ripple to be 30~50% of the regulator’s maximum average output current. The low DCR inductor should be selected for the highest efficiency and the inductor saturation current rating should be higher than the highest transient expected. Based on the same theory in boost start-up described previously in boost inductor selection, a large capacitor at boost output will cause high in-rush current at boost PWM start-up. 22µF is a good choice for applications with buck output voltage less than 10V. Also some minimum amount of capacitance has to be used in boost output to keep the system stable. Low-Side Power MOSFET In Synchronous buck application, a power N-MOSFET is needed as the synchronous low-side MOSFET and it must have low rDS(ON), low Rg (Rg_typ < 1.5Ω recommended), Vgth (Vgth_min ≥ 1.2V) and Qgd. A good example is BSZ100N06LS3G. Output Voltage Feedback Resistor Divider The output voltage can be programmed down to 0.8V by a resistor divider from VOUT to FB according to Equation 11. R UP ⎞ ⎛ V OUT = 0.8 ⋅ ⎜ 1 + --------------------⎟ R LOW⎠ ⎝ (EQ. 11) In an application requiring least input quiescent current, large resistors should be used for the divider. 232k is recommended for the upper resistor. Layout Suggestions 1. Put the input ceramic capacitors at the closest place to the IC VIN pin and power ground connecting to power MOSFET or Diode. Keep this loop (input ceramic capacitor, IC VIN pin and MOSFET/Diode) as tiny as possible to achieve the least voltage spikes induced by the trace parasitic inductance. 2. Put the input aluminum capacitors close to IC VIN pin. 3. Keep the phase node copper area small but large enough to handle the load current. 4. Put the output ceramic and aluminum capacitors also close to the power stage components. Compensation Network 5. Put vias (≥9) in the bottom pad of the IC. The bottom pad should be placed in ground copper plane with area as large as possible in multiple layers to effectively reduce the thermal impedance. With peak current mode control, Type II compensation is normally used for most of the applications. But in applications to achieve higher bandwidth, Type III is better. 6. Put the 4.7µF ceramic decoupling capacitor at VCC pin the closest place to the IC. And put multiple vias (≥3) right close to the ground pad of this capacitor. Note that in an application where PFM mode is desired and type III compensation network is used, the value of the capacitor between COMP pin and FB pin (not the capacitor in series with the resistor between COMP and FB) should be minimal to reduce the noise coupling for proper PFM operations. 10pF is recommended for this capacitor between COMP and FB at PFM applications. Thus, a capacitor (<1nF) at FB pin to ground helps the proper PFM mode operation. 7. Keep the bootstrap capacitor close to the IC. 8. Keep the LGATE drive trace as short as possible and try to avoid use via in LGATE drive path to achieve the lowest impedance. 9. Put the positive voltage sense trace close to the place to be strictly regulated. 10. Put all the peripheral control components close to the IC. Boost Inductor Besides the need to sustain the current ripple to be within a certain range (30% to 50%), the boost inductor current at its soft-start is a more important perspective to be considered in selection of the boost inductor. Each time the boost starts up, there is a fixed 500µs soft-start time when the duty cycle increases linearly from tMIN(ON)*Fs to ~50%. Before and after boost start-up, the boost output voltage will jump from VIN_BOOST to voltage (VIN_BOOST + VOUT_BUCK). The design target in boost soft-start is to ensure the boost input current is sustained to minimum but capable to charge the boost output voltage to have a voltage step equaling to VOUT_BUCK. A big inductor will block the inductor current to increase and not high enough to be able to charge the output capacitor to the final steady state value (VIN_BOOST + VOUT_BUCK) within 500µs. A 6.8µH inductor is a good starting point for its selection in design. The boost inductor current at start-up must be checked by oscilloscope to ensure it is under acceptable range. 16 FIGURE 28. PCB VIA PATTERN FN7640.0 ISL85402 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 9/29/2011 FN7640.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL85402 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. 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For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7640.0 ISL85402 Package Outline Drawing L20.4x4C 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/06 4X 4.00 2.0 16X 0.50 A B 16 6 PIN #1 INDEX AREA 20 6 PIN 1 INDEX AREA 1 4.00 15 2 .70 ± 0 . 15 11 (4X) 5 0.15 6 10 0.10 M C A B 4 20X 0.25 +0.05 / -0.07 20X 0.4 ± 0.10 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0 . 1 C BASE PLANE ( 3. 8 TYP ) ( SEATING PLANE 0.08 C 2. 70 ) ( 20X 0 . 5 ) SIDE VIEW ( 20X 0 . 25 ) C 0 . 2 REF 5 ( 20X 0 . 6) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 18 FN7640.0