CD4031BMS CMOS 64-Stage Static Shift Register December 1992 Features Description • High Voltage Type (20V Rating) The CD4031BMS is a static shift register that contains 64 Dtype, master-slave flip-flop stages and one stage which is a D-type master flip-flop only (referred to as a 1/2 stage). • Fully Static Operation: DC to 12MHz (typ.) at VDD VSS = 15V • Standard TTL Drive Capability on Q Output • Recirculation Capability • Three Cascading Modes: - Direct Clocking for High-Speed Operation - Delayed Clocking for Reduced Clock Drive Requirements - Additional 1/2 Stage for Slow Clocks • 100% Tested For Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; - 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications The logic level present at the DATA input is transferred into the first stage and shifted one stage at each positive-going clock transition. Maximum clock frequencies up to 12MHz (typical) can be obtained. Because fully static operation is allowed, information can be permanently stored with the clock line in either the low or high state. The CD4031BMS has a MODE CONTROL input that, when in the high state, allows operation in the recirculating mode. The MODE CONTROL input can also be used to select between two separate data sources. Register packages can be cascaded and the clock lines driven directly for high-speed operation. Alternatively, a delayed clock output (CLD) is provided that enables cascading register packages while allowing reduced clock drive fan-out and transition-time requirements. A third cascading option makes use of the Q’ output from the 1/2 stage, which is available on the next negative-going transition of the clock after the Q output occurs. This delayed output, like the delayed clock CLD, is used with clocks having slow rise and fall times. The CD4031BMS is supplied in these 16 lead outline packages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W • Serial Shift Registers • Time Delay Circuits Functional Diagram Pinout CD4031BMS TOP VIEW RECIRCULATE DATA IN 2 1 CLOCK INHIBIT 2 DATA 1 15 IN 16 VDD 15 DATA IN 1 NC 3 14 NC NC 4 13 NC Q’ 5 12 NC Q 6 11 NC Q 7 10 MODE CONTROL VSS 8 MODE 10 CONT. RECIRC DATA 2 IN 1 CLOCK IN 2 CONTROL LOGIC DATA OUT 6 DATA OUT 7 CL CLOCK LOGIC 9 DELAYED CLOCK OUT 9 CLD 64 STAGES CL 1/2 STAGE Q’ 5 VDD = 16 VSS = 8 NC = 3, 4, 11, 12, 13, 14 NC = NO CONNECTION CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-816 File Number 3306 Specifications CD4031BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125 C - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current Q, Q’, CLD IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC - V 0.51 - mA 1.3 - mA IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.4 - mA Output Current Q IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 2.04 - mA Output Current Q IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 5.2 - mA Output Current Q IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 13.6 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.51 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.6 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.3 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.4 mA -2.8 -0.7 V 0.7 2.8 V N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B Functional F Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 7-817 V -55oC +25oC, NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. VOH > VOL < VDD/2 VDD/2 +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V 1, 2, 3 +25oC, +125oC, -55oC - 4 V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4031BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Q SYMBOL TPHL1 TPLH1 Propagation Delay Clock to Q TPLH2 Propagation Delay Clock to Q TPHL2 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TPLH3 TPHL3 VDD = 5V, VIN = VDD or GND Propagation Delay Clock to CLD TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency (See Note 5; Table 3) 9 10, 11 Propagation Delay Clock to Q’ Transition Time GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 500 ns - 675 ns - 500 ns - 675 ns - 380 ns - 513 ns - 380 ns - 513 ns - 200 ns - 270 ns - 200 ns - 270 ns 9 +25oC 2 - MHz 10, 11 +125oC, -55oC 1.48 - MHz NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 -55 C, +25 C - 10 µA +125oC - 300 µA o o - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) Q, Q’, CLD Outputs IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Q, Q’, CLD Outputs IOL10 +125oC 0.9 - mA -55oC 1.6 - mA Output Current (Sink) Q, Q’, CLD Outputs IOL15 +125oC 2.4 - mA -55oC 4.2 - mA Output Current (Sink) Q Outputs IOL5 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 0.4V 1, 2 7-818 +125oC 1.44 - mA -55oC 2.56 - mA Specifications CD4031BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Output Current (Sink) Q Outputs IOL10 Output Current (Sink) Q Outputs IOL15 Output Current (Source) Output Current (Source) CONDITIONS VDD = 10V, VOUT = 0.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC 3.6 - mA -55 C 6.4 - mA +125oC 9.6 - mA 16.8 - mA o VDD = 15V, VOUT = 1.5V 1, 2 -55 IOH5A IOH5B VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 oC +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA - -2.0 mA - -0.9 mA - -1.6 mA - -2.4 mA - -4.2 mA - 3 V -55o Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 -55 Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 C +125oC oC +125oC o -55 C Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25o Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V Propagation Delay Clock to Q TPHL1 TPLH1 1, 2, 3 +25oC - 220 ns VDD = 15V 1, 2, 3 +25 oC - 180 ns Propagation Delay Clock to Q TPLH2 VDD = 10V 1, 2, 3 +25oC - 220 ns 1, 2, 3 o +25 C - 180 ns VDD = 10V 1, 2, 3 +25 oC - 160 ns VDD = 15V 1, 2, 3 +25oC - 130 ns 1, 2, 3 +25 oC - 100 ns Propagation Delay Clock to Q VDD = 10V VDD = 15V TPHL2 o C, +125 C, -55oC Propagation Delay Clock to CLD TPLH3 TPHL3 VDD = 10V VDD = 15V 1, 2, 3 +25oC - 80 ns Propagation Delay Clock to Q’ TPLH4 TPHL4 VDD = 10V 1, 2, 3 +25oC - 160 ns VDD = 15V 1, 2, 3 +25oC - 130 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC - 5 MHz VDD = 15V 1, 2, 3 +25oC - 6 MHz VDD = 5V 1, 2, 3 +25oC - 1000 µs VDD = 10V 1, 2, 3 +25oC - 1000 µs VDD = 15V 1, 2, 3 +25oC - 200 µs 1, 2, 3 +25oC - 60 ns VDD = 10V 1, 2, 3 +25oC - 30 ns VDD = 15V 1, 2, 3 +25oC - 20 ns 1, 2, 3 +25oC - 60 ns VDD = 10V 1, 2, 3 +25oC - 30 ns VDD = 15V 1, 2, 3 +25oC - 20 ns 1, 2, 3 +25oC - 240 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns 1, 2 +25oC - 7.5 pF Transition Time Maximum Clock Input Frequency (Note 5) Clock Input Rise or Fall Time (Note 4) Minimum Data Setup Time Minimum Data Hold Time Minimum Clock Pulse Width Input Capacitance TTHL TTLH FCL TRCL TFCL TS TH TW CIN VDD = 10V VDD = 5V VDD = 5V VDD = 5V Any Input 7-819 Specifications CD4031BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded in the parallel clocked application, TRCL should be made ≤ the sum of the propagation delay at 50pF and the transition time of the output driving stage. 5. Maximum clock frequency for cascaded units; a) Using Delayed Clock feature in recirculation mode: 1 FMAX = -------------------------------------------------------------------------------------------------------------------------------------- where n = number of packages ( n-1 ) CL, prop delay and Q prop delay and set – up time b) Not using Delayed Clock: 1 FMAX = ---------------------------------------------------------------------------propagation delay and set – up time TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns N Threshold Voltage VNTH N Threshold Voltage Delta ∆VNTH P Threshold Voltage VPTH P Threshold Voltage Delta ∆VPTH Functional VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V (Worst Case) NOTES: 1. All voltages referenced to device GND. 2. VDD = 5V, CL = 50pF, RL = 200K 3. See Table 2 for +25oC limit. TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading 7-820 Specifications CD4031BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Output Current (Source) SYMBOL DELTA LIMIT ± 20% x Pre-Test Reading IOH5A TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 3 - 7, 9, 11 - 14 1, 2, 8, 10, 15 16 Static Burn-In 2 Note 1 3 - 7, 9, 11 - 14 8 1, 2, 10, 15, 16 Dynamic BurnIn Note 1 3 - 5, 11 - 14 8, 15 1, 16 3 - 7, 9, 11 - 14 8 1, 2, 10, 15, 16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 6, 7, 9 2 10 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-821 CD4031BMS Logic Diagram CL CL 15 p p DATA 1 IN n n * * CL CL CL 10 CL p MODE CONTROL p n * 1 CL RECIRCULATE (DATA 2 IN) CL CL p p n * 2 CL CL n CL CL CL CL CLOCK 9 n 63 IDENTICAL STAGES CLD CL p p n n CL CL CL p VDD 7 6 Q Q n CL *ALL INPUTS ARE PROTECTED BY CMOS/MOS PROTECTION NETWORK CL p n 5 INPUT CONTROL CIRCUIT TRUTH TABLE TYPICAL STAGE TRUTH TABLE DATA RECIR MODE BIT INTO STAGE 1 1 X 0 1 0 X X X 1 0 1 = High Level X = Don’t Care 0 1 1 DATA CL TRUTH TABLE FOR OUTPUT FROM Q’ (TERMINAL 5) DATA + 1 DATA + 64 0 0 1 1 X NC 0 1 0 Q’ CL VSS 1 = High Level X = Don’t Care 0 = Low Level NC = No Change CL DATA + 64 1/2 0 0 1 1 X NC 1 = High Level X = Don’t Care 0 = Low Level NC = No Change 0 = Low Level NC = No Change All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 822 CD4031BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 1 . TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS (Q SINK CURRENT = 4X ORDINATE) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -5 -10 -15 -10V -20 -25 -15V AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS (Q SINK CURRENT = 4X ORDINATE) 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) (SEE TABLE) -15 PROPAGATION DELAY TIME (tPHL, tPLH) (ns) (SEE TABLE) -30 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC tPHL, tPLN - CLOCK TO Q tPLH - CLOCK TO Q 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 20 60 80 40 LOAD CAPACITANCE (CL) (pF) 100 FIGURE 5. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (SEE TABLE) AMBIENT TEMPERATURE (TA) = +25oC tPHL, tPLN - CLOCK TO Q tPLH - CLOCK TO Q 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 20 60 80 40 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (SEE TABLE) 7-823 100 CD4031BMS Typical Performance Characteristics (Continued) AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL) (ns) TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 75 SUPPLY VOLTAGE (VDD) = 5V 50 10V 25 15V 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 0 POWER DISSIPATION PER (PD) (µW) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE (EXCEPT Q, tTHL) 20 40 60 80 LOAD CAPACITANCE (CL) (pF) 100 FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE (Q, tTHL) 8 6 4 2 SUPPLY VOLTAGE (VDD) = 15V 10K 8 6 4 2 10V 1K 8 6 4 100 10V 5V 2 CL = 50pF 8 6 4 CL = 15pF AMBIENT TEMPERATURE (TA) = +25oC 2 10 2 4 68 2 4 6 8 2 2 4 6 8 4 6 8 10 100 1K CLOCK INPUT FREQUENCY (fCL) (kHz) 10K FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY VDD DATA 6 15 Q D 6 15 Q D 6 15 Q D 6 15 MODE CONTROL RECIRC IN 10 CD4031BMS 10 CD4031BMS 10 CD4031BMS 10 CD4031BMS 1 1 1 1 2 CL 2 CL 2 CL CLOCK DRIVER MODE CONTROL VDD = RECIRCULATION GND = NEW DATA FIGURE 10. CASCADING USING DIRECT CLOCKING FOR HIGH-SPEED OPERATION (SEE CLOCK RISE AND FALL TIME REQUIREMENT) 7-824 2 CL Q CD4031BMS VDD DATA 6 15 Q D 6 15 Q D 6 15 Q D 6 15 Q MODE CONTROL 10 CD4031BMS 10 CD4031BMS 10 CD4031BMS 10 CD4031BMS 1 1 1 1 9 RECIRC IN 2 CLD 9 CL 2 CLD 9 CL 2 CLD 9 CL 2 CLD CL CLOCK DRIVER (1/2 - CD4013B) DELAYED CLOCK TO CLOCK NEW DATA INTO FIRST REGISTER D Q *FOR RECIRCULATION MODE ONLY FF* FF TO DELAY DATA UNTIL FISRT REGISTERED DELAYED CLOCKING HAS OCCURED CL MODE CONTROL VDD = RECIRCULATION GND = NEW DATA FIGURE 11. CASCADING USING DELAYED CLOCKING FOR REDUCED CLOCK DRIVE REQUIREMENTS VDD DATA 5 15 Q’ D 5 15 Q’ D 5 15 Q’ D 5 15 Q’ MODE CONTROL RECIRC IN 10 CD4031BMS 10 CD4031BMS 10 CD4031BMS 10 CD4031BMS 1 1 1 1 2 CL 2 CL 2 6 2 CL CL CLOCK DRIVER MODE CONTROL VDD = RECIRCULATION GND = NEW DATA FIGURE 12. CASCADING USING HALF-CLOCK-PULSE DELAYED OUTPUT (Q’) TO PERMIT USE OF SLOW RISE AND FALL CLOCK INPUTS Chip Dimensions and Pad Layout METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) 7-825