IRFI9Z14G, SiHFI9Z14G Datasheet

IRFI9Z14G, SiHFI9Z14G
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Isolated Package
• High Voltage Isolation = 2.5 kVRMS (t = 60 s;
f = 60 Hz)
• Sink to Lead Creepage Distance = 4.8 mm
• P-Channel
• 175 °C Operating Temperature
• Dynamic dV/dt Rating
• Low Thermal Resistance
• Lead (Pb)-free Available
- 60
RDS(on) (Ω)
VGS = - 10 V
0.50
Qg (Max.) (nC)
12
Qgs (nC)
3.8
Qgd (nC)
5.1
Configuration
Single
S
Available
RoHS*
COMPLIANT
DESCRIPTION
TO-220 FULLPAK
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-220 FULLPAK eliminates the need for additional
insulating hardware in commercial-industrial applications.
The molding compound used provides a high isolation
capability and a low thermal resistance between the tab and
external heatsink. This isolation is equivalent to using a 100
micron mica barrier with standard TO-220 product. The
FULLPAK is mounted to a heatsink using a single clip or by
a single screw fixing.
G
D
P-Channel MOSFET
G D S
ORDERING INFORMATION
Package
TO-220 FULLPAK
IRFI9Z14GPbF
SiHFI9Z14G-E3
IRFI9Z14G
SiHFI9Z14G
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
VGS at - 10 V
TC = 25 °C
TC = 100 °C
Currenta
Pulsed Drain
Linear Derating Factor
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
SYMBOL
LIMIT
VDS
VGS
- 60
± 20
- 5.3
- 3.8
- 21
0.18
120
- 5.3
2.7
27
- 4.5
- 55 to + 175
300d
10
1.1
ID
IDM
TC = 25 °C
for 10 s
6-32 or M3 screw
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a.
b.
c.
d.
Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
VDD = - 25 V, starting TJ = 25 °C, L = 5.0 mH, RG = 25 Ω, IAS = - 5.3 A (see fig. 12).
ISD ≤ - 6.7 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 175 °C.
1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91170
S09-0062-Rev. A, 02-Feb-09
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1
IRFI9Z14G, SiHFI9Z14G
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
5.5
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = - 250 µA
- 60
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = - 1 mA
-
- 0.060
-
V/°C
VGS(th)
VDS = VGS, ID = - 250 µA
- 2.0
-
- 4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = - 60 V, VGS = 0 V
-
-
- 100
VDS = - 48 VGS = 0 V, TJ = 150 °C
-
-
- 500
-
-
0.50
Ω
1.6
-
-
S
-
270
-
-
170
-
-
31
-
-
12
-
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = - 3.2 Ab
VGS = - 10 V
VDS = - 25 V, ID = - 3.2
Ab
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Drain to Sink Capacitance
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
C
Total Gate Charge
Qg
Gate-Source Charge
Qgs
f = 1.0 MHz
VGS = - 10 V
ID = - 6.7 A, VDS = - 48 V,
see fig. 6 and 13b
-
-
12
-
-
3.8
Gate-Drain Charge
Qgd
-
-
5.1
Turn-On Delay Time
td(on)
-
11
-
-
63
-
-
9.6
-
-
31
-
-
4.5
-
-
7.5
-
-
-
- 5.3
-
-
- 21
-
-
- 5 .5
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = - 30 V, ID = - 6.7 A,
RG = 24 Ω, RD= 4.0 Ω,
see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
pF
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = - 5.3 A, VGS = 0 Vb
TJ = 25 °C, IF = - 6.7 A, dI/dt = 100 A/µsb
V
-
80
160
ns
-
0.096
0.19
µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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Document Number: 91170
S09-0062-Rev. A, 02-Feb-09
IRFI9Z14G, SiHFI9Z14G
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC= 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC= 175 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91170
S09-0062-Rev. A, 02-Feb-09
www.vishay.com
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IRFI9Z14G, SiHFI9Z14G
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91170
S09-0062-Rev. A, 02-Feb-09
IRFI9Z14G, SiHFI9Z14G
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+VDD
- 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
td(on)
td(off) tf
tr
VGS
10 %
90 %
VDS
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
IAS
VDS
D.U.T.
RG
VDS
+ V DD
VDD
IAS
tp
- 10 V
tp
0.01 Ω
VDS
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91170
S09-0062-Rev. A, 02-Feb-09
Fig. 12b - Unclamped Inductive Waveforms
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IRFI9Z14G, SiHFI9Z14G
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91170
S09-0062-Rev. A, 02-Feb-09
IRFI9Z14G, SiHFI9Z14G
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
+
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
+
- VDD
Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
*
ISD
VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91170.
Document Number: 91170
S09-0062-Rev. A, 02-Feb-09
www.vishay.com
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Revision: 02-Oct-12
1
Document Number: 91000