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NTERSIL o
-888-ISheet
1Data
July 8, 2010
3-Bit VID Single-Phase Voltage Regulator
with Current Monitor for GPU Core Power
The ISL6263D IC is a Single-Phase Synchronous Buck PWM
voltage regulator for GPU core power applications. It features
Intersil’s Robust Ripple Regulator (R3) Technology™.
Integrated current monitor, differential remote sense amplifier,
MOSFET driver and bootstrap diode result in smaller
implementation area and lower component cost.
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency PWM and hysteretic PWM, delivering
excellent light-load efficiency and superior load transient
response by commanding variable switching frequency
during the transitory event. For maximum conversion
efficiency, the ISL6263D automatically enters Diode
Emulation Mode (DEM) when the inductor current attempts
to flow negative. DEM is highly configurable and easy to
set-up. A PWM filter can be enabled, which prevents the
switching frequency from entering the audible spectrum as a
result of extremely light load while in DEM.
The GPU core voltage can be dynamically programmed from
0.7V to 1.0875V by the three VID input pins without requiring
sequential stepping of the VID states. The ISL6263D
requires only one capacitor for both the soft-start slew-rate
and the dynamic VID slew-rate by internally connecting the
SOFT pin to the appropriate current source. The voltage
Kelvin sensing is accomplished with an integrated unity-gain
true differential amplifier.
Ordering Information
• Real-Time GPU Current Monitor Output
• Applications up to 25A
• Input Voltage Range: +5.0V to +25.0V
• Programmable PWM Frequency: 200kHz to 500kHz
• Pre-biased Output Start-Up Capability
• 3-bit Voltage Identification (VID)
• Two Voltage Offset Pins
• 0.7V to 1.0875V Output Voltage Range
• Configurable PWM Modes
- Forced Continuous Conduction Mode
- Automatic Entry and Exit of Diode Emulation Mode
- Selectable Audible Frequency PWM Filter
• Integrated MOSFET Drivers and Bootstrap Diode
• Choice of Current Sensing Schemes
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Overvoltage, Undervoltage and Overcurrent Protection
• Pb-Free (RoHS compliant)
1
IMON
VID2
VID1
VID0
29
28
27
26
25
24 OFFSET1
SOFT
2
23 OFFSET0
OCSET
3
22 PVCC
VW
4
THERMAL PAD
21 LGATE
COMP
5
(BOTTOM)
20 PGND
FB
6
19 PHASE
VDIFF
7
18 UGATE
VSEN
8
17 BOOT
9
10
11
12
13
14
15
16
VDD
1
VSS
RBIAS
VIN
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL6263D. For more information on MSL please see
techbrief TB363.
30
ISP
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020.
31
VO
1. Please refer to TB347 for details on reel specifications.
32
ISN
NOTES:
VR_ON
ISL6263DHRZ-T ISL6263 DHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5
(Note 1)
AF_EN
ISL6263 DHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5
PGOOD
PKG.
DWG. #
ICOMP
PACKAGE
(Pb-Free)
ISL6263D
(32 LD 5x5 QFN)
TOP VIEW
FDE
ISL6263DHRZ
PART
MARKING
• Precision Single-Phase Core Voltage Regulator
- 0.5% System Accuracy 0°C to +100°C
- Differential Remote GPU Die Voltage Sensing
RTN
PART NUMBER
(Notes 2, 3)
FN6753.1
Features
Pinout
TEMP
RANGE
(°C)
ISL6263D
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC.
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas LLC
All other trademarks mentioned are the property of their respective owners.
Block Diagram
VR_ON
PGOOD
BOOT
VDD
VREF
1.55V
+
-
VREF
 
1:1
VSS
PWM
CONTROL
POR
2
x2.5
DIODE
EMULATION
PGOOD
-
SHORT CIRCUIT
SCP
AUDIBLE
FREQUENCY
FILTER
+
OVERCURRENT
RBIAS
OCSET
UNDERVOLTAGE
-
SEVERE
OVERVOLTAGE
SOFT
CROWBAR
CONTROL
OCP
ISP
+
ISN
-
OVERVOLTAGE
+
FAULT LATCH
+
VO
-
PHASE
SHOOT-THROUGH
PROTECTION
PVCC
LGATE
DRIVER
PGND
X31
FDE
VSEN
+
RTN
-
AF_EN
VW


VDIFF
 VW
20%

VID0
VID2
VID DAC
ISS




+
OFFSET1
E/A
-
OFFSET0
SOFT
VW
R3
MODULATOR
>
IDVID

VID1
>
REF
gmVIN
PWM
FB
COMP
IMON
VIN
FN6753.1
July 8, 2010
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF THE ISL6263D
gmVsoft V
COMP
ISL6263D
ICOMP
UGATE
DRIVER
ISL6263D
Simplified Application Circuit for DCR Current Sensing
RVDD
V5V
CPVCC
CVDD
VDD
PVCC
RRBIAS
RBIAS
VIN
VIN
CSOFT
QHS
SOFT
CIN
UGATE
BOOT
RIMON
PGOOD
LOUT
CBOOT
IMON
CIMON
VOUT
PHASE
COUT
QLS
VID<0:2>
OFFSET0
LGATE
OFFSET1
PGND
VR_ON
FDE
AF_EN
VOUT
VSEN
VGND
RTN
RS
RNTC
ISP
VW
ISL6263D
RFSET
RP
CN
CFSET
RNTCS
VO
CCOMP1
ROCSET
RCOMP
RIS1
OCSET
COMP
CCOMP2
ISN
FB
VDIFF
RDIFF2
RIS2
CDIFF
CIS
ICOMP
VSS
RGND
RDIFF1
0
FIGURE 2. ISL6263D GPU CORE VOLTAGE REGULATOR SOLUTION WITH DCR CURRENT SENSING
3
FN6753.1
July 8, 2010
ISL6263D
Simplified Application Circuit for Resistive Current Sensing
RVDD
V5V
CPVCC
CVDD
VDD
PVCC
RRBIAS
RBIAS
VIN
VIN
CSOFT
QHS
SOFT
CIN
UGATE
BOOT
RIMON
PGOOD
LOUT
CBOOT
IMON
CIMON
RSNS
VOUT
PHASE
VID<0:2>
COUT
QLS
OFFSET0
LGATE
OFFSET1
VR_ON
PGND
FDE
AF_EN
VOUT
VSEN
VGND
RTN
RS
VW
ISP
ISL6263D
RFSET
CN
CFSET
VO
CCOMP1
ROCSET
COMP
RCOMP
RIS1
OCSET
CCOMP2
ISN
FB
VDIFF
RDIFF2
RIS2
CDIFF
CIS
ICOMP
VSS
RDIFF1
RGND
0
FIGURE 3. ISL6263D GPU CORE VOLTAGE REGULATOR SOLUTION WITH RESISTIVE CURRENT SENSING
4
FN6753.1
July 8, 2010
ISL6263D
Absolute Voltage Ratings
Thermal Information
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
PHASE to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V
(<100ns Pulse Width, 10µJ) -5.0V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
BOOT to VSS or PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
UGATE. . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V
(<200ns Pulse Width, 20µJ) -4.0V
LGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V
(<100ns Pulse Width, 4µJ) -2.0V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . -0.3V to VSS, VDD +0.3V
Thermal Resistance (Typical, Notes 4, 5) JA (°C/W)
JC (°C/W)
32 Ld QFN Package. . . . . . . . . . . . . . .
35
6
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C
Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . -10°C to +100°C
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +25V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
FDE to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise stated. All typical specifications
TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range,
-10°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
VIN
VIN Input Resistance
R VIN
VIN Shutdown Current
IVIN_SHDN
VR_ON = 3.3V
1.0
VR_ON = 0V, VIN = 25V
MΩ
1.0
µA
3.3
mA
1.0
µA
4.50
V
VDD and PVCC
VDD Input Bias Current
IVDD
VDD Shutdown Current
IVDD_SHDN
VR_ON = 3.3V
2.7
VR_ON = 0V, VDD = 5.0V
VDD POR THRESHOLD
Rising VDD POR Threshold Voltage
V
Falling VDD POR Threshold Voltage
V
4.35
VDD_THR
3.85
4.10
V
VID<2:0> = 000, OFFSET<1:0> = 11
1087.5
mV
VID<2:0> = 111, OFFSET<1:0> = 00
700
mV
VID<2:0> = 000 to 111
50
mV/step
VDD_THF
REGULATION
V
Output Voltage Range
OUT_MAX
V
VID Voltage Step
OUT_MIN
VVID_STEP
OFFSET0 Voltage Offset
VOFT0
OFFSET0 switch between 0 and 1
12.5
mV
OFFSET1 Voltage Offset
VOFT1
OFFSET1 switch between 0 and 1
25
mV
System Accuracy
VOUT = 700mV to 1087.5mV
TA = 0°C to +100°C
-0.5
RFSET = 7kΩVCOMP = 2V
318
0.5
%
348
kHz
500
kHz
PWM
f
Nominal Frequency
SW
Frequency Range
333
200
f
Audio Filter Frequency
5
AF
28
kHz
FN6753.1
July 8, 2010
ISL6263D
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise stated. All typical specifications
TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range,
-10°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
AMPLIFIERS
Error Amplifier DC Gain (Note 7)
AV0
Error Amplifier Gain-Bandwidth Product
(Note 7)
CL = 20pF
18
MHz
SR
CL = 20pF
5
V/µs
IFB
VFB = 1050mV
10
FB Input Bias Current
Current Sense Amplifier Offset
-0.3
ISENSE_OFS
V
RBIAS Voltage
dB
GBW
Error Amp Slew Rate (Note 7)
V
90
RBIAS
R
RBIAS =150kΩ
150
nA
0.3
mV
1.50
1.52
1.54
V
-47
-42
-37
µA
SOFT-START CURRENT
Soft-Start Current
ISS
Soft Dynamic VID Current
IDVID
|SOFT - REF|>100mV
±180
±205
±230
µA
V
V
V
ICOMP - O = 40mV
1.22
1.24
1.26
V
V
V
ICOMP - O = 10mV
0.285
0.310
0.335
V
CURRENT MONITOR
Current Monitor Output Voltage Range
Current Monitor Maximum Output Voltage
V
IMON
IMONMAX
Current Monitor Maximum Current Sinking
Capability
3.1
3.4
VIMON/
VIMON/
VIMON/
V
250Ω
180Ω
130Ω
A
Current Monitor Sourcing Current
ISC_IMON
V
V
ICOMP - O = 40mV
2.0
mA
Current Monitor Sinking Current
ISK_IMON
V
V
ICOMP - O = 40mV
2.0
mA
IIMON ISK_IMON, IIMON ISC_IMON
Current Monitor Impedance (Note 7)
7
Ω
GATE DRIVER
UGATE Source Resistance (Note 7)
RUGSRC
500mA Source Current
1.0
UGATE Source Current (Note 7)
IUGSRC
VUGATE_PHASE = 2.5V
2.0
UGATE Sink Resistance (Note 7)
RUGSNK
500mA Sink Current
1.0
UGATE Sink Current (Note 7)
IUGSNK
VUGATE_PHASE = 2.5V
2.0
LGATE Source Resistance (Note 7)
RLGSRC
500mA Source Current
1.0
LGATE Source Current (Note 7)
ILGSRC
VLGATE_PGND = 2.5V
2.0
LGATE Sink Resistance (Note 7)
RLGSNK
500mA Sink Current
0.5
LGATE Sink Current (Note 7)
ILGSNK
VLGATE_PGND = 2.5V
4.0
A
1.1
kΩ
UGATE Pull-Down Resistor
RPD
1.5
Ω
A
1.5
Ω
A
1.5
Ω
A
0.9
Ω
UGATE Turn-On Propagation Delay
tPDRU
PVCC = 5V, UGATE open
20
30
44
ns
LGATE Turn-On Propagation Delay
tPDRL
PVCC = 5V, LGATE open
7
15
30
ns
0.56
0.69
0.76
V
5.0
µA
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 10mA
Reverse Leakage
IR
VR = 16V
6
FN6753.1
July 8, 2010
ISL6263D
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise stated. All typical specifications
TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range,
-10°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
0.11
0.40
V
1.0
µA
POWER-GOOD and PROTECTION MONITOR
PGOOD Low Voltage
VPGOOD
IPGOOD = 4mA
PGOOD Leakage Current
IPGOOD
VPGOOD = 3.3V
-1.0
VO rising above VSOFT > 1ms
155
195
235
mV
Overvoltage Threshold (VO-VSOFT)
VOVP
Severe Overvoltage Threshold
VOVPS
VO rising above 1.55V reference > 0.5µs
1.525
1.550
1.575
V
OCSET Reference Current
IOCSET
RRBIAS = 150kΩ
9.95
10.15
10.35
µA
3
mV
-240
mV
1
V
OCSET Voltage Threshold Offset
Undervoltage Threshold (VSOFT-VO)
VOCSET_OFS VICOMP rising above VOCSET > 120µs
VUVF
VO falling below VSOFT for > 1ms
-3
-360
-300
CONTROL INPUTS
VR_ON Input Low
VVR_ONL
VR_ON Input High
VVR_ONH
AF_EN Input Low
VAF_ENL
AF_EN Input High
VAF_ENH
VR_ON Leakage
IVR_ONL
VVR_ON = 0V
IVR_ONH
VVR_ON = 3.3V
IAF_ENL
VAF_EN = 0V
IAF_ENH
VAF_EN = 3.3V
AF_EN Leakage
VID<2:0> and OFFSET<1:0> Input Low
VVIDL
VID<2:0> and OFFSET<1:0> Input High
VVIDH
FDE Input Low
VFDEL
FDE Input High
VFDEH
VID<2:0> and OFFSET<1:0> Leakage
FDE Leakage
2.3
V
1
2.3
-1.0
V
0
0
-1.0
µA
1.0
0
0.45
1.0
µA
0.3
V
V
0.3
0.7
VVID = 0V
IVIDH
VVID = 1.0V
IFDEL
VFDE = 0V
IFDEH
VFDE = 1.0V
-1.0
V
V
0
0.45
-1.0
µA
µA
0.7
IVIDL
V
µA
1.0
0
0.45
µA
µA
1.0
µA
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits established by characterization and are not production tested.
7
FN6753.1
July 8, 2010
ISL6263D
Functional Pin Descriptions
RBIAS (Pin 1) - Sets the internal 10µA current reference.
Connect a 150kΩ±1%resistor from RBIAS to VSS.
SOFT (Pin 2) - Sets the output voltage slew-rate. Connect
an X5R or X7R ceramic capacitor from SOFT to VSS. The
SOFT pin is the non-inverting input of the error amplifier.
OCSET (Pin 3) - Sets the overcurrent threshold. Connect a
resistor from OCSET to VO.
VW (Pin 4) - Sets the static PWM switching frequency in
continuous conduction mode. Connect a resistor from VW to
COMP.
COMP (Pin 5) - Connects to the output of the control loop
error amplifier.
FB (Pin 6) - Connects to the inverting input of the control
loop error amplifier.
VDIFF (Pin 7) - Connects to the output of the VDIFF
differential amplifier. Together with FB pin, used for the
output voltage feedback.
VSEN (Pin 8) - This is the VOUT input of the GPU processor
Kelvin connection. Connects internally to the non-inverting
inputs of the VDIFF differential amplifier.
RTN (Pin 9) - This is the VGND input of the GPU processor
Kelvin connection. Connects internally to the inverting inputs
of the VDIFF differential amplifier.
ICOMP (Pin 10) - Connects to the output of the differential
current sense amplifier and to the non-inverting inputs of the
overcurrent comparator. Used for output current monitor and
overcurrent protection.
ISN (Pin 11) - This is the feedback of the current sense
amplifier. Connects internally to the inverting input of the
current sense amplifier. Used for output current sense.
VO (Pin 12) - Connects to the inverting inputs of the VDIFF
differential amplifier. Measures the output voltage VOUT.
ISP (Pin 13) - Connects to the non-inverting input of the
current sense amplifier. Used for output current sense.
VIN (Pin 14) - Connects to the R3 PWM modulator providing
input voltage feed-forward. For optimum input voltage
transient response, connect near the drain of the high-side
MOSFETs.
VSS (Pin 15) - Analog ground.
VDD (Pin 16) - Input power supply for the IC. Connect to
+5VDC and decouple with at least a 1µF MLCC capacitor
from the VDD pin to the VSS pin.
UGATE (Pin 18) - High-side MOSFET gate driver output.
Connect to the gate of the high-side MOSFET.
PHASE (Pin 19) - Current return path for the UGATE
high-side MOSFET gate driver. Detects the polarity of the
PHASE node voltage for diode emulation. Connect the
PHASE pin to the drains of the low-side MOSFETs.
PGND (Pin 20) - Current return path for the LGATE low-side
MOSFET gate driver. The PGND pin only conducts current
when LGATE pulls down. Connect the PGND pin to the
sources of the low-side MOSFETs.
LGATE (Pin 21) - Low-side MOSFET gate driver output.
Connect to the gate of the low-side MOSFET.
PVCC (Pin 22) - Input power supply for the low-side
MOSFET gate driver, and the high-side MOSFET gate
driver, via the internal bootstrap diode connected between
the PVCC and BOOT pins. Connect to +5VDC and decouple
with at least 1µF of an MLCC capacitor from the PVCC pin to
the PGND pin.
OFFSET0 (Pin 23) - A logic high signal will incrementally
provide 12.5mV offset for the DAC output voltage. OFFSET0
pin should not be floated.
OFFSET1 (Pin 24) - A logic high signal will incrementally
provide 25mV offset for the DAC output voltage. OFFSET1
pin should not be floated.
VID0:VID2 (Pin 25:Pin 27) - Voltage identification inputs.
VID0 input is the least significant bit (LSB) and VID2 input is
the most significant bit (MSB).
IMON (Pin 28) - A voltage signal proportional to the output
current of the converter.
VR_ON (Pin 29) - A high logic signal on this pin enables the
converter and a low logic signal disables the converter.
AF_EN (Pin 30) - Together with FDE pin, used to program
the diode-emulation and audio filter behavior.
PGOOD (Pin 31) - The PGOOD pin is an open-drain output
that indicates when the converter is able to supply regulated
voltage. Connect the PGOOD pin to a maximum of 5V
through a pull-up resistor.
FDE (Pin 32) - Together with AF_EN pin, the FDE pin is
used to program the diode-emulation and audio filter
behavior.
BOTTOM - Connects to substrate. Electrically isolated but
should be connected to VSS. Requires best practical
thermal coupling to PCB.
BOOT (Pin 17) - Input power supply for the high-side
MOSFET gate driver. Connect an MLCC bootstrap capacitor
from the BOOT pin to the PHASE pin.
8
FN6753.1
July 8, 2010
ISL6263D
Theory of Operation
The R3 Modulator
The heart of the ISL6263D is Intersil’s Robust-Ripple-Regulator
(R3) Technology™. The R3 modulator is a hybrid of fixed
frequency PWM control, and variable frequency hysteretic
control that will simultaneously affect the PWM switching
frequency and PWM duty cycle in response to input voltage
and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal VR that
appears across the internal ripple-capacitor CR. The V R
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
VSOFT, together produce the voltage-ripple signal VR.
A voltage window signal V W is created across the VW and
COMP pins by sourcing a current proportional to gmVSOFT
through a parallel network consisting of resistor RFSET and
capacitor CFSET. The synthesized voltage-ripple signal VR
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V W and VCOMP. Operating on these
large-amplitude, low noise synthesized signals allows the
ISL6263D to achieve lower output ripple and lower phase
jitter than either conventional hysteretic or fixed frequency
PWM controllers. Unlike conventional hysteretic converters,
the ISL6263D has an error amplifier that allows the controller
to maintain tight voltage regulation accuracy throughout the
VID range from 0.7V to 1.0875V.
Voltage Programming
The output voltage VOUT is regulated to the SOFT pin
voltage, VSOFT, which is determined by the DAC output and
is programmed by the external three VID pins. Another two
pins OFFSET0 and OFFSET1 incrementally provide
+12.5mV and +25mV offset of the DAC output voltage,
respectively. Table 1 shows the DAC output specification.
Power-On Reset
The ISL6263D is disabled until the voltage at the VDD pin
has increased above the rising VDD power-on reset (POR)
VDD_THR threshold voltage. The controller will become
disabled when the voltage at the VDD pin decreases below
the falling POR VDD_THF threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263D start-up timing. Once VDD has
ramped above VDD_THR, the controller can be enabled by
pulling the VR_ON pin voltage above the input-high threshold
VVR_ONH. Approximately 100µs later, the soft-start capacitor
CSOFT begins slewing to the designated VID set-point as it is
charged by the soft-start current source ISS. The VOUT output
voltage of the converter follows the VSOFT voltage ramp to
9
within 10% of the VID set-point then counts 13 switching
cycles, then changes the open-drain output of the PGOOD pin
to high impedance. During soft-start, the regulator always
operates in continuous conduction mode (CCM).
VR_ON
90%
~100µs
VSOFT/VOUT
PGOOD
13 SWITCHING CYCLES
FIGURE 4. ISL6263D START-UP TIMING
Static Regulation
The VOUT output voltage will be regulated to the value set
by the VID inputs per Table 1. A true differential amplifier
connected to the VSEN and RTN pins implements processor
Kelvin sense for precise core voltage regulation at the GPU
voltage sense points.
The ISL6263D can accommodate DCR current sense or
discrete resistor current sense. The DCR current sense uses
the intrinsic series resistance of the output inductor, as
shown in the application circuit of Figure 2. The discrete
resistor current sense uses a shunt connected in series with
the output inductor, as shown in the application circuit of
Figure 3. In both cases the signal is fed to the non-inverting
input of the current sense amplifier at the ISP pin, where it is
measured differentially with respect to the output voltage of
the converter at the VO pin and amplified. The voltage at the
ICOMP pin minus the output voltage measured at the VO
pin, is proportional to the total inductor current. This
information is used for overcurrent protection and current
monitoring. It is important to note that this current
measurement should not be confused with the synthetic
current ripple information created within the R3 modulator.
When using inductor DCR current sense, an NTC
compensation network is optional to compensate the
positive temperature coefficient of the copper winding, thus
maintaining the current sense accuracy.
Processor Kelvin Voltage Sense
The remote voltage sense input pins VSEN and RTN of the
ISL6263D are to be terminated at the die of the GPU. Kelvin
sense allows the voltage regulator to tightly control the
processor voltage at the die, compensating for various
resistive voltage drops in the power delivery path.
FN6753.1
July 8, 2010
ISL6263D
TABLE 1. VID AND OFFSET TRUTH TABLE
DAC OUTPUT VOLTAGE (VSOFT) (mV)
VID CODE
OFFSET1 = 0
OFFSET1 = 1
VID2
VID1
VID0
OFFSET0 = 0
OFFSET0 = 1
OFFSET0 = 0
OFFSET0 = 1
0
0
0
1050
1062.5
1075
1087.5
0
0
1
1000
1012.5
1025
1037.5
0
1
0
950
962.5
975
987.5
0
1
1
900
912.5
925
937.5
1
0
0
850
862.5
875
887.5
1
0
1
800
812.5
825
837.5
1
1
0
750
762.5
775
787.5
1
1
1
700
712.5
725
737.5
by allowing the converter to operate in diode-emulation
mode (DEM) where the low-side MOSFET behaves as a
smart-diode, forcing the device to block negative inductor
current flow.
Since the voltage feedback is sensed at the processor die,
removing the GPU will open the voltage feedback path of the
regulator, causing the output voltage to rise towards VIN.
The ISL6263D will shut down when the voltage between the
VO and VSS pins exceeds the severe overvoltage protection
threshold VOVPS of 1.55V. To prevent this issue from
occurring, it is recommended to install resistors ROPN1 and
ROPN2, as shown in Figure 5. These resistors provide
voltage feedback from the regulator local output in the
absence of the GPU. These resistors should be in the range
of 20Ω to 100Ω
Positive-going inductor current flows from either the source of
the high-side MOSFET, or the drain of the low-side MOSFET.
Negative-going inductor current flows into the source of the
high-side MOSFET, or into the drain of the low-side MOSFET.
When the low-side MOSFET conducts positive inductor
current, the phase voltage will be negative with respect to the
VSS pin. Conversely, when the low-side MOSFET conducts
negative inductor current, the phase voltage will be positive
with respect to the VSS pin. Negative inductor current occurs
when the output DC load current is less than ½ the inductor
ripple current. Sinking negative inductor current through the
low-side MOSFET lowers efficiency through unnecessary
Diode Emulation Mode and Audio Filter Operation
The ISL6263D operates in continuous-conduction-mode
(CCM) during heavy load for minimum conduction loss by
forcing the low-side MOSFET to operate as a synchronous
rectifier. An improvement in light-load efficiency is achieved
VDD
+
Isense
-
ISP
ESR
ISN
VSEN
+
CFILTER1
RFILTER1
VOUT
RFILTER2
RTN
-
RNTC
RIS1
CIS
RIS2
VO
-
CN
ICOMP
+
COUT
RS
Rp
OCP
+
ROCSET
ROPN1
OCSET
VDIFF
CFILTER2
CFILTER3
VGND
TO
PROCESSOR
KELVIN
CONNECTIONS
ROPN2

-
DCR
PHASE
RNTCS
10µA
LOUT
FIGURE 5. SIMPLIFIED GPU VOLTAGE KELVIN SENSE AND INDUCTOR DCR CURRENT SENSE
10
FN6753.1
July 8, 2010
ISL6263D
conduction losses. Efficiency can be further improved with a
reduction of unnecessary switching losses by reducing the
PWM frequency. The PWM frequency is configured to
automatically make a step-reduction upon entering DEM by
forcing a step-increase of the window voltage V W. The
characteristic PWM frequency reduction, coincident with
decreasing load, is accelerated by the step-increase of the
window voltage.
The converter will enter DEM after detecting three
consecutive PWM pulses with negative inductor current. The
negative inductor current is detected during the time that the
high-side MOSFET gate driver output UGATE is low, with the
exception of a brief blanking period. The voltage between
the PHASE pin and VSS pin is monitored by a comparator
that latches upon detection of positive phase voltage. The
converter will return to CCM after detecting three
consecutive PWM pulses with positive inductor current.
The inductor current is considered positive if the phase
comparator has not been latched while UGATE is low.
Because the switching frequency in DEM is a function of load
current, very light load condition can produce frequencies well
into the audio band. To eliminate this audible noise, an audio
filter can be enabled that briefly turns on the low-side
MOSFET gate driver LGATE approximately every 35µs.
The DEM and audio filter operation are programmed by the
AF_EN and FDE pins according to Table 2.
TABLE 2. DIODE-EMULATION MODE AND AUDIO-FILTER
AUDIO
FILTER
FDE
AF_EN
DEM STATUS
0
0
0
1
1
0
Enabled
Disabled
1
1
Enabled
Enabled
Forced CCM
Smooth mode transitions are facilitated by the R3 modulator,
which correctly maintains the internally synthesized ripple
current information throughout mode transitions.
Current Monitor
The ISL6263D features a current monitor output. The
voltage between the IMON and VSS pins is proportional to
the output inductor current. The output inductor current is
proportional to the voltage between the ICOMP and VO pins.
The IMON pin has source and sink capability for close
tracking of transient current events. The current monitor
output is expressed in Equation 1:
(EQ. 1)
V IMON =  V ICOMP – V O   31
Protection
The ISL6263D provides overcurrent protection (OCP),
overvoltage protection (OVP), and undervoltage protection
(UVP), as shown in Table 3.
11
Overcurrent protection is tied to the current sense amplifier.
Given the overcurrent set point IOC, the maximum voltage at
ICOMP pin VICOMP(max) (which is the voltage when OCP
happens) can be determined by the current sense network
(explained in “Inductor DCR Current Sense” on page 13 and
“Resistor Current Sense” on page 14). During start-up, the
ICOMP pin must fall 25mV below the OCSET pin to reset the
overcurrent comparator, which requires (VICOMP(max) - VO)
> 25mV.
The OCP threshold detector is checked every 15µs and will
increment a counter if the OCP threshold is exceeded;
conversely the counter will be decremented if the load
current is below the OCP threshold. The counter will latch an
OCP fault when the counter reaches eight. The fastest OCP
response for overcurrent levels that are no more than 2.5x
the OCP threshold is 120µs, which is eight counts at 15µs
each. The ISL6263D protects against hard shorts by latching
an OCP fault within 2µs for overcurrent levels exceeding
2.5x the OCP threshold.
The overcurrent threshold is determined by the resistor
ROCSET between OCSET pin and VO pin. The value of
ROCSET is calculated in Equation 2:
V ICOMP  max  – V O
R OCSET = ---------------------------------------------------10A
(EQ. 2)
For example, choose VICOMP(max) - VO = 80mV, ROCSET
can use a 8.06kΩresistor, according to Equation 2.
Undervoltage protection is independent of the overcurrent
protection. If the output voltage measured on the VO pin is
less than +300mV below the voltage on the SOFT pin for
longer than 1ms, the controller will latch a UVP fault. If the
output voltage measured on the VO pin is greater than
195mV above the voltage on the SOFT pin for longer than
1ms, the controller will latch an OVP fault. Keep in mind that
VSOFT will equal the voltage level commanded by the VID
states only after the soft-start capacitor CSOFT has slewed to
the VID DAC output voltage. The UVP and OVP detection
circuits act on static and dynamic VSOFT voltage.
When an OCP, OVP, or UVP fault has been latched, PGOOD
becomes a low impedance and the gate driver outputs
UGATE and LGATE are pulled low. The energy stored in the
inductor is dissipated as current flows through the low-side
MOSFET body diode. The controller will remain latched in
the fault state until the VR_ON pin has been pulled below the
falling VR_ON threshold voltage VVR_ONL or until VDD has
gone below the falling POR threshold voltage VVDD_THF.
A severe-overvoltage protection fault occurs immediately after
the voltage between the VO and VSS pins exceed the rising
severe-overvoltage threshold VOVPS, which is 1.55V. The
ISL6263D will latch UGATE and PGOOD low but unlike other
protective faults, LGATE remains high until the voltage
between VO and VSS falls below approximately 0.76V, at
which time LGATE is pulled low. The LGATE pin will continue
to switch high and low at 1.55V and 0.76V until VDD has gone
FN6753.1
July 8, 2010
ISL6263D
Gate-Driver Outputs LGATE and UGATE
The ISL6263D has internal high-side and low-side
N-Channel MOSFET gate-drivers. The LGATE driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant. The LGATE
pull-down resistance is very low in order to clamp the
gate-source voltage of the MOSFET below the VGS(th) at
turn-off. The current transient through the low-side gate at
turn-off can be considerable due to the characteristic large
switching charge of a low rDS(ON) MOSFET.
PWM
across the BOOT and PHASE pins. The boot capacitor is
charged from PVCC through an internal bootstrap diode
each time the low-side MOSFET turns on, pulling the
PHASE pin low.
Internal Bootstrap Diode
The ISL6263D has an integrated boot-strap Schottky diode
connected from the PVCC pin to the BOOT pin. Simply adding
an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit.
2.0
1.8
1.6
CBOOT_CAP (µF)
below the falling POR threshold voltage VVDD_THF. This
provides maximum protection against a shorted high-side
MOSFET while preventing the output voltage from ringing
below ground. The severe-overvoltage fault circuit can be
triggered after another fault has already been latched.
1.4
1.2
1.0
0.8
QGATE = 100nC
0.6
nC
50
0.4
LGATE
0.2
1V
20nC
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VBOOT_CAP (V)
UGATE
1V
t PDRU
t PDRL
FIGURE 6. GATE DRIVER TIMING DIAGRAM
Adaptive shoot-through protection prevents the gate-driver
outputs from going high until the opposite gate-driver output
has fallen below approximately 1V. The UGATE turn-on
propagation delay tPDRU and LGATE turn-on propagation
delay tPDRL are found in the “Electrical Specifications” table
on page 6. The power for the LGATE gate-driver is sourced
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a bootstrap capacitor connected
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
The minimum value of the bootstrap capacitor can be
calculated using Equation 3:
Q GATE
C BOOT  -----------------------V BOOT
(EQ. 3)
where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The VBOOT term is
defined as the allowable droop in the rail of the upper drive.
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263D
FAULT DURATION
PRIOR TO PROTECTION
FAULT TYPE
PROTECTION ACTIONS
FAULT RESET
Overcurrent
120µs
LGATE, UGATE, and PGOOD latched low
Cycle VR_ON or VDD
Short Circuit
<2µs
LGATE, UGATE, and PGOOD latched low
Cycle VR_ON or VDD
Overvoltage (+195mV) between VO
pin and SOFT pin
1ms
LGATE, UGATE, and PGOOD latched low
Cycle VR_ON or VDD
UGATE, and PGOOD latched low, LGATE
toggles ON when VO>1.55V OFF when VO
<0.76V until fault reset
Cycle VDD only
LGATE, UGATE, and PGOOD latched low
Cycle VR_ON or VDD
Severe Overvoltage (+1.55V) between
VO pin and VSS pin
Immediately
Undervoltage (-300mV) between VO
pin and SOFT pin
1ms
12
FN6753.1
July 8, 2010
ISL6263D
As an example, suppose an upper MOSFET has a gate
charge, QGATE , of 25nC at 5V and also assume the droop in
the drive voltage at the end of a PWM cycle is 200mV. One
will find that a bootstrap capacitance of at least 0.125µF is
required. The next larger standard value capacitance is
0.15µF. A good quality ceramic capacitor is recommended.
Soft-Start and Soft Dynamic VID Slew Rate
The output voltage of the converter tracks VSOFT, the voltage
across the SOFT and VSS pins. As shown in Figure 1, the
SOFT pin is connected to the output of the VID DAC through
the unidirectional soft-start current source ISS or the
bidirectional soft-dynamic VID current source IDVID, and the
non-inverting input of the error amplifier. Current is sourced
from the SOFT pin when ISS is active. The SOFT pin can both
source and sink current when IDVID is active. The soft-start
capacitor CSOFT changes voltage at a rate proportional to ISS
or IDVID. The ISL6263D automatically selects ISS for the
soft-start sequence so that the in-rush current through the
output capacitors is maintained below the OCP threshold.
Once soft-start is complete, IDVID is automatically selected for
output voltage changes commanded by the VID inputs,
charging CSOFT when the output voltage is commanded to
rise, and discharging CSOFT when the output voltage is
commanded to fall.
The GPU voltage regulator may require a minimum voltage
slew rate, which will be guaranteed by the value of CSOFT.
For example, if the regulator requires 10mV/µs slew rate, the
value of CSOFT can be calculated using Equation 4:
I DVID  min  180A
C SOFT = ----------------------------- = ------------------ = 0.018F
10k
 10mV
----------------
 s 
(EQ. 4)
I DVID is the soft-dynamic VID current source, and its
minimum value is specified in the “Electrical Specifications”
table on page 6. Choosing the next lower standard
component value of 0.015µF will guarantee 10mV/µs slew
rate. This choice of CSOFT controls the start-up slew-rate as
well. One should expect the output voltage during soft-start
to slew to the voltage commanded by the VID settings at a
nominal rate given by Equation 5:
dV SOFT
I SS
42A
2.8mV
- = -----------------------  ---------------------------------------- = -----------------dt
C SOFT 0.015F
s
(EQ. 5)
Note that the slew rate is the average rate of change
between the initial and final voltage values.
It is worth it to mention that the surge current charges the
output capacitors when the output voltage is commanded to
rise. This surge current could be high enough to trigger the
OC protection circuit if the voltage slew rate is too high,
or/and the output capacitance is too large. The overcurrent
set point should guarantee the VID code transition
successful.
RBIAS Current Reference
The RBIAS pin is internally connected to a 1.55V reference
through a 3kΩ resistance. A bias current is established by
connecting a±1% tolerance, 150kΩ resistor between the
RBIAS and VSS pins. This bias current is mirrored, creating the
reference current I OCSET that is sourced from the OCSET pin.
Do not connect any other components to this pin, as they will
have a negative impact on the performance of the IC.
Setting the PWM Switching Frequency
The R3 modulator scheme is not a fixed-frequency
architecture, lacking a fixed-frequency clock signal to produce
PWM. The switching frequency increases during the
application of a load to improve transient performance. The
static PWM frequency varies slightly depending on the input
voltage, output voltage and output current, but this variation is
normally less than 10% in continuous conduction mode.
Refer to Figure 2 and find that resistor R FSET is connected
between the V W and COMP pins. A current is sourced from
VW through RFSET creating the synthetic ripple window
voltage signal V W, which determines the PWM switching
frequency. The relationship between the resistance of RFSET
and the switching frequency in CCM is approximated by
Equation 6:
–6
 t – 0.5  10 
R FSET = --------------------------------------– 12
400  10
(EQ. 6)
t is the switching period. For example, the value of RFSET for
300kHz operation is approximated using Equation 7:
–6
–6
 3.33  10 – 0.5  10 
3
7.1 10 = -------------------------------------------------------------------– 12
400  10
(EQ. 7)
This relationship only applies to operation in constant
conduction mode because the PWM frequency naturally
decreases as the load decreases while in diode emulation
mode.
Inductor DCR Current Sense
ISL6263D provides the option of using the inductor DCR for
current sense. To maintain the current sense accuracy, an NTC
compensation network is optional when using DCR sense. The
process to compensate the DCR resistance variation takes
several iterative steps. Figure 2 shows the DCR sense method.
Figure 8 shows the simplified model of the current sense
circuitry. The inductor DC current IO generates a DC voltage
drop on the inductor DCR. Equation 8 gives this relationship:
V DCR = I O  DCR
(EQ. 8)
An R-C network senses the voltage across the inductor to
get the inductor current information. RN represents the
equivalent resistance of Rp and the optional NTC network
consisting of RNTC and RNTCS. RN is temperature T
dependent and is given by Equation 9:
 R NTC + R NTCS   R P
R N  T  = -----------------------------------------------------------R NTC + R NTCS + R P
(EQ. 9)
If the NTC network is not used, simply set RN(T) = RP.
13
FN6753.1
July 8, 2010
ISL6263D
0.00393 is the temperature coefficient of the copper. To
make VICOMP independent of the inductor temperature, the
NTC characteristic is desired to satisfy:
Sensing the time varying inductor current accurately
requires that the parallel R-C network time constant match
the inductor L/DCR time constant. Equation 10 shows this
relationship:
 RN  T   RS 
L
------------- =  ------------------------------  CN
DCR
 R N  T  + R S
G 1  T    1 + 0.00393   T – 25C    G 1t arg et
(EQ. 10)
where G1target is the desired ratio of VN /VDCR. Therefore,
the temperature characteristics G1, which determines
parameters selection, is described by Equation 17:
Solution of CN yields:
L 
 ------------ DCR
C N = ------------------------------------ RN  T   RS 
 -------------------------------
 R N  T  + R S
G 1t arg et
G 1  T  = ---------------------------------------------------------------1 + 0.00393   T – 25C 
(EQ. 11)
(EQ. 17)
It is recommended to begin the DCR current sense design
using the RNTC, RNTCS, and RP component values of the
evaluation board available from Intersil.
The first step is to adjust RN(T) and RS such that the correct
current information appears between the ISP and VO pins
even at light loads. Assume VN is the voltage drop across
RN(T). The VN to VDCR gain G1(T) provides a reasonable
amount of light load signal from which to derive the current
information. G1(T) is given by Equation 12:
RN  T 
G 1  T  = ------------------------------RN  T  + RS
Given the inductor DCR and the overcurrent set point IOC, the
maximum voltage of ICOMP pin is given by Equation 18:
R  +25C 
R

N
IS2
V ICOMP  max  – V O = I OC  DCR  +25C   -----------------------------------------------   1 + --------------
R  +25C  + R 
R
N
S
IS1
(EQ. 18)
(EQ. 12)
RN, RS, RIS1, RIS2 should be adjusted to meet the
requirement (VICOMP(max) - VO) > 25mV and the time
constant matching according to Equation 10.
The gain of the current sense amplifier circuit is expressed in
Equation 13:
R IS2
K ISENSE = 1 + ------------R IS1
Given the output current IO, the current monitor IMON
voltage can be determined by Equation 19:
(EQ. 13)
R N  +25C 
R IS2

V IMON = 31  I O  DCR  +25C   -----------------------------------------------   1 + --------------
R N  +25C  + R S 
R IS1
The current sense amplifier output voltage is given by
Equation 14:
(EQ. 19)
(EQ. 14)
V ICOMP = V O + V N  K ISENSE
The effectiveness of the RN network is sensitive to the
coupling coefficient between the NTC thermistor and the
inductor. The NTC thermistor should be placed in the closet
proximity of the inductor.
The inductor DCR is a function of temperature T and is
approximately given by Equation 15:
DCR  T  = DCR 25C   1 + 0.00393   T – 25C  
(EQ. 16)
(EQ. 15)
Resistor Current Sense
Figure 3 shows a detailed schematic using discrete resistor
sense of the inductor current. Figure 9 shows the equivalent
circuit. Since the current sense resistor voltage represents the
VDD

OCSET
+
+
RS
ISP
ISN
ICOMP
VO
VDCR
RIS1
-

Isense

RN
OCP
ROCSET
CN
-
RIS2
10µA
FIGURE 8. EQUIVALENT MODEL OF CURRENT SENSE USING INDUCTOR DCR CURRENT SENSE
14
FN6753.1
July 8, 2010
ISL6263D
and given the output current IO, the IMON voltage is
determined by Equation 26:
actual inductor current information, RS and CN simply provide
noise filtering. A low ESL sense resistor is strongly
recommended for RSNS because this parameter is the most
significant source of noise that affects discrete resistor sense.
It is recommended to start out using 100Ω for RS and 47pF for
CN. Since the current sense resistance changes very little
with temperature, the NTC network is not needed for thermal
compensation. Discrete resistor sense design follows the
same approach as inductor DCR sense. The voltage on the
current sense resistor is given by Equation 20:
R IS2

V IMON = 31  I O  R SNS   1 + -------------
R IS1

RS, RP, RIS1, RIS2 should be adjusted to meet the
requirement (VICOMP(max) - VO) > 25mV.
The current sense traces should be routed directly to the
current sense resistor pads for accurate measurement.
However, due to layout imperfection, the calculated RIS2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust RIS2 after the system has
achieved thermal equilibrium at full load.
(EQ. 20)
V RSNS = I O  R SNS
It is optional to parallel a resistor RP to form a voltage divider
with RS to obtain more flexibility. Assume the voltage across
RP is VN, which is given by Equation 21:
RP
V N = V RSNS  ---------------------R +R
S
Dynamic Mode of Operation - Compensation
Parameters
Intersil provides a spreadsheet to calculate the compensator
parameters. Caution needs to be used in choosing the input
resistor to the FB pin. Excessively high resistance will cause
an error to the output voltage regulation due to the bias
current flowing through the FB pin. It is recommended to
keep this resistor below 3kΩ.
(EQ. 21)
P
The current sense amplifier output voltage VICOMP is given
by Equation 22:
R IS2

V ICOMP = V O + V   1 + -------------
N 
R IS1
(EQ. 22)
Layout Considerations
Given a current sense resistor RSNS and the overcurrent set
point IOC, the maximum voltage of ICOMP pin is determined
by Equation 23:
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding.
RP
R IS2

V ICOMP  max  – V O = I OC  R SNS  ----------------------   1 + ------------- (EQ. 23)
RS + RP 
R IS1
Inductor Current Sense and the NTC Placement
Given the output current IO, the current monitor IMON
voltage can be determined by Equation 24:
RP
R IS2

V IMON = 31  I O  R SNS  ----------------------   1 + -------------
RS + RP 
R IS1
It is crucial that the inductor current be sensed directly at the
PCB pads of the sense element, be it DCR sensed or discrete
resistor sensed. The effect of the NTC on the inductor DCR
thermal drift is directly proportional to its thermal coupling with
the inductor and thus, the physical proximity to it.
(EQ. 24)
If RP is not used, the maximum voltage of ICOMP pin is
determined by Equation 25:
R IS2

V ICOMP  max  – V O = I OC  R SNS   1 + -------------
R

IS1
(EQ. 26)
Signal Ground and Power Ground
The ground plane layer should have a single point connection
to the analog ground at the VSS pin. The VSS island should
be located under the IC package along with the weak analog
(EQ. 25)
VDD

OCSET
OCP
+
+
RS
ISP
ISN
ICOMP
VO
RP
(optional)
VRSNS
RIS1
-
+
Isense
-
ROCSET
CN
-
RIS2
10A
FIGURE 9. EQUIVALENT MODEL OF CURRENT SENSE USING DISCRETE RESISTOR CURRENT SENSE
15
FN6753.1
July 8, 2010
ISL6263D
traces and components. The paddle on the bottom of the
ISL6263D QFN package is not electrically connected to the
IC, however, it is recommended to make a good thermal
connection to the VSS island using several vias. Connect the
input capacitors, the output capacitors and the source of the
lower MOSFETs to the power ground plane.
LGATE, PVCC, and PGND
PGND is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path. The LGATE trace should
be routed in parallel with the trace from the PGND pin. These
two traces should be short, wide and away from other traces
because of the high peak current and extremely fast dv/dt.
PVCC should be decoupled to PGND with a ceramic capacitor
physically located as close as practical to the IC pins.
VIAS TO
GROUND
PLANE
GND
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
VOUT
INDUCTOR
PHASE
NODE
HIGH-SIDE
MOSFETS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
VIN
FIGURE 10. TYPICAL POWER COMPONENT PLACEMENT
UGATE, BOOT, and PHASE
PHASE is the return path for the entire UGATE high-side
MOSFET gate driver. The layout for these signals require
similar treatment, but to a greater extent, than those for
LGATE, PVCC, and PGND. These signals swing from
approximately VIN to VSS and are more likely to couple into
other signals.
IMON, SOFT, OCSET, VW, COMP, FB, VDIFF,
ICOMP, ISP, ISN and VO
The traces and components associated with these pins
require close proximity to the IC as well as close proximity to
each other. This section of the converter circuit needs to be
located above the island of analog ground with the
single-point connection to the VSS pin.
Resistor RS
Resistor RS is preferably located near the boundary
between the power ground and the island of analog ground
connected to the VSS pin.
VSEN and RTN
These traces should be laid out as noise sensitive. For
optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor should be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. The filter
capacitors CFILTER1, CFILTER2, and CFILTER3 used in
conjunction with filter resistors RFILTER1 and RFILTER2 form
common mode and differential mode filters, as shown in
Figure 5. The noise environment of the application and
actual board layout conditions will drive the extent of filter
complexity. The maximum recommended resistance for
RFILTER1 and RFILTER2 is approximately 10Ω to avoid
interaction with the 50kΩ input resistance of the remote
sense differential amplifier. The physical location of these
resistors is not as critical as the filter capacitors. Typical
capacitance values for CFILTER1, CFILTER2, and CFILTER3
range between 330pF to 1000pF and should be placed near
the IC.
VID<0:2>, OFFSET<0:1>, AF_EN, PGOOD, and
VR_ON
These are logic signals that do not require special attention.
RBIAS
FDE
The resistor RRBIAS should be placed in close proximity to
the ISL6263D using a noise-free current return path to the
VSS pin.
This logic signal should be treated as noise sensitive and
should be routed away from rapidly rising voltage nodes,
(switching nodes) and other noisy traces.
VIN
Copper Size for the Phase Node
The VIN signal should be connected near the drain of the
high-side MOSFET.
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the high-side MOSFET and the source of the
low-side MOSFET to suppress turn-off voltage spikes.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN6753.1
July 8, 2010
ISL6263D
Package Outline Drawing
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 02/07
4X 3.5
5.00
28X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
32
25
1
5.00
24
3 .10 ± 0 . 15
17
(4X)
8
0.15
9
16
TOP VIEW
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10
4 32X 0.23 - 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
(
( 28X 0 . 5 )
SIDE VIEW
3. 10 )
(32X 0 . 23 )
C
0 . 2 REF
5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
17
FN6753.1
July 8, 2010
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