DATASHEET

ISL6559
ESIGNS
R N E W D NT
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TERSIL
1-888-IN
FN9084.8
Multi-Phase PWM Controller
Features
The ISL6559 provides core-voltage regulation by driving 2 to
4 interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
• Multi-Phase Power Conversion
- 2, 3 or 4 Phase Operation
• Active Channel Current Balancing
• Precision rDS(ON) Current Sharing
- Lossless
- Low Cost
• Input Voltage: 12V or 5V Bias
• Precision CORE Voltage Regulation
- ± 1% System Accuracy Over Temperature
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID Technology
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 4MHz)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
Pinouts
PGOOD
ISL6559CR (32 LEAD QFN)
TOP VIEW
FS/DIS
ISL6559CB (28 LEAD SOIC)
TOP VIEW
VID2 1
32 31 30 29 28 27 26 25
24 PWM4
VID2 5
24 ISEN4
VID1 2
23 ISEN4
VID1 6
23 ISEN1
VID0 3
22 ISEN1
VID0 7
22 PWM1
NC 4
21 PWM1
OFS 8
21 PWM2
OFS 5
20 PWM2
20 GND
19 GND
COMP 6
FB 10
19 ISEN2
FB 7
IOUT 11
18 ISEN3
NC 8
VDIFF 12
17 PWM3
9 10 11 12 13 14 15 16
VSEN 13
16 VCC
RGND 14
15 GND
IOUT
COMP 9
EN
25 PWM4
GND
26 PGOOD
VID3 4
OVP
27 FS/DIS
VID4 3
VID4
28 EN
OVP 2
NC
GND 1
18 ISEN2
PWM3
VCC
GND
GND
RGND
17 ISEN3
VSEN
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to crowbar the output voltage.
An optional second crowbar on VIN, formed with an external
MOSFET or SCR gated by the OVP pin, is triggered when
an over-voltage condition is detected. Under-voltage
conditions are detected, but PWM operation is not disrupted.
Over-current conditions cause a hiccup-mode response as
the controller repeatedly tries to restart. After a set number
of failed startup attempts, the controller latches off. A power
good logic signal indicates when the converter output is
between the UV and OV thresholds.
• Pb-Free Available (RoHS Compliant)
VID3
Outstanding features of this controller IC include
Dynamic VIDTM technology allowing seamless on-the-fly VID
changing without the need of any external components.
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from
a separate supply.
VDIFF
The ISL6559 uses cost and space-saving rDS(ON) sensing
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 50mV using a single external
resistor. The entire system is trimmed to ensure a system
accuracy of ± 1% over temperature.
NC = NO CONNECT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2002-2004. All Rights Reserved.
Dynamic VID is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
ISL6559
Ordering Information
PART #
TEMP. (°C)
Ordering Information (Continued)
PACKAGE
PART #
PKG. DWG. #
TEMP. (°C)
PACKAGE
PKG. DWG. #
ISL6559CB
0 to 70
28 Ld SOIC
M28.3
ISL6559CR-T
ISL6559CBZ*
0 to 70
28 Ld SOIC (Pb-free)
M28.3
ISL6559CRZ-T* 32 Ld 5x5 QFN Tape and Reel (Pb-free)
ISL6559CB-T
28 Ld SOIC Tape and Reel
NOTE: * Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL6559CBZ-T* 28 Ld SOIC Tape and Reel (Pb-free)
ISL6559CR
0 to 70
32 Ld 5x5 QFN
ISL6559CRZ*
0 to 70
32 Ld 5x5 QFN (Pb-free) L32.5x5
32 Ld 5x5 QFN Tape and Reel
L32.5x5
Block Diagram
PGOOD
VCC
FS/DIS
EN
1.23V
VID4
OSCILLATOR
AND
SAWTOOTH
6V
VID3
DYNAMIC
VID2
POR
AND
SOFT START
VID
DAC
UV
VID1
350mV
+
VID0
PWM1
+
+
PWM2
-
+
E/A
FB
-
+
PWM3
+
COMP
+
OFS
PWM4
+
x 0.1
100A
+
OVP
VDIFF
OV
2.2V
VSEN
DIFF
ISEN1
OC
RGND
IOUT
I1
90A
+
AVERAGE
I2
+
1/N
+
I3
+
CURRENT
SENSE
&
PHASE
DETECT
I4
ISEN2
ISEN3
ISEN4
N PHASES
GND
2
FN9084.8
December 29, 2004
ISL6559
Typical Application - 3 Phase Converter
+12V
+12V
BOOT
PVCC
UGATE
VCC
PHASE
DRIVER
HIP6601B
PWM
LGATE
RISEN1
GND
+12V
300
ISL6559
VOUT
VCC
VSEN
+12V
RGND
PWM4
VDIFF
ISEN4
RFB
NC
BOOT
PVCC
UGATE
VCC
FB
CC
+12V
PHASE
PWM1
IOUT
DRIVER
HIP6601B
ISEN1
RC
LGATE
COMP
PWM2
OFS
PWM
RISEN2
GND
ISEN2
ROFS
FS/DIS
PWM3
RT
ISEN3
+12V
+12V
VID4
VID3
BOOT
PVCC
UGATE
VID2
VCC
VID1
VID0
PHASE
DRIVER
HIP6601B
PGOOD
LGATE
OVP
PWM
RISEN3
GND
GND
3
FN9084.8
December 29, 2004
ISL6559
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Input, Output, or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class TBD
Thermal Resistance
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
JA (°C/W)
JC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
60
N/A
QFN Package (Note 2) . . . . . . . . . . . .
33
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. JC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Operating Conditions: VCC = 5V, TA = 0°C to 70°C. Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Nominal Supply
VCC = 5VDC; EN = 5VDC; RT = 100 k ±1%
8.0
10.8
14.0
mA
Shutdown Supply
VCC = 5VDC; EN = 0VDC; RT = 100 k ±1%
8.0
10.3
13.0
mA
VCC Voltage
VCC tied to 12VDC thru 300 resistor, RT = 100k
5.63
5.8
5.97
V
VCC Sink Current
VCC tied to 12VDC thru 300 resistor, RT = 100k
15
20
25
mA
VCC Rising
4.25
4.35
4.50
V
VCC Falling
3.75
3.85
4.00
V
EN Rising
1.205
1.23
1.255
V
Hysteresis
86
92
98
mV
0.792
0.8
0.808
V
SHUNT REGULATOR
POWER-ON RESET AND ENABLE
POR Threshold
ENABLE Threshold
REFERENCE VOLTAGE AND DAC
Reference Voltage
System Accuracy
(Note 3)
-1
-
1
%VID
VID on Fly Step Size
RT = 100k
-
25
-
mV
VID Pull Up
-
-20
-
A
VID Input Low Level
-
-
1
V
VID Input High Level
-
1.36
1.60
V
-
100
-
A
47.0
50.0
53.0
mV
Accuracy
-10
-
10
%
Adjustment Range
0.08
-
1.0
MHz
0.8
1.0
1.2
V
Sawtooth Amplitude
-
1.37
-
V
Max Duty Cycle
-
75
-
%
PIN-ADJUSTABLE OFFSET
OFS Current
Offset Accuracy
ROFS = 5.00k±1%
OSCILLATOR
Disable Voltage
IFS/DIS = 1mA
4
FN9084.8
December 29, 2004
ISL6559
Electrical Specifications
Operating Conditions: VCC = 5V, TA = 0°C to 70°C. Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER
Open-Loop Gain
RL = 10k to ground
-
72
-
dB
Open-Loop Bandwidth
CL = 100pF, RL = 10k to ground
-
18
-
MHz
Slew Rate
CL = 100pF, Load = ±400mA
-
7.1
11
V/s
Maximum Output Voltage
RL = 10k to ground
3.6
4.5
-
V
Source Current
3.0
7.0
9.5
mA
Sink Current
1.6
3.0
5.4
mA
Input Impedance
-
80
-
k
Bandwidth
-
20
-
MHz
Slew Rate
-
6
-
V/s
-5
-
5
%
-
6
-
mV
72
90
108
A
-
-
0.4
V
REMOTE-SENSE AMPLIFIER
SENSE CURRENT
IOUT Accuracy
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 50A
ISEN Offset Voltage
Over-Current Trip Level
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
IPGOOD = 4mA
Under-Voltage Offset From VID
VSEN Falling
320
350
420
mV
Over-Voltage Threshold
VSEN Rising
2.08
2.13
2.20
V
OVP Voltage
IOVP = 100mA, VCC = 5V
2.2
3.28
4.0
V
NOTE:
3. These parts are designed and adjusted for accuracy within the system tolerance
Functional Pin Description
COMP 9
20 GND
21 PWM1
OFS 5
20 PWM2
COMP 6
19 ISEN2
FB 7
NC 8
18 ISEN3
17 PWM3
VSEN 13
16 VCC
RGND 14
15 GND
19 GND
18 ISEN2
17 ISEN3
9 10 11 12 13 14 15 16
IOUT
IOUT 11
PGOOD
22 ISEN1
NC 4
FB 10
VDIFF 12
FS/DIS
21 PWM2
23 ISEN4
VID0 3
PWM3
OFS 8
EN
22 PWM1
VID1 2
VCC
23 ISEN1
VID0 7
GND
VID1 6
32 31 30 29 28 27 26 25
24 PWM4
GND
24 ISEN4
OVP
25 PWM4
VID2 5
VID2 1
GND
VID3 4
VID4
26 PGOOD
RGND
VID4 3
NC
27 FS/DIS
VSEN
28 EN
OVP 2
VDIFF
GND 1
ISL6559CR (32 LEAD QFN)
TOP VIEW
VID3
ISL6559CB (28 LEAD SOIC)
TOP VIEW
NC = NO CONNECT
GND
Bias and reference ground for the IC.
this pin to the gate of an SCR or MOSFET tied across VIN
and ground to prevent damage to a load device.
VID4, VID3, VID2, VID1, VID0
The state of these five inputs program the internal DAC,
which provides the reference voltage for output regulation.
Connect these pins to either open-drain or active pull-up
type outputs. Pulling these pins above 2.9V can cause a
reference offset inaccuracy.
OFS
Connecting a resistor between this pin and ground creates a
positive offset voltage which is added to the DAC voltage,
allowing easy implementation of load-line regulation. For no
offset, simply tie this pin to ground.
FB and COMP
The internal error amplifier inverting input and output
respectively. Connect the external R-C feedback
compensation network of the regulator to these pins.
IOUT
OVP
Over-voltage protection pin. This pin pulls to VCC and is
latched when an over-voltage condition is detected. Connect
5
The current carried out of this pin is proportional to output
current and can be used to incorporate output voltage droop
FN9084.8
December 29, 2004
ISL6559
and/or load sharing. The scale factor is set by the ratio of the
ISEN resistors and the lower MOSFET rDS(ON). If droop is
desired, connect this pin to FB. When not used for droop or
load sharing, simply leave this pin open.
VSEN, RGND, VDIFF
VSEN and RGND are the inputs to the differential remotesense amplifier. Connect these pins to the sense points of
the remote load. Connect an appropriately sized feedback
resistor, RFB, between VDIFF and FB.
VCC
Supplies all the power necessary to operate the chip. The IC
starts to operate when the voltage on this pin exceeds the
rising POR threshold and shuts down when the voltage on
this pin drops below the falling POR threshold. Connect this
pin directly to a +5V supply or through a series 300 resistor
to a +12V supply.
ISEN1, ISEN2, ISEN3, ISEN4
Current sense inputs. A resistor connected between these
pins and their respective phase node sets a current
proportional to the current in the lower MOSFET during it’s
conduction interval. This current is used as a reference for
channel balancing, load sharing, protection, and load-line
regulation. Inactive channels should have their respective
sense inputs left open.
PWM1, PWM2, PWM3, PWM4
Pulse-width modulating outputs. Connect these pins to the
individual HIP660x driver PWM input pins. These logic
outputs command the driver IC(s) in switching the halfbridge configuration of MOSFETs.The number of active
channels is determined by the state of PWM3 and PWM4. If
PWM3 is tied to VCC, this indicates to the controller that two
channel operation is desired. In this case, PWM 4 should be
left open or tied to VCC. Shorting PWM4 to VCC indicates
that three channel operation is desired.
MOSFET drivers. If this function is not required, simply tie
this pin to VCC.
Multi-Phase Power Conversion
Microprocessor load current profiles have changed to the
point where the multi-phase power conversion advantage is
pronounced. The technical challenges associated with
producing a single-phase converter which is both costeffective and thermally viable have forced a change to the
cost-saving approach of multi-phase. The ISL6559 controller
helps reduce the complexity of implementation by integrating
vital functions and requiring minimal output components.
The block diagram in Figure 1 provides a top level view of
multi-phase power conversion using the ISL6559 controller.
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-topeak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
IL1 + IL2 + IL3, 7A/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
PGOOD
Power good is an open-drain logic output that changes to a
logic low when the voltage at VDIFF is 350mV below the VID
setting or above 2.2V.
PWM2, 5V/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
FS/DIS
A dual function pin for setting the switching frequency and
disabling the controller. Place a resistor from this pin to
ground to set the switching frequency between 80kHz and
1MHz. Pulling this pin below 0.8V disables the controller.
EN
Threshold sensitive enable input of the controller. Transition
this pin above 1.23V (typical enable threshold) to initiate a
soft-start cycle. Pull this pin below 1.14V, taking into account
the enable hysteresis, to disable the controller once in
operation. Connect a resistor divider to this pin to set the
power-on voltage level for proper coordination with Intersil
6
1s/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3),
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle, or 1.33s, after the PWM
pulse of the previous phase. The peak-to-peak current
waveforms for each phase is about 7A, and the dc
components of the inductor currents combine to feed the load.
FN9084.8
December 29, 2004
ISL6559
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
 V IN – V OUT  V OUT
I PP = ----------------------------------------------------L fS V
(EQ. 1)
IN
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Outputvoltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
 V IN – N V OUT  V OUT
I C, PP = ----------------------------------------------------------L fS V
(EQ. 2)
IN
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1s/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
The converter depicted in Figure 2 delivers 36A to a 1.5V
load from a 12V input. The RMS input capacitor current is
5.9A. Compare this to a single-phase converter also
stepping down 12V to 1.5V at 36A. The single-phase
7
converter has 11.9A RMS input capacitor current. The
single-phase converter must use an input capacitor bank
with twice the RMS current capacity as the equivalent threephase converter.
Figures 15, 16 and 17 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution. Figure 18 shows the single
phase input-capacitor RMS current for comparison.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6559
is four. One switching cycle is defined as the time between
PWM1 pulse termination signals. The pulse termination
signal is an internally generated clock signal which triggers
the falling edge of PWM1. The cycle time of the pulse
termination signal is the inverse of the switching frequency
set by the resistor between the FS/DIS pin and ground. Each
cycle begins when the clock signal commands the channel-1
PWM output to go low. The PWM1 transition signals the
channel-1 MOSFET driver to turn off the channel-1 upper
MOSFET and turn on the channel-1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
terminates 1/4 of a cycle after PWM1. The PWM 3 output
follows another 1/4 of a cycle after PWM2. PWM4 terminates
another 1/4 of a cycle after PWM3.
If PWM3 is connected to VCC, then two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later.
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
increments.
Once a PWM signal transitions low, it is held low for a
minimum of 1/4 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 1. When the modified
VCOMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sensing
During the forced off time following a PWM transition low, the
controller senses channel load current by sampling the
voltage across the lower MOSFET rDS(ON), see Figure 3. A
ground-referenced amplifier, internal to the ISL6559,
connects to the PHASE node through a resistor, RISEN. The
voltage across RISEN is equivalent to the voltage drop
FN9084.8
December 29, 2004
ISL6559
VIN
I
In
r DS  ON 
SEN = I L ------------------------R
ISEN
CHANNEL N
UPPER MOSFET
IL
SAMPLE
&
HOLD
I 1 + I 2 + I N
I AVG = ---------------------------------N
ISEN(n)
-
RISEN
-
+
I L r DS  ON 
+
EXTERNAL CIRCUIT
FIGURE 3. INTERNAL AND EXTERNAL CURRENT-SENSING
CIRCUITRY
across the RDS(ON) of the lower MOSFET while it is
conducting. The resulting current into the ISEN pin is
proportional to the channel current, IL. The ISEN current is
then sampled and held after sufficient settling time every
switching cycle. The sampled current, In, is used for
channel-current balance, load-line regulation, overcurrent
protection, and module current sharing. From Figure 3, the
following equation for In is derived:
r DS  ON 
I n = I L ---------------------R ISEN
(EQ. 3)
where IL is the channel current.
If RDS(ON) sensing is not desired, an independent currentsense resistor in series with the lower MOSFET source can
serve as a sense element. The circuitry shown in Figure 3
represents channel n of an N-channel converter. This
circuitry is repeated for each channel in the converter, but
may not be active depending upon the status of the PWM3
and PWM4 pins as described in the previous section.
Channel-Current Balance
The sampled current, In, from each active channel is used to
gauge both overall load current and the relative channel
current carried in each leg of the converter. The individual
sample currents are summed and divided by the number of
VCOMP
+
+
-
PWM1
SAWTOOTH SIGNAL
f(j)
I4 *
IER
IAVG
-
N

+
I3 *
I2
I1
NOTE: *CHANNELS 3 and 4 are OPTIONAL.
FIGURE 4. CHANNEL-1 PWM FUNCTION AND CURRENTBALANCE ADJUSTMENT
8
(EQ. 4)
I OUT r DS  ON 
- ---------------------I AVG = -----------N
R ISEN
where N is the number of active channels and IOUT is the
total load current.
CHANNEL N
LOWER MOSFET
ISL6559 INTERNAL CIRCUIT
active channels. The resulting average current, IAVG,
provides a measure of the total load current demand on the
converter and the appropriate level of channel current. Using
Figures 3 and 4, the average current is defined as
The average current is then subtracted from the individual
channel sample currents. The resulting error current, IER, is
then filtered before it adjusts VCOMP. The modified VCOMP
signal is compared to a sawtooth ramp signal and produces
a pulse width which corrects for any unbalance and drives
the error current toward zero. Figure 4 illustrates Intersil’s
patented current-balance method as implemented on
channel-1 of a multi-phase converter.
Two considerations designers face are MOSFET selection
and inductor design. Both are significantly improved when
channel currents track at any load level. The need for
complex drive schemes for multiple MOSFETs, exotic
magnetic materials, and expensive heat sinks is avoided.
Resulting in a cost-effective and easy to implement solution
relative to single-phase conversion. Channel-current
balance insures the thermal advantage of multi-phase
conversion is realized. Heat dissipation is spread over
multiple channels and a greater area than single phase
approaches.
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one or two channels may be able
to cool more effectively than the other(s) due to nearby air
flow or heat sinking components. The other channel(s) may
have more difficulty cooling with comparatively less air flow
and heat sinking. The hotter channels may also be located
close to other heat-generating components tending to drive
their temperature even higher. In these cases, the proper
selection of the current sense resistors (RISEN in Figure 3)
introduces channel current unbalance into the system.
Increasing the value of RISEN in the cooler channels and
decreasing it in the hotter channels moves all channels into
thermal balance at the expense of current balance.
Voltage Regulation
The output of the error amplifier, VCOMP, is compared to the
sawtooth waveform to modulate the pulse width of the PWM
signals. The PWM signals control the timing of the Intersil
MOSFET drivers and regulate the converter output to the
specified reference voltage. Three distinct inputs to the error
amplifier determine the voltage level of VCOMP. The internal
and external circuitry which control voltage regulation is
illustrated in Figure 5.
FN9084.8
December 29, 2004
ISL6559
Most multi-phase controllers simply have the output voltage
fed back to the inverting input of the error amplifier through a
resistor. The ISL6559 features an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point, resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
amplifier output, VDIFF, is then tied through an external
resistor to the inverting input of the error amplifier.
VID3
VID2
VID1
VID0
DAC
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.300
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
-
1
0
1
0
0
1.050
+
+
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
The ISL6559 features a second non-inverting input to the
error amplifier which allows the user to directly offset the
DAC reference voltage in the positive direction only. The
offset voltage is created by an internal current source which
RC
CC
ISL6559 INTERNAL CIRCUIT
COMP
ERROR AMPLIFIER
FB
+
RFB
IAVG
IOUT
VCOMP
VDROOP
-
REFERENCE
VOLTAGE
VDIFF
VOUT
REMOTE
SENSE
POINTS
GND
1
1
0
1
0
0.900
+
1
1
0
1
1
0.875
-
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown
VSEN
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
OFS
ROFS
1/10
+
VOFS
-
100A
FIGURE 5. OUTPUT-VOLTAGE AND LOAD-LINE
REGULATION
9
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID4
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID0. The DAC decodes the a 5-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 20A pull-up to an internal 2.5V
source for use with open-drain outputs. External pull-up
resistors or active-high output stages can augment the pullup current sources, but a slight accuracy error can occur if
they are pulled above 2.9V. The DAC-selected reference
voltage is connected to the non-inverting input of the error
amplifier.
EXTERNAL CIRCUIT
feeds out the OFS pin into a user selected external resistor
to ground. The resulting voltage across the resistor, VOFS, is
internally divided down by ten to create the offset voltage.
This method of offsetting the DAC voltage is more accurate
than external methods of level-shifting the FB pin.
OFFSET
VOLTAGE
The integrating compensation network shown in Figure 5
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the OFS current source, remotesense and error amplifiers. Intersil specifies the guaranteed
tolerance of the ISL6559 to include all variations in current
FN9084.8
December 29, 2004
ISL6559
sources, amplifiers and the reference so that the output
voltage remains within the specified system tolerance of
± 1% over temperature.
LOAD-LINE REGULATION
Microprocessor load current demands change from near noload to full load often during operation. The resulting sizable
transient current slew rate causes an output voltage spike
since the converter is not able to respond fast enough to the
rapidly changing current demands. The magnitude of the
spike is dictated by the ESR and ESL of the output
capacitors selected. In order to drive the cost of the output
capacitor solution down, one commonly accepted approach
is active voltage positioning. By adding a well controlled
output impedance, the output voltage can effectively be level
shifted in a direction which works against the voltage spike.
The average current of all the active channels, IAVG, flows
out IOUT, see Figure 5. IOUT is connected to FB through a
load-line regulation resistor, RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
V DROOP = I AVG R FB
(EQ. 5)
In most cases, each channel uses the same RISEN value to
sense current. A more complete expression for VDROOP is
derived by combining equations 3 and 4.
I OUT r DS  ON 
- ---------------------- R FB
V DROOP = -----------N
R ISEN
(EQ. 6)
Droop is an optional feature of the ISL6559. If active voltage
positioning is not required, simply leave the IOUT pin open.
DYNAMIC VID
Next generation microprocessors can change VID inputs at
any time while the regulator is in operation. The power
management solution is required to monitor the DAC inputs
and respond to VID voltage transitions or ‘on-the-fly’ VID
changes, in a controlled manner. Supervising the safe output
voltage transition within the DAC range of the processor
without discontinuity or disruption.
The ISL6559 checks the five VID inputs at the beginning of
each channel-1 switching cycle. If the VID code has
changed, the controller waits one complete switching cycle
to validate the new code. If the VID code is stable for this
entire switching cycle, then the controller will begin
executing the output voltage change. The controller begins
incrementing the reference voltage by making 25mV steps
every two switching cycles until it reaches the new VID code.
The total time required for a VID change, tDV, is dependent
on the switching frequency (fS), the size of the change
(VID), and the time before the next switching cycle begins.
Since the ISL6559 recognizes VID-code changes only at the
beginning of switching cycles, up to one full cycle may pass
before a VID change registers. This is followed by a onecycle wait before the output voltage begins to change. The
one-cycle uncertainty in Equation 8 is due to the possibility
that the VID code change may occur up to one full cycle
before being recognized.
1 VID
1 2 VID
-----  2
------------------ – 1 < t DV  -----  ------------------
f S  0.025
f S 0.025
The time required for a converter running with fS = 500kHz
to make a 1.2V to 1.4V reference-voltage change is between
30s and 32s as calculated using Equation 8. This example
is also illustrated in Figure 7.
REFERENCE OFFSET
Typical microprocessor tolerance windows are centered
around a nominal DAC set point. Implementing a load-line
would require offsetting the output voltage above this
nominal DAC set point. Centering the load-line within the
static specification window. The ISL6559 features an internal
100A current source which feeds out the OFS pin. Placing
a resistor from OFS and ground allows the user to set the
amount of positive offset desired directly to the reference
voltage. The voltage developed across the OFS resistor,
ROFS, is divided down internally by a factor of 10 and
directly counters the DAC voltage at the error amplifier noninverting input. Select the resistor value based on the
voltage offset desired, VOFS, using Equation 6.
V OFS  10
R OFS = -------------------------100A
(EQ. 7)
10
(EQ. 8)
01110
00110
VID, 5V/DIV
VID CHANGE OCCURS
ANYWHERE HERE
VREF, 100mV/DIV
1.2V
1.2V
VOUT, 100mV/DIV
5s/DIV
FIGURE 6. DYNAMIC-VID WAVEFORMS FOR 500KHZ
ISL6559 BASED MULTI-PHASE BUCK
CONVERTER
FN9084.8
December 29, 2004
ISL6559
Operation Initialization
Before converter operation is initialized, proper conditions
must exist on the enable and disable inputs. Once these
conditions are met, the controller begins a soft-start interval.
Once the output voltage is within the proper window of
operation, the PGOOD output changes state to update an
external system monitor.
Enable and Disable
The PWM outputs are held in a high-impedance state to
assure the drivers remain off while in shutdown mode. Four
separate input conditions must be met before the ISL6559 is
released from shutdown mode.
First, the bias voltage applied at VCC must reach the internal
power-on reset (POR) circuit rising threshold. Once this
threshold is met, the EN input signal becomes the gate for
soft-start initialization. Hysteresis between the rising and
falling thresholds insures that once enabled, the ISL6559 will
not inadvertently turn off unless the bias voltage drops
substantially. See Electrical Specifications for specifics on
POR rising and falling thresholds.
ISL6559 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
+5V
VCC
OV LATCH
SIGNAL
+
-
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.23V;
FS/DIS must not be grounded; and VID cannot be equal to
11111. Once these conditions are true, the controller
immediately initiates a soft-start sequence.
Soft-Start
The soft-start time, tSS, is determined by an 11-bit counter
that increments with every pulse of the phase clock. For
example, a converter switching at 250kHz per phase has a
soft-start time of
2048
T SS = ------------- = 8.3ms
f SW
(EQ. 9)
During the soft-start interval, the soft-start voltage, VRAMP,
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, IRAMP, is
decreasing from 160A down to zero. These signals are
connected as shown in Figure 8 (IOUT may or may not be
connected to FB depending on the particular application).
+12V
EXTERNAL CIRCUIT
10.7k
ENABLE
COMPARATOR
POR
CIRCUIT
The 11111 VID code is reserved as a signal to the controller
that no load is present. The controller will enter shutdown
mode after receiving this code and will start up upon
receiving any other code. This code is not intended as a
means of enabling the controller when a load is present.
RC
CC
ISL6559 INTERNAL CIRCUIT
COMP
EN
ERROR AMPLIFIER
FB
-
1.40k
1.23V (± 2%)
RFB
REFERENCE
VOLTAGE
IRAMP
VDIFF
FIGURE 7. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
Second, the ISL6559 features an enable input (EN) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6559 in shutdown until the voltage at EN rises above
1.23V. The enable comparator has about 90mV of hysteresis
to prevent bounce. It is important that the driver ICs reach
their POR level before the ISL6559 becomes enabled. The
schematic in Figure 7 demonstrates sequencing the
ISL6559 with the HIP660X family of Intersil MOSFET drivers
which require 12V bias.
Third, the frequency select\disable input (FS/DIS) will
shutdown the converter when pulled to ground. Under this
condition, the internal oscillator is disabled. The oscillator
resumes operation upon release of FS/DIS and a soft-start
sequence is initiated.
11
VCOMP
+
IOUT
VRAMP
IAVG
IDEAL DIODES
FIGURE 8. RAMP CURRENT AND VOLTAGE FOR
REGULATING SOFT-START SLOPE
AND DURATION
The ideal diodes in Figure 8 assure that the controller tries to
regulate its output to the lower of either the reference voltage
or VRAMP. Since IRAMP creates an initial offset across RFB of
(RFB x 160A), the first PWM pulse will not be seen until
VRAMP is greater than the RFB IRAMP offset. This produces a
delay after the ISL6559 enables before the output voltage
starts moving. For example, if VID = 1.5V, RFB = 1k and TSS
= 8.3ms, the delay time can be expressed using Equation 10.
FN9084.8
December 29, 2004
ISL6559
T SS
- = 560s
t DELAY = -------------------------------------------------1.4  VID
1 + ---------------------------------------–
6
R FB 160  10
(EQ. 10)
outlines the interaction between the fault monitors and the
power good signal.
PGOOD
Following the delay, the soft start ramps linearly until VRAMP
reaches VID. For the system described above, this first
linear ramp will continue for approximately
-
+
UV
+
350mV
-
T SS
RAMP1 = ----------- – t DELAY
1.4
(EQ. 11
POR
CIRCUIT
-
90A
OC
+
IAVG
DAC
REFERENCE
= 5.27ms
VDIFF
+
OV
OVP
-
The final portion of the soft-start sequence is the time
remaining after VRAMP reaches VID and before IRAMP gets to
zero. This is also characterized by a slight change in the slope
of the output voltage ramp which, for the current example,
exists for a time of
2.2V
FIGURE 10. POWER GOOD AND PROTECTION CIRCUITRY
Power Good Signal
t RAMP2 = T SS – t RAMP1 – t DELAY
(EQ. 12)
= 2.34ms
This behavior is seen in the example in Figure 9 of a converter
switching at 500kHz. For this converter, RFB is set to 2.67k
leading to TSS = 4.0ms, tDELAY = 700ns, tRAMP1 = 2.23ms,
and tRAMP2 = 1.17ms.
VOUT, 500mV/DIV
The power good pin (PGOOD) is an open-drain logic output
which indicates that the converter is operating properly and
the output voltage is within a set window. The under-voltage
(UV) and over-voltage (OV) comparators create the output
voltage window. The controller also takes advantage of
current feedback to detect output over-current (OC)
conditions. PGOOD pulls low during shutdown and releases
high during soft-start once the output voltage exceeds the
UV threshold. Once high, PGOOD will only transition low
when the controller is disabled or a fault condition is
detected. It will return high under certain circumstances once
a fault clears.
Under-Voltage Protection
EN, 5V/DIV
tDELAY tRAMP1
tRAMP2
1ms/DIV
FIGURE 9. SOFT-START WAVEFORMS FOR ISL6559 BASED
MULTI-PHASE BUCK CONVERTER
NOTE: Switching frequency 500kHz and RFB = 2.67k
Fault Monitoring and Protection
The ISL6559 actively monitors voltage and current feedback
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indication signal is provided for linking
to external system monitors. The schematic in Figure 10
12
The voltage on VDIFF is internally offset by 350mV before it
is compared with the DAC reference voltage. By positively
offsetting the output voltage, an UV threshold is created
which moves relative to the VID code. During soft-start, the
slow rising output voltage eventually exceeds the UV
threshold. Assuming the POR leg of the PGOOD NOR gate
has not detected an OC fault, the PGOOD signal will go
high.
If a fault condition arises during operation and the output
voltage drops below the UV threshold, PGOOD will
immediately pull low, but converter operation will continue.
PGOOD will return high once the output voltage surpasses
the UV threshold.
If the ISL6559 is disabled during operation, the PGOOD
signal will not pull low until the output voltage decays below
the UV threshold.
FN9084.8
December 29, 2004
ISL6559
Over-Voltage Protection
When the output of the differential amplifier (VDIFF) reaches
2.2V, PGOOD immediately goes low indicating a fault. Two
protective actions are taken by the ISL6559 to protect the
microprocessor load.
First, all PWM outputs are commanded low. Directing the
Intersil drivers to turn on the lower MOSFETs; shunting the
output to ground preventing any further increase in output
voltage. The PWM outputs remain low until VDIFF falls to the
programmed DAC level at which time they go into a highimpedance state. The Intersil drivers respond by turning off
both upper and lower MOSFETs. If the over-voltage
condition reoccurs, the ISL6559 will again command the
lower MOSFETs to turn on. The ISL6559 will continue to
protect the load in this fashion as long as the over-voltage
repeats.
Second, the OVP pin pulls to VCC and can deliver 100mA
into the gate of either a MOSFET or SCR placed across the
input voltage (VIN) and VOUT. Turning on the MOSFET or
SCR collapses the power rail and causes a fuse placed
further up stream to blow. The fuse must be sized such that
the MOSFET or SCR will not overheat before the fuse blows.
Once an over-voltage condition is detected, normal PWM
operation ceases and PGOOD remains low until the
ISL6559 is reset. Cycling the voltage on EN below 1.23V or
the bias to VCC below the POR-falling threshold will reset
the controller.
Over-Current Protection
The ISL6559 takes advantage of the proportionality between
the load current and the average current, IAVG, to detect an
over-current condition. See the Channel-Current Balance
section for more detail on how the average current is
created. The average current is continually compared with a
constant 90A reference current. Once the average current
exceeds the reference current, the comparator triggers the
converter to shutdown. The POR circuit places all PWM
signals in a high-impedance state which commands the
drivers to turn off both upper and lower MOSFETs. PGOOD
pulls low and the system remains in this state while the
controller counts 2048 phase clock cycles. This is followed
by a soft-start attempt (see Soft-Start).
OUTPUT CURRENT, 20A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
5ms/DIV
FIGURE 11. OVERCURRENT BEHAVIOR IN HICCUP MODE
During the soft-start interval, the over-current protection
circuitry remains active. As the output voltage ramps up, if
an over-current condition is detected, the ISL6559
immediately places all PWM signals in a high-impedance
state. The ISL6559 repeats the 2048-cycle wait period and
follows with another soft-start attempt, as shown in
Figure 11. This hiccup mode of operation repeats up to
seven times. On the eighth soft-start attempt, the part
latches off. Once latched off, the ISL6559 can only be reset
when the voltage on EN is brought below 1.23V or VCC is
brought below the POR falling threshold. Upon completion of
a successful soft-start attempt, operation will continue as
normal, PGOOD will return high, and the OC latch counter is
reset.
During VID-on-the-fly transitions, the OC comparator output
is blanked. The quality and mix of output capacitors used in
different applications leads to a wide output capacitance
range. Depending upon the magnitude and direction of the
VID change, the change in voltage across the output
capacitors could result in significant current flow. Summing
this instantaneous current with the load current already
present could drive the average current above the reference
current level and cause an OC trip during the transition. By
blanking the OC comparator during the VID-on-the-fly
transition, nuisance tripping is avoided.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
13
FN9084.8
December 29, 2004
ISL6559
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those where each phase handles between 15 and 20A. All
surface-mount designs will tend toward the lower end of this
current range and, if through-hole MOSFETs can be used,
higher per-phase currents are possible. In cases where
board space is the limiting constraint, current can be pushed
as high as 30A per phase, but these designs require heat
sinks and forced air to cool the MOSFETs.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching frequency;
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (rDS(ON)). In Equation 13, IM is the maximum
continuous output current; IPP is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (VOUT/VIN); and
L is the per-channel inductance.
P L = r DS  ON 
I L, 2PP  1 – d 
 I M 2
   1 – d  + ------------------------------------ N
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON); the switching
frequency, fS; and the length of dead times, td1 and td2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
(EQ. 14)
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of PL and PD.
UPPER MOSFET POWER CALCULATION
In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
14
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 15,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
I M I PP  t 1 
P UP,1  V IN  -----  ----  f
 N- + -------2  2 S
(EQ. 15)
The upper MOSFET begins to conduct and this transition
occurs over a time t2. In Equation 16, the approximate power
loss is PUP,2.
 I M I PP  t 2 
P UP, 2  V IN  ----- – ---------  ----  f S
2  2
N
(EQ. 16)
A third component involves the lower MOSFET’s reverserecovery charge, Qrr. Since the inductor current has fully
commutated to the upper MOSFET before the lowerMOSFET’s body diode can draw all of Qrr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is PUP,3 and is approximately
(EQ. 17)
P UP,3 = V IN Q rr f S
(EQ. 13)
12
I

I M I PP
M I PP t
P D = V D  ON  f S  ----- t d1 +  ----- – --------- d2
 N- + -------2 
2
N
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverserecovery charge, Qrr; and the upper MOSFET rDS(ON)
conduction loss.
Finally, the resistive part of the upper MOSFET’s is given in
Equation 18 as PUP,4.
2
 I M
I PP2
P UP,4  r DS  ON   ----- d + ---------12
 N
(EQ. 18)
In this case, of course, rDS(ON) is the on resistance of the
upper MOSFET.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 15, 16, 17 and 18. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process that involves
repetitively solving the loss equations for different MOSFETs
and different switching frequencies until converging upon the
best solution.
Current Sensing
The ISEN pins are denoted ISEN1, ISEN2, ISEN3 and
ISEN4. The resistors connected between these pins and
their respective phase nodes determine the gains in the
load-line regulation loop and the channel-current balance
FN9084.8
December 29, 2004
ISL6559
loop. Select the values for these resistors based on the room
temperature rDS(ON) of the lower MOSFETs; the full-load
operating current, IFL; and the number of phases, N
according to Equation 19 (see also Figure 3).
(EQ. 19)
In certain circumstances, it may be necessary to adjust the
value of one or more of the ISEN resistors. This can arise
when the components of one or more channels are inhibited
from dissipating their heat so that the affected channels run
hotter than desired (see the section entitled Channel-Current
Balance). In these cases, chose new, smaller values of RISEN
for the affected phases. Choose RISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase.
T
R ISEN ,2 = R ISEN ----------2
T 1
(EQ. 20)
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
In Equation 20, make sure that T2 is the desired temperature
rise above the ambient temperature, and T1 is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 20 is usually
sufficient, it may occasionally be necessary to adjust RISEN
two or more times to achieve perfect thermal balance
between all channels.
C2 (OPTIONAL)
RC
Load-Line Regulation Resistor
(EQ. 21)
If one or more of the ISEN resistors was adjusted for thermal
balance, as in Equation 20, the load-line regulation resistor
should be selected according to Equation 22. Where IFL is
the full-load operating current and RISEN(n) is the ISEN
resistor connected to the nth ISEN pin.
V DROOP
R FB = -------------------------------I FL r DS  ON 

n
R ISEN  n 
(EQ. 22)
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
15
COMP
FB
The load-line regulation resistor is labeled RFB in Figure 5.
Its value depends on the desired full-load droop voltage
(VDROOP in Figure 5). If Equation 19 is used to select each
ISEN resistor, the load-line regulation resistor is as shown
in Equation 21.
V DROOP
R FB = -----------------------–6
50 10
CC
+
RFB
ISL6559
r DS  ON  I FL
R ISEN = ---------------------- -------50 10 – 6 N
COMPENSATING LOAD-LINE REGULATED
CONVERTER
IOUT
VDROOP
VDIFF
FIGURE 12. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6559 CIRCUIT
The feedback resistor, RFB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f0. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the perchannel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
FN9084.8
December 29, 2004
ISL6559
each of the three cases which follow, there is a separate set
of equations for the compensation components.
1
------------------- > f 0
2 LC
RC
CC
2f 0 V pp LC
R C = R FB ----------------------------------0.75V
FB
IN
C1
0.75V IN
C C = ----------------------------------2V PP R FB f 0
Case 2:
IOUT
VDIFF
(EQ. 23)
0.75V IN
C C = ----------------------------------------------------------- 2  2 f 02 V PP R FB LC
Case 3:
RFB
R1
1
1
-------------------  f 0 < ----------------------------2C  ESR 
2 LC
V PP  2  2 f 02 LC
R C = R FB -------------------------------------------0.75 V IN
COMP
ISL6559
Case 1:
C2
1
f 0 > -----------------------------2C  ESR 
2 f 0 V pp L
R C = R FB ----------------------------------------0.75 V IN  ESR 
0.75V IN  ESR  C
C C = -----------------------------------------------2V PP R FB f 0 L
In Equations 23, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and VPP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 4 and Electrical Specifications.
Once selected, the compensation values in Equations 23
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equations 23 unless some performance issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 12). Keep
a position available for C2, and be prepared to install a highfrequency capacitor of between 22pF and 150pF in case any
trailing edge jitter problem is noted.
FIGURE 13. COMPENSATION CIRCUIT FOR ISL6559 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 13, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, fHF. This pole can be used for added
noise rejection or to assure adequate attenuation at the erroramplifier high-order pole and zero frequencies. A good general
rule is to chose fHF = 10f0, but it can be higher if desired.
Choosing fHF to be lower than 10f0 can cause problems with
too much phase shift below the system bandwidth.
In the solutions to the compensation equations, there is a single
degree of freedom. For the solutions presented in Equations
24, RFB is selected arbitrarily. The remaining compensation
components are then selected according to Equations 24.
C  ESR 
R 1 = R FB ----------------------------------------LC – C  ESR 
LC – C  ESR 
C 1 = ----------------------------------------R FB
0.75V IN
C 2 = -----------------------------------------------------------------2
 2  f 0 f HF LCR FB V PP
2
V PP  2 f 0 f HF LCR FB
 
R C = -------------------------------------------------------------------2f

0.75 V
 HF LC – 1
IN

0.75V IN 2f
 HF LC – 1
C C = ------------------------------------------------------------------ 2  2 f 0 f HF LCR FB V PP
16
(EQ. 24)
FN9084.8
December 29, 2004
ISL6559
In Equations 24, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and VPP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 4 and Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy during the interval of time after
the beginning of the transient until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response leaving the output capacitor bank
to supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, VMAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total outputvoltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
di
V   ESL  ----- +  ESR  I
dt
(EQ. 25)
The filter capacitor must have sufficiently low ESL and ESR
so that V < VMAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to IC,PP (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
VPP(MAX), determines the lower limit on the inductance.
V – N V

OUT V OUT
 IN
L   ESR  -----------------------------------------------------------f S V IN V PP MAX 
(EQ. 26)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
VMAX. This places an upper limits on inductance.
2NCVO
L  -------------------- V MAX – I  ESR 
 I  2
(EQ. 27)
 1.25  NC
L  -------------------------- V MAX – I  ESR   V IN – V O


 I  2
(EQ. 28)
Equation 28 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 27
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
Input Supply Voltage Selection
The VCC input of the ISL6559 can be connected to either a
+5V supply directly or through a current limiting resistor to a
+12V supply. An integrated 5.8V shunt regulator maintains
the voltage on the VCC pin when a +12V supply is used. A
300 resistor is suggested for limiting the current into the
VCC pin to approximately 20mA.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in MOSFETs, and they establish the upper limit for
the switching frequency. The lower limit is established by the
requirement for fast transient response and small outputvoltage ripple as outlined in Output Filter Design. Choose the
lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT (see the figure Typical
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
17
FN9084.8
December 29, 2004
ISL6559
Application on page 3). Figure 15 and Equation 29 are
provided to assist in the selecting the correct value for RT.
Figures 16 and 17 provide the same input RMS current
information for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as described above.
0.3
10
10
100
1000
SWITCHING FREQUENCY (kHz)
10000
FIGURE 14. RT vs SWITCHING FREQUENCY
R T = 10
(EQ. 29)
11.09 – 1.13 log  f S  
0.3
0.1
0
0.1
IC,PP = 0
IC,PP = 0.5 IO
IC,PP = 0.75 IO
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN / VO)
FIGURE 15. NORMALIZED INPUT-CAPACITOR RMS
CURRENT VS DUTY CYCLE FOR 2-PHASE
CONVERTER
For a two phase design, use Figure 15 to determine the
input-capacitor RMS current requirement given the duty
cycle, maximum sustained output current (IO), and the ratio
of the combined peak-to-peak inductor current (IC,PP) to IO.
18
0.2
0.4
0.6
0.8
1.0
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes.The result from the high
current slew rates produced by the upper MOSFETs turn on
and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitics and maximize suppression.
0.3
0.2
IC,PP = 0.75 IO
FIGURE 16. NORMALIZED INPUT-CAPACITOR RMS
CURRENT VS DUTY CYCLE FOR 3-PHASE
CONVERTER
0.2
0
IC,PP = 0.5 IO
IC,PP = 0.25 IO
DUTY CYCLE (VIN / VO)
The input capacitors are responsible for sourcing the ac
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the ac component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
0
IC,PP = 0
0.2
0
Input Capacitor Selection
INPUT-CAPACITOR CURRENT (IRMS / IO)
INPUT-CAPACITOR CURRENT (IRMS / IO)
100
INPUT-CAPACITOR CURRENT (IRMS / IO)
RT (k)
1000
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25 times greater
than the maximum input voltage.
IC,PP = 0
IC,PP = 0.5 IO
IC,PP = 0.25 IO
IC,PP = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN / VO)
FIGURE 17. NORMALIZED INPUT-CAPACITOR RMS
CURRENT VS DUTY CYCLE FOR 4-PHASE
CONVERTER
FN9084.8
December 29, 2004
ISL6559
MULTIPHASE RMS IMPROVEMENT
Figure 18 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input rms current requirements of a two-phase
converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of IC,PP to IO of 0.5. The
single phase converter would require 17.3 Arms current
capacity while the two-phase converter would only require 10.9
Arms. The advantages become even more pronounced when
output current is increased and additional phases are added to
keep the component cost down relative to the single phase
approach.
INPUT-CAPACITOR CURRENT (IRMS / IO)
0.6
MOSFET drain. Place the bulk input capacitors as close to
the upper MOSFET drains as dictated by the component
size and dimensions. Long distances between input
capacitors and MOSFET drains results in too much trace
inductance and a reduction in capacitor performance. Locate
the output capacitors between the inductors and the load,
while keeping them in close proximity around the
microprocessor socket.
The ISL6559 can be placed off to one side or centered
relative to the individual phase switching components.
Routing of sense lines and PWM signals will guide final
placement. Critical small signal components to place close
to the controller include the ISEN resistors, RT resistor,
feedback resistor, and compensation components.
Bypass capacitors for the ISL6559 and HIP660X driver bias
supplies must be placed next to their respective pins. Stray
trace parasitics will reduce their effectiveness.
0.4
Plane Allocation and Routing
Dedicate one solid layer, usually a middle layer, for a ground
plane. Make all critical component ground connections with
vias to this plane. Dedicate one additional layer for power
planes; breaking the plane up into smaller islands of
common voltage. Use the remaining layers for small signal
wiring.
0.2
IC,PP = 0
IC,PP = 0.5 IO
IC,PP = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN / VO)
FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS
CURRENT VS DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
Route PHASE planes of copper filled polygons on the top
and bottom once the switching component placement is set.
Size the trace width between the driver gate pins and the
MOFET gates to carry 1A of current. When routing
components in the switching path, use short wide traces to
reduce the associated parasitics.
Layout Considerations
The following multi-layer printed circuit board layout strategies
minimize the impact of board parasitics on converter
performance. The following sections highlight some important
practices which should not be overlooked during the layout
process.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they switch large amounts of energy and
tend to generate large amounts of noise. How the switching
components are placed should also take into account power
dissipation. Align the output inductors and MOSFETs such
that space between the components is minimized while
creating the PHASE plane. Place the Intersil HIP660X
drivers as close as possible to the MOSFETs they control to
reduce the parasitics due to trace length between critical
driver input and output signals. If possible, duplicate the
same placement of these components for each phase.
Next, place the input and output capacitors. Position one
high-frequency ceramic input capacitor next to each upper
19
FN9084.8
December 29, 2004
ISL6559
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
INDEX
AREA
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
10.00
-
0.394
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
0.419
1.27 BSC
H

NOTES:
MAX
A1
e

MIN
28
0o
10.65
28
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
20
FN9084.8
December 29, 2004
ISL6559
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
b
0.20 REF
0.18
D
0.30
5,8
5.00 BSC
D1
D2
0.23
9
-
4.75 BSC
2.95
3.10
9
3.25
7,8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
2.95
e
3.10
3.25
7,8
0.50 BSC
-
k
0.25
-
-
-
L
0.30
0.40
0.50
8
L1
-
-
0.15
10
N
32
Nd
2
8
3
Ne
8
8
3
P
-
-
0.60
9

-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN9084.8
December 29, 2004
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