DATASHEET

DATASHEET
Synchronous Buck Pulse-Width Modulator (PWM)
Controller
ISL6535
Features
The ISL6535 is a high performance synchronous controller for
demanding DC/DC converter applications. It provides
overcurrent fault protection and is designed to safely start-up
into prebiased output loads.
• Operates from +12V input
The output voltage of the converter can be precisely regulated
to as low as 0.597V, with a maximum tolerance of ±1% over
the commercial temperature range, and ±1.5% over the
industrial temperature range.
• Excellent output voltage regulation
- 0.597V internal reference
- ±1% over the commercial temperature range
- ±1.5% over the industrial temperature range
• Simple single-loop control design
- Voltage-mode PWM control
The ISL6535 provides simple, single feedback loop, voltage
mode control with fast transient response. It includes a
triangle wave oscillator that is adjustable from below 50kHz to
over 1.5MHz. Full (0% to 100%) PWM duty cycle support is
provided.
• Fast transient response
- High-bandwidth error amplifier
- Full 0% to 100% duty ratio
- Leading and falling edge modulation
The error amplifier features a 15MHz gain bandwidth product
and 6V/µs slew rate, which enables high converter bandwidth
for fast transient performance.
• Small converter size
- Constant frequency operation
- Oscillator programmable from 50kHz to over 1.5MHz
The ISL6535's overcurrent protection monitors the current by
using the rDS(ON) of the upper MOSFET, which eliminates the
need for a current sensing resistor.
• 12V high-speed MOSFET gate drivers
- 2.0A source/3A sink at 12V low-side gate drive
- 1.25A source/2A sink at 12V high-side gate drive
- Drives two N-channel MOSFETs
Pin Configurations
ISL6535 (14 LD SOIC)
TOP VIEW
14 VCC
RT 1
13 PVCC
OCSET 2
SS 3
12 LGATE
• Converter can source and sink current
• Soft-start done and an external reference pin for tracking
applications are available in the QFN package
COMP 4
11 PGND
FB 5
10 BOOT
• Pin compatible with ISL6522
EN 6
9 UGATE
• Supports start-up into prebiased loads
GND 7
8 PHASE
• Pb-free (RoHS compliant)
Applications
SSDONE
OCSET
RT
VCC
ISL6535 (16 LD QFN)
TOP VIEW
16
15
14
13
• Power Supply for some Pentium™, PowerPC™, as well as
graphic CPUs
• High-power 12V input DC/DC regulators
• Low-voltage distributed power supplies
12 PVCC
SS
1
COMP
2
FB
3
10 PGND
EN
4
9
March 3, 2016
FN9255.3
• Overcurrent fault monitor
- High-side MOSFET’s rDS(ON) sensing
- Reduced ~120ns blanking time
11 LGATE
GND
7
8
UGATE
6
PHASE
5
REFIN
PAD
1
BOOT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2007, 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6535
Pin Descriptions
PIN #
SOIC
PIN #
QFN
PIN NAME
DESCRIPTION
1
14
RT
This pin provides oscillator switching frequency adjustment. By placing a resistor (RRT) from
this pin to GND, the switching frequency is set from between 200kHz and 1.5MHz according
Equation 1:
6500
R RT  k   ------------------------------------------------------- – 1.3k
(RRT to GND)
F s  kHz  – 200  kHz 
(EQ. 1)
Alternately ISL6535’s switching frequency can be lowered from 200kHz to 50kHz by
connecting the RT pin with a resistor to VCC according to Equation 2:
55000
R RT  k   ------------------------------------------------------- + 70k
200  kHz  – F s  kHz 
(RRT to VCC)
(EQ. 2)
2
15
OCSET
3
1
SS
4
2
COMP
5
3
FB
6
4
EN
7
6
GND
8
7
PHASE
This pin connects to the source of the high-side MOSFET and the drain of the low-side
MOSFET. This pin represents the return path for the high-side gate driver. During normal
switching, this pin is used for high-side current sensing.
9
8
UGATE
Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper
MOSFET.
10
9
BOOT
This pin provides bias to the upper MOSFET driver. A bootstrap circuit may be used to create
a BOOT voltage suitable to drive a standard N-channel MOSFET.
11
10
PGND
This is the power ground connection. Tie the lower MOSFET source and board ground to this
pin.
12
11
LGATE
Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower
MOSFET.
13
12
PVCC
Provide a 12V ±10% bias supply for the lower gate drive to this pin. This pin should be
bypassed with a capacitor to PGND.
14
13
VCC
Provide a 12V bias supply for the chip to this pin. The pin should be bypassed with a capacitor
to GND.
-
5
REFIN
Upon enable if REFIN is less than 2.2V, the external reference pin is used as the control
reference instead of the internal 0.597V reference. An internal 6µA pull-up to 5V is provided
for disabling this functionality.
-
16
SSDONE
-
PAD
EPAD
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2
The current limit is programmed by connecting this pin with a resistor and capacitor to the
drain of the high-side MOSEFT. A 200µA current source develops a voltage across the
resistor, which is then compared with the voltage developed across the high-side MOSFET. A
blanking period of 120ns is provided for noise immunity.
Connect a capacitor from this pin to ground. This capacitor, along with an internal 30µA
current source, sets the soft-start interval of the converter.
COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting
input of the error amplifier and the COMP pin is the error amplifier output. These pins are
used to compensate the voltage-control feedback loop of the converter.
This pin is a TTL compatible input. Pull this pin below 0.8V to disable the converter. In
shutdown the soft-start pin is discharged and the UGATE and LGATE pins are held low.
Signal ground for the IC. All voltage levels are measured with respect to this pin.
Provides an open-drain signal at the end of soft-start.
The exposed pad is at GND potential, but does not conduct current; the GND and PGND pins
must be used for bias current. The pad should be tied to a GND plane with as many thermal
vias as possible, for optimal thermal performance.
FN9255.3
March 3, 2016
ISL6535
Ordering Information
PART NUMBER
(Notes 4, 5)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6535CBZ (Note 1)
6535CBZ
0 to +70
14 Ld SOIC
M14.15
ISL6535IBZ (Note 1)
6535IBZ
-40 to +85
14 Ld SOIC
M14.15
ISL6535CRZ (Note 2)
65 35CRZ
0 to +70
16 Ld 4x4 QFN
L16.4x4
ISL6535IRZ (Note 3)
65 35IRZ
-40 to +85
16 Ld 4x4 QFN
L16.4x4
1. Add “-T” suffix for 2.5k unit tape and reel option. Please refer to TB347 for details on reel specifications.
2. Add “-T” suffix for 6k unit tape and reel option. Please refer to TB347 for details on reel specifications.
3. Add “-T” suffix for 6k unit or -TK for 1k unit tape and reel options. Please refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see product information page for ISL6535. For more information on MSL, please see tech brief TB363.
Block Diagram
EN
SS
VCC
OCSET
INTERNAL
REGULATOR
6mA
30mA
REFERENCE
VREF = 0.597V
200mA
POWER-ON
RESET (POR)
BOOT
REFIN
(QFN ONLY)
SOFT-START
AND
FAULT LOGIC
SOURCE OCP
UGATE
FB
GATE
CONTROL
LOGIC
EA
PHASE
PWM
PVCC
COMP
OSCILLATOR
GND
LGATE
PGND
SSDONE
(QFN ONLY)
RT
FIGURE 1. BLOCK DIAGRAM
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FN9255.3
March 3, 2016
ISL6535
Simplified Power System Diagram
ROCSET
+12V
+1.2V TO +12VIN
Q1
Cvcc
LOUT
VOUT
ISL6535
COUT
RFS
Q2
CSS
R1
R2
FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM
Typical Application
+12VIN
LIN
RFILTER
CHFIN
CBIN
DBOOT
CF2
CF1
VCC
PVCC
BOOT
ROCSET
OCSET
SSDONE
(QFN ONLY)
COCSET
Q1
UGATE
REFIN
(QFN ONLY)
CBOOT
LOUT
VOUT
PHASE
CHFOUT
Q2
LGATE
EN
CBOUT
PGND
RRT
RT
SS
ISL6535
COMP
CSS
C2
C1
C3
R3
R2
FB
R1
GND
RO
FIGURE 3. TYPICAL APPLICATION
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FN9255.3
March 3, 2016
ISL6535
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VPVCC,VVCC. . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to + 16V
Enable Voltage, VEN . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to + 16V
Soft-start Done Voltage, VSSDONE . . . . . . . . . . . . . . . (GND - 0.3V) to + 16V
Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to + 36V
Phase Voltage, VPHASE . . . . . . . . . . . . . . . . . (VBOOT - 16V) to VBOOT + 0.3V
UGATE Voltage VUGATE . . . . . . . . . . . . . . . . (VPHASE - 0.3V) to VBOOT + 0.3V
LGATE Voltage VLGATE . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to VPVCC + 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 5.0V
ESD Rating
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
SOIC Package (Notes 6, 8) . . . . . . . . . . . . .
80
45
QFN Package (Notes 7, 9) . . . . . . . . . . . . . .
42
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Supply Voltage
VVCC, VPVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10%
Boot to Phase Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . <VPVCC
Ambient Temperature Range
ISL6535C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6535I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379.
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For JC, the “case temp” location is taken at the package top center.
9. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, unless otherwise noted specifications. Boldface limits apply across the
operating temperature range, -40°C to +85°C (ISL6535I), 0°C to +70°C (ISL6535C).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 11)
TYP
MAX
(Note 11)
UNIT
VCC SUPPLY CURRENT
Shutdown Supply VCC
IVCC
SS/EN = 0V
3.5
6.1
8.5
mA
Shutdown Supply VPVCC
IPVCC
SS/EN = 0V
0.30
0.50
0.75
mA
VCC/VPVCC Rising Threshold
6.45
7.10
7.55
V
VCC/VPVCC Hysteresis
170
250
500
mV
OCSET Rising Threshold
0.70
0.73
0.75
V
OCSET Hysteresis
180
200
220
mV
Enable - Rising Threshold
1.40
1.50
1.60
V
Enable - Hysteresis
175
250
325
mV
175
200
220
kHz
POWER-ON RESET
OSCILLATOR
Trim Test Frequency
RRT = OPEN VVCC = 12
Total Variation
8kΩ < RRT to GND < 200kΩ(Note 10)
-
±15
-
%
1.7
1.9
2.15
VP-P
RL = 10kΩ, CL= 100pF (Note 10)
-
88
-
dB
GBWP
RL = 10kΩ, CL= 100pF (Note 10)
-
15
-
MHz
SR
RL = 10kΩ, CL= 100pF (Note 10)
-
6
-
V/µs
VOSC
Ramp Amplitude
RRT = OPEN
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
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FN9255.3
March 3, 2016
ISL6535
Electrical Specifications Recommended Operating Conditions, unless otherwise noted specifications. Boldface limits apply across the
operating temperature range, -40°C to +85°C (ISL6535I), 0°C to +70°C (ISL6535C). (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 11)
TYP
MAX
(Note 11)
UNIT
PROTECTION
OCSET Current
IOCSET
TJ = 0°C to +70°C
180
200
220
µA
OCSET Current
IOCSET
TJ = -40°C to +85°C
176
200
224
µA
-
±10
-
mV
22
30
38
µA
TJ = 0°C to +70°C
0.591
0.597
0.603
V
TJ = -40°C to +85°C
0.588
0.597
0.606
V
TJ = 0°C to +70°C
-1.0
-
1.0
%
TJ = -40°C to +85°C
-1.5
-
1.5
%
-4
-6
-8
µA
2.10
-
3.50
V
-3
-
3
mV
OCSET Measurement Offset
OCPOFFSET
Soft-Start Current
OCSET= 1.5V to 15.4V (Note 10)
ISS
REFERENCE
Reference Voltage
System Accuracy
REFIN Current Source (QFN Only)
REFIN Threshold (QFN Only)
REFIN Offset (QFN Only)
GATE DRIVERS
Upper Drive Source Current
IU_SOURCE
VBOOT - VPHASE = 12V, 3nF Load (Note 10)
-
1.25
-
A
Upper Drive Source Impedance
RU_SOURCE
90mA Source Current
-
2.0
-
Ω
Upper Drive Sink Current
IU_SINK
VBOOT - VPHASE = 12V, 3nF Load (Note 10)
-
2
-
A
Upper Drive Sink Impedance
RU_SINK
90mA Source Current
-
1.3
-
Ω
Lower Drive Source Current
IL_SOURCE
VPVCC = 12V, 3nF Load (Note 10)
-
2
-
A
Lower Drive Source Impedance
RL_SOURCE
90mA Source Current
-
1.3
-
Ω
Lower Drive Sink Current
IL_SINK
VPVCC = 12V, 3nF Load (Note 10)
-
3
-
A
Lower Drive Sink Impedance
RL_SINK
90mA Source Current
-
0.94
-
Ω
ISSDONE = 2mA
-
-
0.30
V
SSDONE (QFN ONLY)
SSDONE Low Output Voltage
NOTE:
10. Limits should be considered typical and are not production tested.
11. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN9255.3
March 3, 2016
ISL6535
Typical Performance Curves
80
60
IPVCC+VCC (mA)
RESISTANCE (k)
70
RRT PULL-UP
TO +12V
1000
100
RRT PULLDOWN
TO GND
10
CGATE = 3300pF
50
CGATE = 1000pF
40
30
20
CGATE = 10pF
10
10k
100k
SWITCHING FREQUENCY (Hz)
1M
0
100
200
300
400
500
600
700
800
900
1k
SWITCHING FREQUENCY (kHz)
FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY
FIGURE 4. RRT RESISTANCE vs FREQUENCY
Functional Description
VEN
Initialization
The ISL6535 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the bias
voltage at the VCC pin and the driver input on the PVCC pin. When
the voltages at VCC and PVCC exceed their rising POR thresholds,
a 30µA current source driving the SS pin is enabled. Upon the SS
pin exceeding 1V, the ISL6535 begins ramping the noninverting
input of the error amplifier from GND to the System Reference.
During initialization the MOSFET drivers, pull UGATE to PHASE
and LGATE to PGND.
VOUT
VSS
Soft-Start
During soft-start, an internal 30µA current source charges the
external capacitor (CSS) on the SS pin up to ~4V. If the ISL6535 is
utilizing the internal reference, then as the SS pin’s voltage
ramps from 1V to 3V, the soft-start function scales the reference
input (positive terminal of error amp) from GND to VREF (0.597V
nominal). If the ISL6535 is utilizing an externally supplied
reference, when the voltage on the SS pin reaches 1V, the
internal reference input (into of the error amp) ramps from GND
to the externally supplied reference at the same rate as the
voltage on the SS pin. Figure 6 shows a typical soft-start interval.
The rise time of the output voltage is, therefore, dependent upon
the value of the soft-start capacitor, CSS. If the internal reference
is used, then the soft-start capacitance value can be calculated
through Equation 3:
30A  t SS
C SS = ---------------------------2V
(EQ. 3)
If an external reference is used, then the soft-start capacitance
can be calculated through Equation 4:
30A  t SS
C SS = ---------------------------V REFEXT
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tSS
FIGURE 6. TYPICAL SOFT-START INTERVAL
Prebiased Load Start-Up
Drivers are held in tri-state (UG pulled to Phase, LG pulled to
PGND) at the beginning of a soft-start cycle until two PWM pulses
are detected. The low-side MOSFET is turned on first to provide
for charging of the bootstrap capacitor. This method of driver
activation provides support for start-up into prebiased loads by
not activating the drivers until the control loop has entered its
linear region, thereby substantially reducing output transients
that would otherwise occur had the drivers been activated at the
beginning of the soft-start cycle.
SSDONE
Soft-start is only available in the 16 Ld QFN packaging option of
the ISL6535. When the soft-start pin reaches 4V, an open drain
signal is provided to support sequencing requirements. The
SSDONE is deasserted by disabling of the part, including pulling
SS low, and by POR and OCP events.
(EQ. 4)
7
FN9255.3
March 3, 2016
ISL6535
Oscillator
The oscillator is a triangular waveform, providing for leading and
falling edge modulation. The peak-to-peak of the ramp
amplitude is set at 1.9V and varies as a function of frequency. At
50kHz the peak-to-peak amplitude is approximately 1.8V while
at 1.5MHz it is approximately 2.2V. In the event the regulator
operates at 100% duty cycle for 64 clock cycles an automatic
boot cap refresh circuit will activate turning on LG for
approximately 1/2 of a clock cycle.
repeatedly tripping overcurrent, the hiccup period can be
approximated by Equation 5:
8V  C SS
t HICCUP = -----------------------30A
(EQ. 5)
The OCP trip point varies mainly due to MOSFET rDS(ON)
variations and layout noise concerns. To avoid overcurrent
tripping in the normal operating load range, find the ROCSET
resistor from the following equations with:
1. The maximum rDS(ON) at the highest junction temperature.
Overcurrent Protection
2. The minimum IOCSET from the specification table.
VSSDONE
Determine the overcurrent trip point greater than the maximum
output continuous current at maximum inductor ripple current.
SIMPLE OCP EQUATION
I OC_SOURCE  r
DS  ON 
R OCSET = ---------------------------------------------------------------200A
VSS
DETAILED OCP EQUATION
IOCP
I
I
+ -----  r
 OC_SOURCE 2  DS  ON 
R OCSET = ---------------------------------------------------------------------------------I HSOC  N U
N U = NUMBER OF HIGH SIDE MOSFETs
ILOAD
tHICCUP
FIGURE 7. TYPICAL OVERCURRENT PROTECTION
The OCP function is enabled with the drivers at start-up. OCP is
implemented via a resistor (ROCSET) and a capacitor (COCSET)
connecting the OCSET pin and the drain of the high-side MOSEFT.
An internal 200µA current source develops a voltage across
ROCSET, which is then compared with the voltage developed
across the high-side MOSFET at turn-on as measured at the
PHASE pin. When the voltage drop across the MOSFET exceeds
the voltage drop across the resistor, a sourcing OCP event occurs.
The COCSET is placed in parallel with ROCSET to smooth the
voltage across ROCSET in the presence of switching noise on the
input bus.
A 120ns blanking period is used to reduce the current sampling
error due to leading-edge switching noise. An additional
simultaneous 120ns low pass filter is used to further reduce
measurement error due to noise.
OCP faults cause the regulator to disable (upper and lower drives
disabled, SSDONE pulled low, soft-start capacitor discharged)
itself for a fixed period of time, after which a normal soft-start
sequence is initiated. If the voltage on the SS pin is already at 4V
and an OCP is detected, a 30mA current sink is immediately
applied to the SS pin. If an OCP is detected during soft-start, the
30µA current sink will not be applied until the voltage on the SS
pin has reached 4V. This current sink discharges the CSS
capacitor in a linear fashion. Once the voltage on the SS pin has
reached approximately 0V, the normal soft-start sequence is
initiated. If the fault is still present on the subsequent restart, the
ISL6535 will repeat this process in a hiccup mode. Figure 7
shows a typical reaction to a repeated overcurrent condition that
places the regulator in a hiccup mode. If the regulator is
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V IN - V OUT V OUT
I = --------------------------------  ---------------f SW  L OUT
V IN
f SW = Regulator Switching Frequency
(EQ. 6)
High Speed MOSFET Gate Driver
The integrated driver has the same drive capability and feature as
the Intersil’s 12V gate driver, ISL6612. The PWM tri-state feature
helps prevent a negative transient on the output voltage when the
output is being shut down. This eliminates the Schottky diode that
is used in some systems for protecting the microprocessor from
reversed output voltage damage. See the ISL6612 datasheet for
specification parameters that are not defined in the current
ISL6535 “Electrical Specifications” table on page 5.
Reference Input
The REFIN pin allows the user to bypass the internal 0.597V
reference with an external reference. If REFIN is NOT above
~2.2V, the external reference pin is used as the control reference
instead of the internal 0.597V reference. When is not using the
external reference option, the REFIN pin should be left floating.
An internal 6µA pull-up keeps this REFIN pin above 2.2V in this
situation.
Internal Reference and System Accuracy
The internal reference is set to 0.597V. The total DC system
accuracy of the system is to be within 1.0% over commercial
temperature range and 1.5% over the industrial temperature
range. System accuracy includes error amplifier offset and
reference error. The use of REFIN may add up to 3mV of offset
error into the system (as the error amplifier offset is trimmed out
via the internal system reference).
FN9255.3
March 3, 2016
ISL6535
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using wide,
short printed circuit traces. The critical components should be
located as close together as possible using ground plane
construction or single point grounding.
A multilayer printed circuit board is recommended. Figure 8
shows the critical components of the converter. Note that
capacitors CIN and COUT could each represent numerous physical
capacitors. Dedicate one solid layer (usually a middle layer of the
PC board) for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another solid
layer as a power plane and break this plane into smaller islands
of common voltage levels. Keep the metal runs from the PHASE
terminals to the output inductor short. The power plane should
support the input power and output power nodes. Use copper
filled polygons on the top and bottom circuit layers for the phase
nodes. Use the remaining printed circuit layers for small signal
wiring.
VCC
Locate the ISL6535 within 2 to 3 inches of the MOSFETs, Q1 and
Q2 (1 inch or less for 500kHz or higher operation). The circuit
traces for the MOSFETs’ gate and source connections from the
ISL6535 must be sized to handle up to 3A peak current.
Minimize any leakage current paths on the SS pin and locate the
capacitor CSS close to the SS pin as the internal current source is
only 30µA. Provide local VCC decoupling between VCC and GND
pins. Locate the capacitor CBOOT as close as practical to the
BOOT pin and the phase node.
C2
C1
R2
COMP
FB
C3
R1
R3
ISL6535
VOUT
FIGURE 9. COMPENSATION CONFIGURATION FOR THE
ISL6535 CIRCUIT
C2
+12V
COMP
R2
CBP_PVCC
C3
R3
C1
-
PVCC
E/A
CBP_VCC
ISL6535
+
FB
R1
VREF
VIN
GND
CIN
UGATE
Q1
BOOT
LOUT
PHASE
VOUT
COUT
LGATE
LOAD
CIN
Q2
PGND
VIN
PWM
CIRCUIT
VOSC
UGATE
SS
GND
VOUT
OSCILLATOR
HALF-BRIDGE
DRIVE
CSS
L
DCR
PHASE
LGATE
KEY
C
ESR
TRACE SIZED FOR 3A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
ISL6535
EXTERNAL CIRCUIT
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
DESIGN
FIGURE 8. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
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9
FN9255.3
March 3, 2016
ISL6535
Compensating the Converter
3. Calculate C2 such that FP1 is placed at FCE.
The ISL6535 Single-phase converter is a voltage-mode controller.
This section highlights the design consideration for a voltage-mode
controller requiring external compensation. To address a broad
range of applications, a type-3 feedback network is
recommended (see Figure 9).
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to provide a
pulse-width modulated wave with an amplitude of VIN at the
PHASE node. The PWM wave is smoothed by the output filter. The
output filter capacitor bank’s equivalent series resistance is
represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of VOUT /VCOMP. This function is dominated by a DC gain
and shaped by the output filter, with a double pole break
frequency at FLC and a zero at FCE . For the purpose of this
analysis, L and DCR represent the output inductance and its
DCR, while C and ESR represents the total output capacitance
and its equivalent series resistance.
1
F LC = --------------------------2  L  C
1
F CE = --------------------------------2  C  ESR
(EQ. 7)
The compensation network consists of the error amplifier
(internal to the ISL6535) and the external R1 to R3, C1 to C3
components. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing frequency
(F0; typically 0.1 to 0.3 of fSW) and adequate phase margin
(better than 45°). Phase margin is the difference between the
closed loop phase at F0dB and 180°. The equations that follow
relate the compensation network’s poles, zeros and gain to the
components (R1 , R2 , R3 , C1 , C2 and C3) in Figures 9 and 10.
Use the following guidelines for locating the poles and zeros of
the compensation network:
1. Select a value for R1 (1kΩ to 10kΩ, typically). Calculate value
for R2 for desired converter bandwidth (F0). If setting the
output voltage to be equal to the reference set voltage, as
shown in Figure 10, the design procedure can be followed as
presented.
V OSC  R 1  F 0
R 2 = ---------------------------------------------D MAX  V IN  F LC
(EQ. 8)
As the ISL6535 supports 100% duty cycle, DMAX equals 1.
The ISL6535 uses a fixed ramp amplitude (VOSC) of 1.9V,
Equation 8 simplifies to Equation 9:
1.9  R 1  F 0
R 2 = ------------------------------V IN  F LC
(EQ. 9)
2. Calculate C1 such that FZ1 is placed at a fraction of the FLC,
at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor in
Equation 10 to the desired number). The higher the quality
factor of the output filter and/or the higher the ratio FCE/FLC,
the lower the FZ1 frequency (to maximize phase boost at FLC).
1
C 1 = ----------------------------------------------2  R 2  0.5  F LC
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(EQ. 10)
10
C1
C 2 = -------------------------------------------------------2  R 2  C 1  F CE – 1
(EQ. 11)
4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such
that FP2 is placed below fSW (typically, 0.3 to 1.0 times fSW).
fSW represents the switching frequency of the regulator.
Change the numerical factor (0.7) below to reflect desired
placement of this pole. Placement of FP2 lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
R1
R 3 = -------------------f SW
----------- – 1
F LC
(EQ. 12)
1
C 3 = ----------------------------------------------2  R 3  0.7  f SW
It is recommended that a mathematical model be used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (GMOD), feedback
compensation (GFB) and closed-loop response (GCL):
D MAX  V IN
1 + s  f   ESR  C
G MOD  f  = -------------------------------  ----------------------------------------------------------------------------------------------------------2
V OSC
1 + s  f    ESR + DCR   C + s  f   L  C
1 + s  f   R2  C1
G FB  f  = ---------------------------------------------------- 
s  f   R1   C1 + C2 
1 + s  f    R1 + R3   C3
----------------------------------------------------------------------------------------------------------------------- C1  C2  

------------------- 1 + s  f   R3  C3    1 + s  f   R2  

 C 1 + C 2 

G CL  f  = G MOD  f   G FB  f 
where s  f  = 2  f  j
(EQ. 13)
COMPENSATION BREAK FREQUENCY EQUATIONS
1
F Z1 = ------------------------------2  R 2  C 1
1
F P1 = --------------------------------------------C1  C2
2  R 2  --------------------C1 + C2
1
F Z2 = ------------------------------------------------2   R 1 + R 3   C 3
1
F P2 = ------------------------------2  R 3  C 3
(EQ. 14)
Figure 11 on page 11 shows an asymptotic plot of the DC/DC
converter’s gain vs frequency. The actual Modulator Gain has a
high gain peak dependent on the quality factor (Q) of the output
filter, which is not shown. Using the previously mentioned
guidelines should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at FP2 against
the capabilities of the error amplifier. The closed loop gain, GCL,
is constructed on the log-log graph of Figure 11 by adding the
modulator gain, GMOD (in dB), to the feedback compensation
gain, GFB (in dB). This is equivalent to multiplying the modulator
transfer function and the compensation transfer function and
then plotting the resulting gain.
FN9255.3
March 3, 2016
ISL6535
FP1
FP2
GAIN
FZ1 FZ2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case capacitor.
Output Inductor Selection
 R 2
20 log  --------
 R 1
D
V
MAX
IN
20 log ---------------------------------V
OSC
0
GFB
LOG
GCL
GMOD
LOG
FLC
FCE
F0
FREQUENCY
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of the
switching frequency, fSW.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the
load transient current. The filtering requirements are a function
of the switching frequency and the ripple current. The load
transient requirements are a function of the slew rate (di/dt) and
the magnitude of the transient load current. These requirements
are generally met with a mix of capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the ESR
(Effective Series Resistance) and voltage rating requirements
rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as close
to the power pins of the load as physically possible. Be careful
not to add inductance in the circuit board wiring that could
cancel the usefulness of these low inductance components.
Consult with the manufacturer of the load on specific decoupling
requirements.
Use only specialized low-ESR capacitors intended for switching
regulator applications for the bulk capacitors. The bulk
capacitor’s ESR will determine the output ripple voltage and the
initial voltage drop after a high slew-rate transient. An aluminum
electrolytic capacitor's ESR value is related to the case size with
lower ESR available in larger case sizes. However, the equivalent
series inductance (ESL) of these capacitors increases with case
size and can reduce the usefulness of the capacitor to high
slew-rate transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure the
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11
The output inductor is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
Equation 15:
V IN - V OUT V OUT
I = --------------------------------  ---------------Fs x L
V IN
VOUT= I x ESR
(EQ. 15)
Increasing the value of inductance reduces the ripple current and
voltage. However, the large inductance values reduce the
converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a load
transient is the time required to change the inductor current. Given
a sufficiently fast control loop design, the ISL6535 will provide
either 0% or 100% duty cycle in response to a load transient. The
response time is the time required to slew the inductor current
from an initial current value to the transient current level. During
this interval the difference between the inductor current and the
transient current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient load is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L O  I TRAN
t RISE = -------------------------------V IN – V OUT
L O  I TRAN
t FALL = ------------------------------V OUT
(EQ. 16)
Where ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application or
removal of load and dependent upon the output voltage setting.
Be sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors for
high frequency decoupling and bulk capacitors to supply the
current needed each time Q1 turns on. Place the small ceramic
capacitors physically close to the MOSFETs and between the
drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable operation,
select a bulk capacitor with voltage and current ratings above the
maximum input voltage and largest RMS current required by the
circuit. The capacitor voltage rating should be at least 1.25x
greater than the maximum input voltage, a voltage rating of 1.5x
greater is a conservative guideline. The RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
FN9255.3
March 3, 2016
ISL6535
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or
equivalent) may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be exercised
with regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. The TPS series available from AVX, and the 593D
series from Sprague are both surge current tested.
+12V
DBOOT
+
ISL6535
VD
BOOT
CBOOT
UGATE
MOSFET Selection/Considerations
PHASE
The ISL6535 requires at least two N-channel power MOSFETs.
These should be selected based upon rDS(ON), gate supply
requirements and thermal management requirements.
PVCC
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design factors.
The power dissipation includes two loss components; conduction
loss and switching loss. At a 300kHz switching frequency, the
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs. These
losses are distributed between the two MOSFETs according to
duty factor (see Equation 17). Only the upper MOSFET exhibits
switching losses, since the schottky rectifier clamps the
switching node before the synchronous rectifier turns on.
PUPPER = IO2 x rDS(ON) x D + 1 Io x VIN x tSW x fSW
2
PLOWER = IO2 x rDS(ON) x (1 - D)
Where: D is the duty cycle = VO / VIN,
tSW is the switching interval, and
fSW is the switching frequency.
(EQ. 17)
Figure 12 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from +12V. The boot capacitor, CBOOT develops
a floating supply voltage referenced to the PHASE pin. This
supply is refreshed each cycle to a voltage of +12V less the boot
diode drop (VD) when the lower MOSFET, Q2 turns on. A MOSFET
can only be used for Q1 if the MOSFETs absolute gate-to-source
voltage rating exceeds the maximum voltage applied to +12V.
For Q2, a logic-level MOSFET can be used if its absolute
gate-to-source voltage rating also exceeds the maximum voltage
applied to +12V.
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12
Q1
NOTE:
VG-S  VCC - VD
+12V
Q2
LGATE
+
D2
NOTE:
VG-S  PVCC
PGND
GND
FIGURE 12. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 13 shows the upper gate drive supplied by a direct
connection to +12V. This option should only be used in converter
systems where the main input voltage is +5 V DC or less. The peak
upper gate-to-source voltage is approximately +12V less the input
supply. For +5V main power and +12V DC for the bias, the
gate-to-source voltage of Q1 is 7V. A logic-level MOSFET is a good
choice for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the maximum
voltage applied to PVCC. This method reduces the number of
required external components, but does not provide for immunity to
phase node ringing during turn on and may result in lower system
efficiency.
These equations assume linear voltage-current transitions and
do not adequately model power loss due the reverse recovery of
the lower MOSFETs body diode. The gate-charge losses are
dissipated by the ISL6535 and don't heat the MOSFETs. However,
large gate-charge increases the switching interval, tSW which
increases the upper MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at high
ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for use with
the ISL6535. However, logic-level gate MOSFETs can be used
under special circumstances. The input voltage, upper gate drive
level, and the MOSFETs absolute gate-to-source voltage rating
determine whether logic-level MOSFETs are appropriate.
+1.2V TO +12V
-
+12V
+5V OR LESS
ISL6535
BOOT
UGATE
PVCC
+
Q1
NOTE:
VG-S  VCC - 5V
+12V
LGATE
PGND
Q2
D2
NOTE:
VG-S  PVCC
GND
FIGURE 13. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor swing
during the dead time between turning off the lower MOSFET and
turning on the upper MOSFET. The diode must be a Schottky type
to prevent the lossy parasitic MOSFET body diode from conducting.
It is acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but efficiency
could slightly decrease as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.
FN9255.3
March 3, 2016
ISL6535
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
March 3, 2016
FN9255.3
Applied Intersil’s new standards throughout datasheet.
Updated QFN Pin Configuration on page 1 by adding the word “PAD”.
Updated “Pin Descriptions” on page 2 by adding EPAD.
Updated Note 1 to include tape and reel units.
Added Notes 2 and 3.
Added the UGATE Voltage and LGATE Voltage information to the “Absolute Maximum Ratings” on page 5.
Added Revision History and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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13
FN9255.3
March 3, 2016
ISL6535
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
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14
FN9255.3
March 3, 2016
ISL6535
Package Outline Drawing
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08
4X 1.95
4.00
12X 0.65
A
B
13
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
1
4.00
12
2 . 10 ± 0 . 15
9
4
0.15
(4X)
5
8
TOP VIEW
0.10 M C A B
+0.15
16X 0 . 60
-0.10
4 0.28 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
1.00 MAX
( 3 . 6 TYP )
(
SEATING PLANE
0.08 C
SIDE VIEW
2 . 10 )
C
BASE PLANE
( 12X 0 . 65 )
( 16X 0 . 28 )
C
0 . 2 REF
5
( 16 X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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15
FN9255.3
March 3, 2016
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