Using the ISL8118 PWM Controller Evaluation Board ® Application Note Introduction The ISL8118 is a single-phase PWM controller for a synchronous buck converter with an integrated MOSFET driver that operates from +3.3V to +20V bias supply voltage. Utilizing voltage-mode operation with input voltage feed-forward compensation, the ISL8118 maintains a constant loop gain, providing optimal transient response for applications with a wide input operating voltage range. The controller features the ability to safely start-up into prebiased output loads and provides protection against overcurrent fault events. Overcurrent protection is implemented using both topside and bottomside MOSFET rDS(ON) sensing, eliminating the need for a current sensing resistor. Dual sensing allows the ISL8118 to detect overcurrent faults at the very low and very high duty cycles that can result from the ISL8118’s wide input range. The ISL8118 evaluation board highlights the operations of the controller in a DC/DC application. ISL8118 Reference Design TABLE 1. ISL8118 EVALUATION BOARD DESIGN PARAMETERS MIN TYP MAX Operating Input Voltage (VIN) 4.5V 12V 20V Optimal Input Voltage (VIN) 9.6V 12V 14.4V Output Voltage (VOUT) 1.8V Output Voltage Ripple 30mV Continuous Load Current 25A Switching Frequency 300kHz In the evaluation board, a 0.68µH inductor with a 1.6mΩ DCR (Vishay’s IHLP5050FD-R68) is employed. This yields approximately 1W conduction loss in the inductor. Output Capacitor Selection The output capacitors are generally selected by the output voltage ripple and load transient response requirements. ESR and capacitor charge are major contributions to the output voltage ripple. Assuming that the total output capacitance is sufficient, then the output voltage ripple is dominated by the ESR, which can be calculated using Equation 2. (EQ. 2) V RIPPLE = ΔI L ⋅ ESR To meet the 30mVP-P output voltage ripple requirement, the effective ESR should be less than 3.5mΩ. The output voltage response to a transient load is contributed from ESL, ESR and the amount of output capacitance. With VIN>>VOUT, the amplitude of the voltage excursions can be approximated using Equation 3: L ⋅ I tran ΔV = ------------------------------------C OUT ⋅ V OUT The following sections illustrate simple design steps and component selections for a converter using the ISL8118. Output Inductor Selection The output inductor is chosen by the desired inductor ripple current, which is typically set to be approximately 35% of the rated output current. The desired output inductor can be calculated using Equation 1: V IN – V OUT V OUT 1 L = -------------------------------- × ---------------- × -----------V IN ΔI F SW (EQ. 1) (EQ. 3) With 0.68µH inductor and 0A to 25A step load, the total output capacitance of 1600µF is required for 150mV output voltage transient. In the evaluation board, five of Sanyo’s 6TPF330M9L are employed. Input Capacitor Selection The input bulk capacitors selection criteria are based on the capacitance and RMS current capability. The RMS current rating requirement for the input capacitor is approximated in Equation 4: I IN ( RMS ) = Design Procedure 14.4 – 1.8 1.8 1 = -------------------------- × ----------- × ---------------------3 0.35 ⋅ 25 14.4 300 ×10 AN1489.0 2 The evaluation board is designed to optimize for the output voltage and current specifications shown in Table 1. PARAMETER June 20, 2009 ΔI 2 I O 2 ( D – D 2 ) + -------- D 12 VO D = ---------VIN (EQ. 4) In this application, the RMS current for the input capacitor is 8.98A; therefore, two of Nippon Chemi-con’s EKZE350ELL561MJ25S are used. Small ceramic capacitors for high frequency decoupling are also required to control the voltage overshoot across the MOSFETs. MOSFET Selection The ISL8118 requires two N-Channel power MOSFETs as the main and the synchronous switches. These should be selected based on rDS(ON), gate supply requirements and thermal management requirements. = 0.6μH 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1489 The total power loss on MOSFET consists of conduction loss and switching loss, as shown in Equation 5: The switching loss in the high-side MOSFET can be approximated using Equation 12: P MOSFET ( TOT ) = P cond + P sw 2 1 1 P TFET ( SW ) = --- ⋅ I O ⋅ V IN ⋅ t tr ⋅ F SW + --- ⋅ 2 ⋅ C OSS ⋅ V IN ⋅ F SW 2 2 (EQ. 5) In this relatively small duty cycle design, the low-side MOSFET conducts current most of the time. To optimize the converter efficiency, select the high-side MOSFET with low gate charge for fast switching transition and low-side MOSFET with low rDS(ON). where ttr is the combined ON and OFF MOSFET transition times. The budget power losses in each high-side and low-side MOSFETs are 1W. P TFET ( TOT ) = 0.765W = 0.34W (EQ. 12) The total power dissipation in high-side MOSFET is shown in Equation 13: (EQ. 13) LOW-SIDE MOSFET SELECTION Overcurrent Protection Setting The low-side MOSFET’s RMS current is approximated in Equation 6: The ISL8118 monitors both the top side MOSFET and bottom side MOSFET for overcurrent events. Dual sensing allows the ISL8118 to detect overcurrent faults at the very low and very high duty cycles that can result from the ISL8118’s wide input range. The OCP function is enabled with the drivers at start-up. 2 1 ⎛ ΔI L ⎞ I L ( RMS ) = I OUT ⋅ 1 – D ⋅ 1 + ------ ⋅ ⎜ -------------⎟ ≈ 23.1A 12 ⎝ I OUT⎠ (EQ. 6) Assuming a target conduction loss of 0.7W in the low-side MOSFET, the total ON-resistance of the low-side MOSFETs must be approximately less than 1.3mΩ. Two of Infineon’s BSC018N04LS are employed in the evaluation board. The conduction loss in the low-side MOSFETs can be calculated using Equation 7:i 2 P BFET ( cond ) = I L ( RMS ) ⋅ r DS ( ON ) = 0.67W (EQ. 7) BFET The switching loss in the low-side MOSFETs is dominated by the loss in body diode, which can be calculated using Equation 8: P diode = I O ⋅ t D ⋅ V F ⋅ F SW = 0.54W (EQ. 8) Where tD is the total dead time in each switching period (~60ns) and VF is the forward voltage drop of MOSFET’s body diode. The total power dissipation in the low-side MOSFETs is calculated using Equation 9: P BFET ( TOT ) = 1.21W (EQ. 9) HIGH-SIDE MOSFET SELECTION For the high-side MOSFET selection, first we assume that the conduction loss and the switching loss contribute evenly to the total power dissipation. The high-side MOSFET’s RMS current is approximated using Equation 10: 2 1 ⎛ ΔI L ⎞ I T ( RMS ) = I OUT ⋅ D ⋅ 1 + ------ ⋅ ⎜ -------------⎟ ≈ 10A 12 ⎝ I OUT⎠ (EQ. 10) Hence, the required ON-resistance of the high-side MOSFET is 5mΩ. Two of Infineon’s BSC059N04LS are selected. The conduction loss in the high-side MOSFET is calculated using Equation 11: 2 P TFET ( cond ) = I T ( RMS ) ⋅ r DS ( ON ) = 0.425W TFET 2 (EQ. 11) BOTTOM SIDE OCP A resistor(RBSOC) and a capacitor(CBSOC) between the BSOC pin and the source of the bottom side MOSFETs set the bottom side source and sinking current limits. A 100μA current source develops a voltage across the resistor which is then compared with the voltage developed across the bottom side MOSFET during the conduction period. A capacitor (CBSOC) of 1000pF or greater should be used in parallel with RBSOC. The OCP trip point varies mainly due to MOSFET rDS(ON) variations and layout noise concerns. To avoid overcurrent tripping in the normal operating load range, find the RBSOC resistor from Equation 14 with: 1. The maximum rDS(ON) at the highest junction temperature 2. The minimum IBSOC from the specifications table in the datasheet Determine the overcurrent trip point greater than the maximum output continuous current at maximum inductor ripple current. Simple Bottom side OCP Equation I OC_SOURCE • r DS ( ON ) BFET R BSOC = --------------------------------------------------------------------------------100μA Detailed OCP Equation ΔI ⎛I + -----⎞ • r ⎝ OC_SOURCE 2 ⎠ DS ( ON ) BFET R BSOC = -------------------------------------------------------------------------------------------------I BSOC • N B (EQ. 14) N B = NUMBER OF BOTTOM-SIDE MOSFETs V IN - V OUT V OUT ΔI = --------------------------------- • ---------------F SW • L OUT V IN AN1489.0 June 20, 2009 Application Note 1489 With two of Infineon’s BSC018N04LS as the bottom-side MOSFETs and RBSOC of 511Ω, the bottom-side overcurrent trip point on the evaluation board has been approximately set to 35A. TOP SIDE OCP A resistor (RTSOC) and a capacitor (CTSOC) between the TSOC pin and the drain of the top side MOSFETs set the top side sourcing current limits. A 100μA current source develops a voltage across the resistor RTSOC which is then compared with the voltage developed across the top side MOSFET while on. A capacitor (CTSOC) of 1000pF or greater should be used in parallel with RTSOC. DS ( ON ) The input voltage can be monitored through the enable pin. Programmable enable’s hysteresis can be achieved with the internal 10μA sink current and an external resistor divider. Setting the ISL8118 to be enabled at an input voltage of 4.2V with 0.5V hysteresis, resistor divider network is expressed in Equation 17: V EN_HYS R up = -------------------------- = 49.9kΩ I EN_HYS (EQ. 17) R UP • V EN_REF R down = ----------------------------------------------------------------------------------------- = 7.15kΩ V EN_RTH – V EN_HYS – V EN_REF Feedback Compensator Simple Bottom Side OCP Equation I OC_SOURCE • r Setting Input UVLO A Type-III network is recommended for compensating the feedback loop. Figure 1 shows Type-III compensation configuration for the ISL8118. TFET R TSOC = -------------------------------------------------------------------------------100μA C2 Detailed OCP Equation ΔI ⎛I + -----⎞ • r ⎝ OC_SOURCE 2 ⎠ DS ( ON ) TFET R TSOC = -------------------------------------------------------------------------------------------------I TSOC • N T (EQ. 15) COMP R2 C3 R3 C1 - N T = NUMBER OF TOP-SIDE MOSFETs R1 FB E/A V IN - V OUT V OUT ΔI = --------------------------------- • ---------------F SW • L OUT V IN + VREF VDIFF With two of Infineon’s BSC059N04LS as the top-side MOSFETs and RTSOC of 1.59kΩ, the top-side overcurrent trip point on the evaluation board has been approximately set to 35A. - RFB VSENSN CSEN VSENSP Voltage Margining VOUT OSCILLATOR When MARGIN is pulled high or low, the positive or negative margining functionality is respectively enabled. When MARGIN is left floating, the function is disabled. Upon positive margining, an internal buffer drives the OFSN pin from VCC to maintain OFSP at 0.591V. The resistor divider, RMARG and ROFSP, causes the voltage at OFSN to be increased. Similarly, upon negative margining, an internal buffer drives the OFSP pin from VCC to maintain OFSN at 0.591V. The resistor divider, RMARG and ROFSN, causes the voltage at OFSP to be increased. In both modes, the voltage difference between OFSP and OFSN is then sensed with an instrumentation amplifier and is converted to the desired margining voltage by a 5:1 ratio. A desired percentage change in the output voltage when using the internal 0.591V reference can be calculated from Equation 16: R MARG V M – POS = 20 × --------------------- = 16.95 R OFS R MARG V M – NEG = 20 × --------------------- = 16.95 R OFS 3 (EQ. 16) ROS + VIN PWM CIRCUIT VOSC TGATE HALF-BRIDGE DRIVE L DCR LX C ESR BGATE ISL8118 EXTERNAL CIRCUIT FIGURE 1. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN With the inductor and output capacitor selected as described in the previous sections, the poles and zero of the power stage can be summarized in Equation 18: 1 F 0 = ------------------------------------- = 4.75kHz 2×π× L×C (EQ. 18) 1 F ESR = ------------------------------------------- = 53.6kHz 2 × π × C × ESR AN1489.0 June 20, 2009 Application Note 1489 1. With a value of 1.07kΩ for RFB, select ROS for the target output voltage of 1.8V using Equation 19: V REF R OS = R FB × ------------------------------------V –V OUT (EQ. 19) REF = 523Ω 2. With the desired feedback loop bandwidth at approximately 50kHz, R2 can be calculated using Equation 20, setting R1 to 2kΩ: : V OSC ⋅ R 1 ⋅ F BW ( R OS + R FB ) R 2 = --------------------------------------------- • ----------------------------------d max ⋅ V IN ⋅ F 0 R OS (EQ. 20) Power and Load Connections Terminals J1 and J2 are connected to the input of the power stage. For single rail supply, the IC bias supply can be tied to the converter input supply through pin 1 and 2 of the Jumper J8. When using separate supplies, provide the IC bias voltage to terminal J6 with pins 2 and pin 3 of J8 connected together. The load can be connected to terminal J3 and J4. TP4 and TP5 can be used for DMM to measure output voltage. The toggle switch, SW1, can be used to enable/disable the controller. Start-up = 10kΩ 3. Select C1 such that FZ1 is located at 3.5kHz: 1 C 1 = -------------------------------------------3 2π ⋅ R 2 ⋅ 3.5 ×10 (EQ. 21) ≈ 4.7nF When the voltages at VCC, PVCC, VFF and EN of ISL8118 exceed their rising POR thresholds, a 38A current source driving the SS pin is enabled. Figure 3 shows the start-up profile of the ISL8118 in relation to the start-up of the 12V input supply and the bias supply.. 4. Select C2 such that FP1 is located at FESR: C1 C 2 = -----------------------------------------------------------2π ⋅ R 2 ⋅ C 1 ⋅ F ESR – 1 VIN = 12V, VOUT = 1.8V, IOUT = 25A (EQ. 22) EN ≈ 270pF 5. Select R3 such that FZ2 is located at FLC and FP2 is located at 150kHz: VOUT R1 R 3 = -------------------------------- ≈ 64.9Ω 3 150 ×10 ---------------------- – 1 F0 (EQ. 23) 1 C 3 = ---------------------------------------------- ≈ 15nF 3 2π ⋅ R 3 ⋅ 150 ×10 A more detailed explanation of designing compensation networks for buck converters with voltage mode control can be found in TB417 entitled “Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators”. SS PGOOD FIGURE 3. SOFT-START Soft-Start with Pre-Biased Output Evaluation Board Performance Figure 2 shows a photograph of the ISL8118EVAL1Z. If the output is pre-biased to a voltage less than the expected value, the ISL8118 will detect that condition. Drivers are held in tri-state (TGATE pulled to LX, BGATE pulled to PGND) at the beginning of a soft-start cycle until the COMP signal exceeds the bottom of the oscillator ramp. The bottom-side MOSFET is turned on first for 200ns to charge the bootstrap capacitor. This method of driver activation provides support for start-up into prebiased loads by not activating the drivers until the control loop has entered its linear region, thereby substantially reducing output transients that would otherwise occur had the drivers been activated at the beginning of the soft-start cycle. FIGURE 2. ISL8118EVAL1Z 4 AN1489.0 June 20, 2009 Application Note 1489 VIN = 12V, VOUT = 1.8V, IOUT = 1A EN VOUT VOUT SS IOUT PGOOD FIGURE 7. TRANSIENT RESPONSE FIGURE 4. SOFT-START WITH PRE-BIASED OUTPUT Output Ripple Figure 5 shows the ripple voltage on the output of the regulator. VOUT VOUT IOUT FIGURE 8. TRANSIENT RESPONSE FIGURE 5. OUTPUT RIPPLE (20MHz BW) Transient Performance Figures 6, 7 and 8 show the response of the output voltage when subjected to transient loading from 0A to 25A at 1A/µs. Efficiency ISL8118 based regulators enable the design of highly efficient systems. The efficiency of the evaluation board using a 12V input supply is shown in Figure 9. 92 90 EFFICIENCY (%) 88 VOUT 86 84 82 80 78 76 IOUT 74 0 5 10 15 20 25 30 OUTPUT CURRENT (A) FIGURE 9. EVALUATION BOARD EFFICIENCY (VOUT = 1.8V) FIGURE 6. TRANSIENT RESPONSE 5 AN1489.0 June 20, 2009 Application Note 1489 Voltage Margining By pulling MARGIN high or low, the positive or negative margining funtionality is respectively enabled. Waveforms are included in Figures 10 and 11. VOUT MARGIN MARGIN VOUT FIGURE 11. MARGINING DOWN References FIGURE 10. MARGINING UP For Intersil documents available on the web, go to http://www.intersil.com/. 1. ISL8118 Data Sheet “3.3V to 20V, Single-Phase PWM Controller with Integrated 2A/4A MOSFET Drivers”, Intersil Corporation 2. Tech Brief TB417 , “Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators”, Intersil Corporation 6 AN1489.0 June 20, 2009 ISL8118EVAL1Z Schematic 1 1 1 TP11 R26 DNP C3 15nF R3 64.9 R27 C2 270pF 2 2 2 C1 4.7nF R1 2K R2 10K C36 1 J1 2 TP6 DNP Vout 1000pF PVIN 1 D1 3.3uF R20 49.9K 2 R21 DNP C22 0.1uF 1 1 TP4 2 2 1 2 1 1 2 1 2 2 1 1 2 1 1 R41 DNP Q5 DNP TP9 Vbias PVCC R40 DNP R38 2.2 5365F D2 R39 DNP C5 DNP 1 VIN 1 1 2 TP16 Q6 BSS123LT1 PGOOD C6 DNP 1 2 1 2 R35 DNP EXDRV 2 1 R16 Enable when Vin=4.2V Disable when Vin=4.0V 2 2 PVIN R43 4.7k C39 DNP 1 2 0 R42 4.7k PVIN C8 100pF 2 1 1 PVCC PVIN 3 3 C35 1uF 2 2 C34 1uF RED R15 DNP C20 0.1uF C40 DNP Vsensn J9 GND 1 1 1 VIN R14 SW1 C30 330uF 3 J8 DNP R33 10k C28 330uF R23 0 TP14 J7 2 C26 DNP C7 DNP J3 OUT C21 0.1uF C19 0.1uF C41 330uF J6 VBIAS GREEN VCC C29 330uF 1 R11 7.15K 2 VCC C27 330uF C24 DNP C4 1000pF 2 2 C32 0.1uF 2 2 1 511 Q4 2 C38 10uF 2 C33 10nF C31 10uF C25 DNP 2 R34 0 Q2 C37 1000pF R19 Vbias 1 1 R9 2.2 C23 DNP 2 15 EXDRV TP10 PVCC 1 0.68uH R18 2.2 BG 1 VIN14 VFF 13 EN 12 PGOOD 11 PGDLY 10 VCC8 R7 11.8K R6 11.8K MARGIN 9 C18 0.22uF 0 R12 16 PVCC 1 C12 1nF 2 R36 DNP 2 2 C11 2.2uF VOUT 2 1 EXDRV TP5 L1 2 PVCC OFSN TP7 1 1 OFSP 7 2 FSET BSOC FB COMP GND TSOC 17 BGATE ISL8118 VCC R8 10K 1 1 TP1 PGND BGATE REFIN Q3 Q1 1 18 PGND VIN R37 DNP LX 6 R13 0 19 LX U1 OFSN R44 0 TP8 TGATE 20 TGATE REFOUT SS Vsens+ J4 GND Application Note 1489 SS 5 OFSP TP3 TP15 R28 0 1 4 VFF REFIN EN PVIN VSENSN PGOOD VCC 21 BOOT C10 0.22uF 2 REFOUT 3 BOOT VSENSP 1 VSENSN2 PGDLY 2 VSENSP1 VDIFF EPAD C9 1nF MARGIN R4 523 R25 DNP J2 TP2 TG 29 VCC C17 DNP 2 0 R22 22 TSOC 23 BSOC 25 COMP 24 FSET 1 26 FB 28 VDIFF 1.07K 27 GND R5 Vsens+ C16 560uF 2 7 C14 3.3uF R24 52.3K TP13 C15 560uF 2 1 BAT54C/SOT 2 DNP 1 C13 1 R17 1.69K TP12 2 R32 0 DNP 1 R29 R30 AN1489.0 June 20, 2009 Application Note 1489 ISL8118EVAL1Z Bill of Materials ID REFERENCE QTY PART NUMBER PART TYPE DESCRIPTION PACKAGE VENDOR 1 U1 1 ISL8118IRZ IC, Linear IC, Single PWM Controller 28 Ld 5x5 MLFP Intersil 2 Q1, Q3 2 BSC059N04LS G MOSFET 40V N-Channel MOSFET TDSON-08 Infineon 3 Q2, Q4 2 BSC018N04LS G MOSFET 40V N-Channel MOSFET TDSON-08 Infineon 4 D1 1 BAT54C Schottky Diode 30V, 200mA Schottky diode SOT23 Onsemi 5 L1 1 IHLP5050FD-R68 Inductor 0.68µH, high current inductor SMD Vishay 6 SW1 1 GT11MSCKE Toggle Switch Switch toggle, SMD, Ultramini, 1P, SPST Mini 7 D2 1 SSL-LXA3025IGCF LED Dual LED RED/GREEN 8 Q6 1 BSS123LT1G MOSFET 100V 0.17A N-Channel MOSFET SOT23 9 Q5 DNP C&K SMD 3x2.5mm LUMEX On Semi CAPACITORS 10 C1 1 Capacitor, Ceramic, X7R 4.7nF, 50V, 10%, ROHS SM_0603 Generic 11 C2 1 Capacitor, Ceramic, X7R 270pF, 50V, 10%, ROHS SM_0603 Generic 12 C3 1 Capacitor, Ceramic, X7R 15nF, 50V, 10%, ROHS SM_0603 Generic 13 C4, C9, C12, C36, C37 5 Capacitor, Ceramic, X5R 1000pF, 50V, 10%, ROHS SM_0603 Generic 14 C8 1 Capacitor, Ceramic, COG 100pF, 50V, 10%, ROHS SM_0603 Generic 15 C10 1 Capacitor, Ceramic, X7R 0.22µF, 25V, 10%, ROHS SM_0603 Generic 16 C11 Capacitor, Ceramic, X5R 2.2µF, 16V, 10%, ROHS SM_0805 Generic 17 C13, C14 1 C3225X7R1H335K 18 C15, C16 2 EKZE350ELL561MJ25S Aluminum Capacitor 19 C18 1 Capacitor, Ceramic, X7R 3.3µF, 50V, 10%, ROHS 560µF, 35V Capacitor, Ceramic, X7R 0.22µF, 50V, 10%, ROHS SM_12105 TDK RAD 10x25 United CHEMI-CON SM_0603 Generic 20 C19-C22, C32 5 C1608X7R1H104K Capacitor, Ceramic, X7R 0.1µF, 50V, 10%, ROHS SM_0603 Generic 21 C27-C30, C41 5 6TPF330M9L POSCAP SMD D3L Sanyo 22 C31, C38 2 Capacitor, Ceramic, X5R 10µF, 16V, 10%, ROHS SM_0805 Generic 23 C33 Capacitor, Ceramic, X7R 0.01µF, 50V, 10%, ROHS SM_0603 Generic 24 C34, C35 Capacitor, Ceramic, X7R 1.0µF, 50V, 10%, ROHS SM_12105 Generic 25 2 330µF, 6.3V, 20%, ROHS DNP C5, C6, C7, C17, C23, C24, C25, C26, C39, C40 RESISTORS 26 R1 1 Resistor, Film 2kΩ, 1%, 1/10W SM_0603 Generic 27 R2 1 Resistor, Film 10kΩ, 1%, 1/10W SM_0603 Generic 28 R3 1 Resistor, Film 64.9Ω, 1%, 1/10W SM_0603 Generic 29 R4 1 Resistor, Film 523Ω, 1%, 1/10W SM_0603 Generic 30 R5 1 Resistor, Film 1.07kΩ, 1%, 1/10W SM_0603 Generic 31 R6, R7 2 Resistor, Film 11.8kΩ, 1%, 1/10W SM_0603 Generic 32 R8, R33 2 Resistor, Film 10kΩ, 1%, 1/10W SM_0603 Generic 33 R9, R18, R38 3 Resistor, Film 2.2Ω, 1%, 1/10W SM_0603 Generic 34 R11 1 Resistor, Film 7.15kΩ, 1%, 1/10W SM_0603 Generic 8 AN1489.0 June 20, 2009 Application Note 1489 ISL8118EVAL1Z Bill of Materials (Continued) ID REFERENCE QTY PART NUMBER PART TYPE DESCRIPTION PACKAGE VENDOR 35 R12, R13, R15, R22, R23, R28, R32, R34, R44 9 Resistor, Film 0Ω, 1/10W SM_0603 Generic 36 R17 1 Resistor, Film 1.69kΩ, 1%, 1/10W SM_0603 Generic 37 R19 1 Resistor, Film 511Ω, 1%, 1/10W SM_0603 Generic 38 R20 1 Resistor, Film 49.9kΩ, 1%, 1/10W SM_0603 Generic 39 R24 1 Resistor, Film 52.3kΩ, 1%, 1/10W SM_0603 Generic 40 R42, R43 2 Resistor, Film 4.7kΩ, 1%, 1/10W SM_0603 Generic 41 R14, R16, R21, DNP R25, R26, R27, R29, R30, R35, R36, R37, R39, R40, R41 SM_0603 OTHERS 42 J1 1 111-0702-001 Blinding Post Conn-Gen, Bind. Post, RED, Thmbnut-Gnd Johnson Components 43 J2, 1 111-0703-001 Blinding Post Conn-Gen, Bind. Post, Black, Thmbnut-Gnd Johnson Components 44 J3, J4 2 KPA8CTP Cable Terminal 14AWG Cable Terminal BERG/FCI 45 J6, J9 2 1514-2 Turrett Post Conn-Turret, Terminal Post, TH, ROHS Keystone 46 J7, J8 2 68000-236HLF 3-pin Jumper BERG/FCI 47 J5 1 68000-236-1x3 3-pin Jumper Berg/FCI 48 TP1-TP6, TP8-TP16 15 5002 Conn-Mini Test Point, Vertical, White, ROHS Keystone 49 TP7 DNP Test Point 9 AN1489.0 June 20, 2009 Application Note 1489 ISL8118EVAL1Z Printed Circuit Board Layers FIGURE 12. TOP SILK SCREEN FIGURE 13. TOP LAYER FIGURE 14. LAYER 2 10 AN1489.0 June 20, 2009 Application Note 1489 ISL8118EVAL1Z Printed Circuit Board Layers (Continued) FIGURE 15. LAYER 3 FIGURE 16. BOTTOM LAYER FIGURE 17. BOTTOM SILKSCREEN Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 11 AN1489.0 June 20, 2009

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