DATASHEET

ISL6431
TM
Data Sheet
June 2001
Advanced Pulse-Width Modulation (PWM)
Controller for Home Gateways
The ISL6431 is a high efficiency, fixed frequency,
synchronous buck PWM controller. It is designed for use in
applications that convert 5V to lower distributed voltages
required for set-top box, cable modem, DSL modem and
residential home gateway core processor, memory and
peripheral power supplies.
This device makes simple work out of implementing a
complete control and protection scheme for a DC-DC
stepdown converter. Designed to drive N-channel MOSFETs
in a synchronous buck topology, the ISL6431 integrates the
control, output adjustment, monitoring and protection
functions into a single 8-pin package.
The ISL6431 provides simple, single feedback loop, voltagemode control with fast transient response. The output
voltage can be precisely regulated to as low as 0.8V, with a
maximum tolerance of ±1.5% over temperature and line
voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 6V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
TEMP. RANGE
(oC)
PACKAGE
PKG.
NO.
ISL6431CB
0 to 70
8 Ld SOIC
M8.15
ISL6431IB
-40 to 85
8 Ld SOIC
M8.15
ISL6431EVAL1
Evaluation Board
Features
• Operates from +5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s rDS(ON)
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Lead SOIC Package
• High Conversion Efficiency
• Synchronous/Standard Buck Configuration
Applications
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Power Supplies for Microprocessors and Embedded
Controllers
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• Low-Voltage Distributed Power Supplies
Pinout
BOOT 1
UGATE 2
GND 3
LGATE 4
1
9018
• 5V-Input DC-DC Regulators
Ordering Information
PART NUMBER
File Number
8 PHASE
7 COMP/OCSET
6 FB
5 VCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL6431
Block Diagram
VCC
POR AND
SOFTSTART
+
SAMPLE
AND
HOLD
-
BOOT
OC
COMPARATOR
UGATE
PHASE
+
-
INHIBIT
PWM
COMPARATOR
ERROR
AMP
+
0.8V
GATE
CONTROL
LOGIC
PWM
+
-
-
VCC
FB
LGATE
COMP/OCSET
20µA
OSCILLATOR
FIXED 300kHz
GND
Typical Application
VCC
C3
C4
C5
DBOOT
VCC
R1
5
1
ISL6431
COMP/OCSET
BOOT
UGATE
C6
2
7
8
R2
LOUT
PHASE
+VO = 0.8 to VIN
C2
6
C1
FB
4
3
LGATE
C7
GND
R3
R4
2
ISL6431
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1)
θJA ( oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Junction Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Recommended Operating Conditions, Unless Otherwise Noted VCC = 5.0V±5% and TA = 25oC
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Nominal Supply
IVCC
ISL6431CB; UGATE and LGATE Open
-
3.2
-
mA
ISL6431IB; UGATE and LGATE Open
2.5
3.2
3.8
mA
ISL6431CB
-
4.30
-
V
ISL6431IB
4.17
4.30
4.50
V
ISL6431CB
-
0.20
-
V
ISL6431IB
0.01
0.20
0.85
V
ISL6431CB; VCC = 5V
-
300
-
kHz
ISL6431IB; VCC = 5V
230
300
340
kHz
ISL6431CB
-
1.5
-
VP-P
ISL6431IB
-
1.5
-
VP-P
ISL6431CB
-
-
1.5
%
POWER-ON RESET
Rising VCC POR Threshold
POR
VCC POR Threshold
Hysteresis
OSCILLATOR
Frequency
fOSC
∆VOSC
Ramp Amplitude
REFERENCE
Reference Voltage Tolerance
Nominal Reference Voltage
VREF
ISL6431IB
-
-
1.5
%
ISL6431CB
-
0.800
-
V
ISL6431IB
-
0.800
-
V
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
GBWP
Slew Rate
SR
ISL6431CB
-
82
-
dB
ISL6431IB
-
82
-
dB
ISL6431CB
14
-
-
MHz
ISL6431IB
14
-
-
MHz
ISL6431CB; COMP = 10pF
-
8.0
-
V/µs
ISL6431IB; COMP = 10pF
4.5
8.0
9.2
V/µs
ISL6431CB; VBOOT - VPHASE = 5V, VUGATE = 4V
-
1.0
-
A
ISL6431IB; VBOOT - VPHASE = 5V, VUGATE = 4V
-
1.0
-
A
ISL6431CB
-
1.0
-
A
GATE DRIVERS
Upper Gate Source Current
IUGATE-SRC
Upper Gate Sink Current
IUGATE-SNK
Lower Gate Source Current
ILGATE-SRC
3
ISL6431IB
-
1.0
-
A
ISL6431CB; VCC = 5V, VLGATE = 4V
-
1.0
-
A
ISL6431IB; VCC = 5V, VLGATE = 4V
-
1.0
-
A
ISL6431
Recommended Operating Conditions, Unless Otherwise Noted VCC = 5.0V±5% and TA = 25oC (Continued)
Electrical Specifications
PARAMETER
Lower Gate Sink Current
SYMBOL
MIN
TYP
MAX
UNITS
ISL6431CB
-
2.0
-
A
ISL6431IB
-
2.0
-
A
IOCSET
ISL6431CB
17
20
22
µA
ISL6431IB
14
20
24
µA
VDISABLE
ISL6431CB
-
-
0.8
V
ISL6431IB
-
-
0.8
V
ILGATE-SNK
TEST CONDITIONS
PROTECTION / DISABLE
OCSET Current Source
Disable Threshold
Functional Pin Descriptions
VCC (Pin 5)
(IOCSET), and the upper MOSFET on-resistance (rDS(ON))
set the converter overcurrent (OC) trip point according to the
following equation:
This is the main bias supply for the ISL6431, as well as the
lower MOSFET’s gate. Connect a well-decoupled 5V supply
to this pin.
IOCSET xR OC SET
I PEAK = ------------------------------------------------r DS ( ON )
FB (Pin 6)
This pin is the inverting input of the internal error amplifier.
Use this pin, in combination with the COMP/OCSET pin, to
compensate the voltage-control feedback loop of the
converter.
GND (Pin 3)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE (Pin 8)
Connect this pin to the upper MOSFET source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection. This pin is also monitored by the
continuously adaptive shoot-through protection circuitry to
determine when the upper MOSFET has turned off.
UGATE (Pin 2)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/OCSET (Pin 7)
This is a multiplexed pin. During a short period of time
following power-on reset (POR), this pin is used to determine
the overcurrent threshold of the converter. Connect a
resistor (R OCSET) from this pin to the drain of the upper
MOSFET (VCC ). ROCSET, an internal 20µA current source
4
Internal circuitry of the ISL6431 will not recognize a voltage
drop across ROCSET larger than 0.5V. Any voltage drop
across ROCSET that is greater than 0.5V will set the
overcurrent trip point to:
0.5V
I PEAK = ---------------------r DS ( ON )
An overcurrent trip cycles the soft-start function.
Pulling OCSET to a level below 0.8V will disable the
controller. Disabling the ISL6431 causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm.
During soft-start, and all the time during normal converter
operation, this pin represents the output of the error
amplifier. Use this pin, in combination with the FB pin, to
compensate the voltage-control feedback loop of the
converter.
LGATE (Pin 4)
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
Functional Descriptions
Initialization
The ISL6431 automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the
Overcurrent Protection (OCP) sampling and hold operation
after the supply voltage exceeds its POR threshold. Upon
ISL6431
completion of the OCP sampling and hold operation, the POR
function initiates the Soft Start operation.
in the normal operating load range, find the R OCSET resistor
from the equation above with:
1. The maximum rDS(ON) at the highest junction temperature.
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s on-resistance, rDS(ON),
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
2. The minimum IOCSET from the specification table.
OUTPUT INDUCTOR
Over Current Protection
( ∆I )
IPEAK > IOUT ( MAX ) + ---------- ,
2
3. Determine IPEAK for
where ∆I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
14A
Soft Start
12A
The POR function initiates the soft start sequence after the
overcurrent set point has been sampled. Soft start clamps the
error amplifier output (COMP pin) and reference input (noninverting terminal of the error amp) to the internally generated
Soft Start voltage. Figure 2 shows a typical soft start interval.
Initially the clamp on the error amplifier (COMP/OCSET pin)
controls the converter’s output voltage. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitor(s). With sufficient output voltage,
the clamp on the reference input controls the output voltage.
When the internally generated Soft Start voltage exceeds the
feedback (FB pin) voltage, the output voltage is in regulation.
This method provides a rapid and controlled output voltage rise.
10A
8A
6A
4A
2A
0A
TIME (50µs/DIV.)
FIGURE 1. OVERCURRENT OPERATION
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor
(ROCSET) programs the overcurrent trip level (see Typical
Application diagram).
Immediately following POR, the ISL6431 initiates the
Overcurrent Protection sampling and hold operation. First,
the internal error amplifier is disabled. This allows an internal
20µA current sink to develop a voltage across ROCSET. The
ISL6431 then samples this voltage at the COMP pin. This
sampled voltage, which is referenced to the VCC pin, is held
internally as the Overcurrent Set Point.
VOUT
500mV/DIV.
0V
When the voltage across the upper MOSFET, which is also
referenced to the VCC pin, exceeds the Overcurrent Set
Point, the overcurrent function initiates a soft-start sequence.
Figure 1 shows this operation with an overload condition. This
current is repeated with a 21ms period. Note that the inductor
current increases to over 14A during the Soft Start interval and
causes an overcurrent trip. The converter dissipates very little
power with this method. The measured input power for the
conditions of Figure 1 is only 0.25W.
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by:
IOCSET x R OCSET
I PEAK = ----------------------------------------------------r DS ( ON )
where IOCSET is the internal OCSET current source (20µA
typical). The OC trip point varies mainly due to the
MOSFET’s rDS(ON) variations. To avoid overcurrent tripping
5
TIME (1ms/DIV.)
FIGURE 2. SOFT START INTERVAL
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
ISL6431
width modulated (PWM) wave with an amplitude of V IN at
the PHASE node. The PWM wave is smoothed by the output
filter (LO and CO).
VIN
ISL6431
Q1
PHASE
CIN
Q2
LGATE
VOUT
CO
VIN
DRIVER
OSC
LO
PWM
COMPARATOR
LO
+
∆ VOSC
LOAD
UGATE
DRIVER
PHASE
VE/A
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 4 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
the COMP/OCSET pin and locate the resistor, ROSCET close
to the COMP/OCSET pin because the internal current source
is only 20µA. Provide local VCC decoupling between VCC and
GND pins. Locate the capacitor, CBOOT as close as practical
to the BOOT and PHASE pins. All components used for
feedback compensation should be located as close to the IC a
practical.
CBOOT
ISL6431
Q1
LO
VOUT
PHASE
VCC
+5V
Q2
CO
COMP/OCSET
CVCC
GND
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse6
ERROR
AMP
REFERENCE
DETAILED COMPENSATION COMPONENTS
ZFB
C2
C1
VOUT
ZIN
C3
R2
R3
R1
COMP
FB
+
ISL6431
REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (LO and CO ), with a double pole
break frequency at F LC and a zero at FESR . The DC Gain of
the modulator is simply the input voltage (VIN ) divided by the
peak-to-peak oscillator voltage ∆VOSC .
Modulator Break Frequency Equations
+VIN
LOAD
ROCSET
+5V
D1
ZIN
+
Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors CIN and CO may each
represent numerous physical capacitors. Locate the ISL6431
within 3 inches of the MOSFETs, Q1 and Q2 . The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6431 must be sized to handle up to 1A peak current.
BOOT
CO
ESR
(PARASITIC)
ZFB
RETURN
VOUT
1
F LC = -----------------------------------------2π x L O x C O
1
F ESR = ------------------------------------------2π x ESR x C O
The compensation network consists of the error amplifier
(internal to the ISL6431) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R 1 , R2 ,
R3 , C1 , C2 , and C 3) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
ISL6431
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
1
F Z1 = -----------------------------------2π x R 2 x C 1
1
FP1 = -------------------------------------------------------- C 1 x C 2
2π x R 2 x  ---------------------- 
 C1 + C2 
1
FP2 = -----------------------------------2π x R 3 x C 3
1
F Z2 = ------------------------------------------------------2π x ( R 1 + R 3 ) x C 3
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Refer to the evaluation board application note (available
soon) for a complete reference design schematic and bill of
materials for a typical Residential Gateway application.
100
FZ1 FZ2
FP1
FP2
80
OPEN LOOP
ERROR AMP GAIN
GAIN (dB)
60
40
20
20LOG
(R2/R1)
0
COMPENSATION
GAIN
CLOSED LOOP
GAIN
-40
FLC
FESR
-60
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
7
High frequency capacitors initially supply the transient and
slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the
ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
∆I =
20LOG
(VIN/DVOSC)
MODULATOR
GAIN
-20
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
VIN - VOUT
Fs x L
x
VOUT
VIN
∆VOUT = ∆I x ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6431 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
ISL6431
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
across the lower MOSFET clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not
adequately model power loss due the reverse-recovery of
the lower MOSFET’s body diode. The gate-charge losses
are dissipated by the ISL6431 and don't heat the
MOSFETs. However, large gate-charge increases the
switching interval, tSW which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within
their maximum junction temperature at high ambient
temperature by calculating the temperature rise according
to package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
1
Io x VIN x tSW x FS
2
Input Capacitor Selection
PUPPER = Io2 x rDS(ON) x D +
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2 .
PLOWER = Io2 x rDS(ON) x (1 - D)
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
Where: D is the duty cycle = VOUT / VIN ,
tSW is the switch ON time, and
FS is the switching frequency.
Given the reduced available gate bias voltage (5V), logiclevel or sub-logic-level transistors have to be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low VGS(ON) characteristics, as the low gate
threshold could be conducive to some shoot-through (due to
the Miller effect), in spite of the counteracting circuitry
present aboard the ISL6431.
+5V
DBOOT
VCC
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6431 requires two N-Channel power MOSFETs for use
in a synchronous buck configuration. These should be selected
based upon rDS(ON), gate supply requirements, and thermal
management requirements.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only
the upper MOSFET has switching losses, since the lower
MOSFETs body diode or an external Schottky rectifier
8
+5V
+ VD BOOT
CBOOT
ISL6431
Q1
UGATE
PHASE
+
LGATE
NOTE:
VG-S ≈ VCC -VD
Q2
NOTE:
VG-S ≈ VCC
GND
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Figure 7 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from VCC. The boot capacitor, CBOOT,
develops a floating supply voltage referenced to the PHASE
pin. The supply is refreshed to a voltage of VCC less the boot
diode drop (VD) each time the lower MOSFET, Q2 , turns on.
ISL6431
ISL6431 DC-DC Converter Application Circuit
Figure 8 shows an application circuit of a DC-DC Converter.
Detailed information on the circuit, including a complete Billof-Materials and circuit board description is available.
+5V
+
CIN
VCC
5
ISL6431
D1
MONITOR
AND
PROTECTION
1
BOOT
2 UGATE
COMP/OCSET 7
REF
8 PHASE
Q1
L1
+
-
VOUT
+
FB
-
6
OSC
U1
4
LGATE
3
GND
FIGURE 8. DC-DC CONVERTER
9
Q2
COUT
+
ISL6431
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
µα
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
A1
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MILLIMETERS
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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