DATASHEET

ISL6431A
®
Data Sheet
October 2002
Advanced Pulse Width Modulation (PWM)
Controller for Broadband Applications
The ISL6431A is a high efficiency, fixed frequency,
synchronous buck PWM controller. It is designed for use in
applications that convert 5V to lower distributed voltages
required for DSL modems, cable and DSL routers and
broadband gateway core processor, memory and peripheral
power supplies.
The ISL6431A makes simple work out of implementing a
complete control and protection scheme for a DC-DC
stepdown converter. Designed to drive N-channel MOSFETs
in a synchronous buck topology, the ISL6431A integrates
the control, output adjustment, monitoring and protection
functions into a single 8-Lead package.
The ISL6431A provides simple, single feedback loop,
voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of ±1.5% over temperature and
line voltage variations. The device is capable of sinking, as
well as sourcing current. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 8V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Ordering Information
PART NUMBER
ISL6431ACB
ISL6431EVAL1
Features
• Operates from +5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s rDS(on)
• Converter Can Source and Sink Current
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8-Lead SOIC Package
Applications
• Cable/DSL Routers and DSL Modems
• DSP and Core Communications Processor Supplies
• Broadband Gateways
• Memory Supplies
• Industrial Power Supplies
• 5V-Input DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Pinout
TEMP. RANGE
(oC)
0 to 70
PACKAGE
8 Ld SOIC
Evaluation Board
PKG.
NO.
M8.15
BOOT 1
UGATE 2
GND 3
LGATE 4
1
FN9088
8 PHASE
7 COMP/OCSET
6 FB
5 VCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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ISL6431A
Block Diagram
VCC
POR AND
SOFTSTART
+
SAMPLE
AND
HOLD
-
BOOT
OC
COMPARATOR
UGATE
+
PWM
COMPARATOR
ERROR
AMP
+
0.8V
-
+
-
-
INHIBIT
PHASE
GATE
CONTROL
LOGIC
PWM
VCC
FB
LGATE
COMP/OCSET
20µA
OSCILLATOR
FIXED 300kHz
GND
Typical Application
VCC
CBULK
CDCPL
CHF
DBOOT
VCC
ROCSET
5
1
ISL6431A
COMP/OCSET
8
RF
CI
6
FB
CBOOT
UGATE
2
7
CF
BOOT
4
3
LOUT
PHASE
LGATE
COUT
GND
ROFFSET
RS
2
+VO
ISL6431A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -40oC to 85oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Recommended Operating Conditions, Unless Otherwise Noted. VCC = 5.0V ±5% and TA = 25oC
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IVCC
2.6
3.2
3.8
mA
POR
4.19
4.30
4.50
V
0.01
0.20
0.85
V
250
300
340
kHz
∆VOSC
-
1.5
-
VP-P
VREF
-
-
1.5
%
-
0.800
-
V
-
82
-
dB
14
-
-
MHz
4.65
8.0
9.2
V/µs
-
-1
-
A
VCC SUPPLY CURRENT
Nominal Supply
POWER-ON RESET
Rising VCC POR Threshold
VCC POR Threshold Hysteresis
OSCILLATOR
Frequency
fOSC
Ramp Amplitude
VCC = 5V
REFERENCE
Reference Voltage Tolerance
Nominal Reference Voltage
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
GBWP
Slew Rate
SR
COMP = 10pF
GATE DRIVERS
Upper Gate Source Current
IUGATE-
VBOOT - VPHASE = 5V, VUGATE = 4V
SRC
Upper Gate Sink Current
IUGATE-SNK
-
1
-
A
Lower Gate Source Current
ILGATE-SRC VVCC = 5V, VLGATE = 4V
-
-1
-
A
Lower Gate Sink Current
ILGATE-SNK
-
2
-
A
IOCSET
17
20
22
µA
VDISABLE
-
-
0.8
V
PROTECTION / DISABLE
OCSET Current Source
Disable Threshold
3
ISL6431A
Functional Pin Description
VCC (Pin 5)
This pin provides the bias supply for the ISL6431A, as well
as the lower MOSFET’s gate. Connect a well-decoupled 5V
supply to this pin.
FB (Pin 6)
This pin is the inverting input of the internal error amplifier.
Use this pin, in combination with the COMP/OCSET pin, to
compensate the voltage-control feedback loop of the
converter.
During soft-start, and all the time during normal converter
operation, this pin represents the output of the error
amplifier. Use this pin, in combination with the
COMP/OCSET pin, to compensate the voltage-control
feedback loop of the converter.
Pulling COMP/OCSET to a level below 0.8V disables the
controller. Disabling the ISL6431A causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm.
LGATE (Pin 4)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the lower
MOSFET has turned off.
PHASE (Pin 8)
Functional Description
GND (Pin 3)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
UGATE (Pin 2)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper
MOSFET has turned off.
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/OCSET (Pin 7)
This is a multiplexed pin. During a short period of time
following power-on reset (POR), this pin is used to determine
the overcurrent threshold of the converter. Connect a
resistor (ROCSET) from this pin to the drain of the upper
MOSFET (VCC). ROCSET, an internal 20µA current source
(IOCSET), and the upper MOSFET on-resistance (rDS(ON))
set the converter overcurrent (OC) trip point according to the
following equation:
I OCSET xR OCSET
I PEAK = ------------------------------------------------r DS ( ON )
Internal circuitry of the ISL6431A will not recognize a voltage
drop across ROCSET larger than 0.5V. Any voltage drop
across ROCSET that is greater than 0.5V will set the
overcurrent trip point to:
0.5V
I PEAK = ---------------------r DS ( ON )
An overcurrent trip cycles the soft-start function.
4
Initialization
The ISL6431A automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the
Overcurrent Protection (OCP) sampling and hold operation
after the supply voltage exceeds its POR threshold. Upon
completion of the OCP sampling and hold operation, the POR
function initiates the Soft Start operation.
Over Current Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s on-resistance, rDS(ON),
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the overcurrent trip level (see Typical Application
diagram).
Immediately following POR, the ISL6431A initiates the
Overcurrent Protection sampling and hold operation. First,
the internal error amplifier is disabled. This allows an internal
20µA current sink to develop a voltage across ROCSET . The
ISL6431A then samples this voltage at the COMP pin. This
sampled voltage, which is referenced to the VCC pin, is held
internally as the Overcurrent Set Point.
When the voltage across the upper MOSFET, which is also
referenced to the VCC pin, exceeds the Overcurrent Set
Point, the overcurrent function initiates a soft-start sequence.
Figure 1 shows the inductor current after a fault is introduced
while running at 15A. The continuous fault causes the
ISL6431A to go into a hiccup mode with a typical period of
25ms. The inductor current increases to 18A during the Soft
Start interval and causes an overcurrent trip. The converter
dissipates very little power with this method. The measured
input power for the conditions of Figure 1 is only 1.5W.
ISL6431A
method provides a rapid and controlled output voltage rise. The
entire startup sequence typically take about 11ms.
OUTPUT INDUCTOR
CURRENT
5A/DIV.
VOUT
500mV/DIV.
COMP/OCSET
1V/DIV.
TIME (5ms/DIV.)
FIGURE 1. OVERCURRENT OPERATION
TIME (2ms/DIV.)
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by:
I OCSET x R OCSET
I PEAK = ---------------------------------------------------r DS ( ON )
FIGURE 2. SOFT START INTERVAL
Current Sinking
where IOCSET is the internal OCSET current source (20µA
typical). The OC trip point varies mainly due to the
MOSFET’s rDS(ON) variations. To avoid overcurrent tripping
in the normal operating load range, find the ROCSET resistor
from the equation above with:
1. The maximum rDS(ON) at the highest junction
temperature.
2. The minimum IOCSET from the specification table.
( ∆I )
3. Determine IPEAK for I PEAK > I OUT ( MAX ) + ---------- ,
2
where ∆I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
Soft Start
The POR function initiates the soft start sequence after the
overcurrent set point has been sampled. Soft start clamps the
error amplifier output (COMP pin) and reference input (noninverting terminal of the error amp) to the internally generated
Soft Start voltage. Figure 2 shows a typical start up interval
where the COMP/OCSET pin has been released from a
grounded (system shutdown) state. Initially, the COMP/OCSET
is used to sample the overcurrent setpoint by disabling the error
amplifier and drawing 20µA through ROCSET. Once the
overcurrent level has been sampled, the soft start function is
initiated. The clamp on the error amplifier (COMP/OCSET pin)
initially controls the converter’s output voltage during soft start.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). When the
internally generated Soft Start voltage exceeds the feedback
(FB pin) voltage, the output voltage is in regulation. This
5
The ISL6431A incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6431A when it is known
that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating it’s input voltage. This
means that the converter is boosting current into the VCC
rail, which supplies the bias voltage to the ISL6431A. If there
is nowhere for this current to go, such as to other distributed
loads on the VCC rail, through a voltage limiting protection
device, or other methods, the capacitance on the VCC bus
will absorb the current. This situation will allow voltage level
of the VCC rail to increase. If the voltage level of the rail is
boosted to a level that exceeds the maximum voltage rating
of the ISL6431A, then the IC will experience an irreversible
failure and the converter will no longer be operational.
Ensuring that there is a path for the current to follow other
than the capacitance on the rail will prevent this failure
mode.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
ISL6431A
pulse-width modulated (PWM) wave with an amplitude of
VIN at the PHASE node. The PWM wave is smoothed by the
output filter (LO and CO).
VIN
ISL6431A
Q1
PHASE
PWM
COMPARATOR
VOUT
CIN
Q2
LGATE
CO
VIN
DRIVER
OSC
LO
LO
-
∆VOSC
LOAD
UGATE
DRIVER
+
PHASE
CO
ESR
(PARASITIC)
ZFB
RETURN
VOUT
VE/A
ZIN
-
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
+
Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors CIN and CO may each
represent numerous physical capacitors. Locate the ISL6431A
within 3 inches of the MOSFETs, Q1 and Q2 . The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6431A must be sized to handle up to 1A peak current.
ERROR
AMP
REFERENCE
DETAILED COMPENSATION COMPONENTS
ZFB
C2
C1
VOUT
ZIN
C3
R2
R3
R1
COMP
FB
+
Figure 4 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/OCSET pin and locate the
resistor, ROSCET close to the COMP/OCSET pin because
the internal current source is only 20µA. Provide local VCC
decoupling between VCC and GND pins. Locate the
capacitor, CBOOT as close as practical to the BOOT and
PHASE pins. All components used for feedback
compensation should be located as close to the IC a
practical.
CBOOT
ISL6431A
Q1
LO
VOUT
PHASE
VCC
+5V
Q2
CO
LOAD
ROCSET
+5V
D1
COMP/OCSET
CVCC
GND
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a
6
REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR . The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ∆VOSC .
Modulator Break Frequency Equations
+VIN
BOOT
ISL6431A
1
F LC = ------------------------------------------2π x L O x C O
1
F ESR = -------------------------------------------2π x ESR x C O
The compensation network consists of the error amplifier
(internal to the ISL6431A) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1 , R2 ,
R3 , C1 , C2 , and C3) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
ISL6431A
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
1
F Z1 = -----------------------------------2π x R 2 x C 1
1
F P1 = -------------------------------------------------------- C 1 x C 2
2π x R 2 x  ----------------------
 C1 + C2
1
F Z2 = ------------------------------------------------------2π x ( R 1 + R 3 ) x C 3
1
F P2 = -----------------------------------2π x R 3 x C 3
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
FZ1 FZ2
FP1
FP2
80
OPEN LOOP
ERROR AMP GAIN
GAIN (dB)
60
40
20
20LOG
(R2/R1)
0
20LOG
(VIN/DVOSC)
MODULATOR
GAIN
-20
CLOSED LOOP
GAIN
FLC
-60
10
100
1K
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
7
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
∆I =
COMPENSATION
GAIN
-40
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
VIN - VOUT
Fs x L
x
VOUT
VIN
∆VOUT = ∆I x ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6431A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
ISL6431A
equations give the approximate response time interval for
application and removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2 .
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
equations below). These equations assume linear voltagecurrent transitions and do not adequately model power loss
due the reverse-recovery of the upper and lower MOSFET’s
body diode. The gate-charge losses are dissipated by the
ISL6431A and don't heat the MOSFETs. However, large gatecharge increases the switching interval, tSW which increases
the MOSFET switching losses. Ensure that both MOSFETs
are within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Losses while Sourcing Current
2
1
P UPPER = Io × r DS ( ON ) × D + --- ⋅ Io × V IN × t SW × F S
2
PLOWER = Io2 x rDS(ON) x (1 - D)
Losses while Sinking Current
PUPPER = Io2 x rDS(ON) x D
2
1
P LOWER = Io × r DS ( ON ) × ( 1 – D ) + --- ⋅ Io × V IN × t SW × F S
2
Where: D is the duty cycle = VOUT / VIN ,
tSW is the combined switch ON and OFF time, and
FS is the switching frequency.
Given the reduced available gate bias voltage (5V),
logic-level or sub-logic-level transistors should be used for
both N-MOSFETs. Caution should be exercised with devices
exhibiting very low VGS(ON) characteristics. The shootthrough protection present aboard the ISL6431A may be
circumvented by these MOSFETs if they have large parasitic
impedences and/or capacitances that would inhibit the gate
of the MOSFET from being discharged below it’s threshold
level before the complementary MOSFET is turned on.
+5V
DBOOT
VCC
MOSFET Selection/Considerations
BOOT
8
CBOOT
ISL6431A
The ISL6431A requires 2 N-Channel power MOSFETs. These
should be selected based upon rDS(ON) , gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching
losses when the converter is sinking current (see the
+5V
+ VD -
UGATE
Q1
PHASE
-
+
LGATE
NOTE:
VG-S ≈ VCC -VD
Q2
NOTE:
VG-S ≈ VCC
GND
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Figure 7 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from VCC . The boot capacitor, CBOOT ,
develops a floating supply voltage referenced to the PHASE
pin. The supply is refreshed to a voltage of VCC less the boot
diode drop (VD) each time the lower MOSFET, Q2 , turns on.
ISL6431A
ISL6431A DC-DC Converter Application Circuit
Figure 8 shows an application circuit of a DC-DC Converter.
Detailed information on the circuit, including a complete Bill-
of-Materials and circuit board description, can be found in
Application Note AN9975.
+5V
+
CIN
2 x 330µF
0.1µF
2 x 1µF
VCC
5
ISL6431A
6.19kΩ
D1
MONITOR
AND
PROTECTION
1
2 UGATE
COMP/OCSET 7
REF
8 PHASE
10.0kΩ
0.1µF
Q1
L1
+
470pF
-
8200pF
4
+
-
FB 6
OSC
1.00kΩ
BOOT
U1
VOUT
LGATE
Q2
3
+
COUT
3 x 330µF
0.1µF
GND
3.16kΩ
60.4Ω
18000pF
Component Selection Notes:
CIN - Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent.
COUT - Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent.
D1 - 30mA Schottky Diode, MA732 or Equivalent
L1 - 3.1µH Inductor, Panasonic P/N ETQ-P6F2ROLFA or Equivalent.
Q1 , Q2 - Intersil MOSFET; HUF76143.
FIGURE 8. 5V to 3.3V 15A DC-DC CONVERTER
9
ISL6431A
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µα
e
A1
B
0.25(0.010) M
C
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
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