DATASHEET

SIGNS
NEW DE
R
O
F
D
NT
NDE
L ACEM E
C OM M E
P
E
E
R
R
T
D
O
E
r at
N
D
OMMEN
ort Cente sc
p2007
p
u
S
l
NO REC
April
3,
a
/t
m
nic
tersil.co
our Tech
contact ERSIL or www.in
T
1-888-IN
Data Sheet
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
ISL6520
FN9009.6
Features
• Operates from +5V Input
The ISL6520 makes simple work out of implementing a
complete control and protection scheme for a DC/DC
stepdown converter. Designed to drive N-Channel
MOSFETs in a synchronous buck topology, the ISL6520
integrates the control, output adjustment, monitoring and
protection functions into a single 8 Lead package.
The ISL6520 provides simple, single feedback loop, voltagemode control with fast transient response. The output
voltage can be precisely regulated to as low as 0.8V, with a
maximum tolerance of 1.5% over-temperature and line
voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Over-Current Protection
- Uses Upper MOSFET’s rDS(on)
The error amplifier features a 15MHz gain-bandwidth
product and 8V/s slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Ld SOIC or 16Ld 4mmx4mm QFN
Protection from over-current conditions is provided by
monitoring the rDS(ON) of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Ordering Information
• Pb-Free Plus Anneal Available (RoHS Compliant)
PART
NUMBER
ISL6520CB*
PART
TEMP.
MARKING RANGE (°C)
6520CB
ISL6520CBZ* 6520 CBZ
(Note)
PACKAGE
PKG.
DWG. #
0 to 70
8 Ld SOIC
M8.15
0 to 70
8 Ld SOIC
(Pb-free)
M8.15
ISL6520IB*
6520IB
-40 to 85
8 Ld SOIC
M8.15
ISL6520IBZ*
(Note)
6520 IBZ
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
ISL6520CR*
ISL
6520CR
0 to 70
16 Ld 4x4mm QFN L16.4x4
0 to 70
16 Ld 4x4mm QFN L16.4x4
(Pb-free)
ISL6520CRZ* 65 20CRZ
(Note)
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
ISL6520IR*
ISL 6520IR
-40 to 85
16 Ld 4x4mm QFN L16.4x4
• Personal Computer Peripherals
ISL6520IRZ*
(Note)
65 20IRZ
-40 to 85
16 Ld 4x4mm QFN L16.4x4
(Pb-free)
• Industrial Power Supplies
ISL6520EVAL1
• 5V-Input DC/DC Regulators
Evaluation Board
* Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
• Low-Voltage Distributed Power Supplies
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2003, 2005, 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6520
Pinouts
16 15 14 13
6 FB
GND 3
BOOT 1
5 VCC
LGATE 4
NC
7 COMP/SD
PHASE
NC
8 PHASE
BOOT 1
UGATE 2
NC
ISL6520
(16 LD QFN)
TOP VIEW
ISL6520
(8 LD SOIC)
TOP VIEW
12 NC
UGATE 2
11 COMP/OCSET
GND
GND 3
10 NC
NC 4
6
7
8
LGATE
NC
VCC
NC
9 FB
5
Block Diagram
VCC
POR AND
SOFTSTART
+
-
SAMPLE
AND
HOLD
BOOT
OC
COMPARATOR
UGATE
+
0.8V
PWM
COMPARATOR
ERROR
AMP
+
-
-
INHIBIT
PHASE
GATE
CONTROL
PWM LOGIC
+
-
VCC
FB
LGATE
COMP/OCSET
20A
OSCILLATOR
FIXED 300kHz
GND
Typical Application
VCC
CBULK
CDCPL
VCC
ROCSET
5
COMP/OCSET
1
ISL6520
2
7
8
RF
CI
CF
CHF
DBOOT
6
FB
4
3
BOOT
CBOOT
UGATE
LOUT
PHASE
LGATE
+VO
COUT
GND
ROFFSET
RS
2
FN9009.6
April 3, 2007
ISL6520
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . 7.0V (DC)
8.0V (<10ns Pulse Width, 10J)
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range - ISL6520C . . . . . . . . . . 0°C to +70°C
Ambient Temperature Range - ISL6520I . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
JA (°C/W)
JC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . . .
95
N/A
QFN Package (Notes 2, 3). . . . . . . . . . . . .
45
7
Maximum Junction Temperature
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . -65°C to +150°C
Maximum Lead Temperature
(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
2.6
3.2
3.8
mA
4.19
4.30
4.5
V
-
0.25
-
V
ISL6520C, VCC = 5V
250
300
340
kHz
ISL6520I, VCC = 5V
230
300
340
kHz
-
1.5
-
VP-P
ISL6520C
-1.5
-
+1.5
%
ISL6520I
-2.5
VCC SUPPLY CURRENT
Nominal Supply
IVCC
UGATE and LGATE Open
POWER-ON RESET
Rising VCC POR Threshold
POR
VCC POR Threshold Hysteresis
OSCILLATOR
Frequency
fOSC
VOSC
Ramp Amplitude
REFERENCE
Reference Voltage Tolerance
+2.5
%
-
0.800
-
V
-
88
-
dB
GBWP
-
15
-
MHz
SR
-
8
-
V/s
Upper Gate Source Current
IUGATE-SRC
-
-1
-
A
Upper Gate Sink Current
IUGATE-SNK
-
1
-
A
Lower Gate Source Current
ILGATE-SRC
-
-1
-
A
Lower Gate Sink Current
ILGATE-SNK
-
2
-
A
ISL6520C
17
20
22
A
ISL6520I
14
20
24
A
-
0.8
-
V
Nominal Reference Voltage
VREF
ERROR AMPLIFIER
DC Gain
Guaranteed By Design
Gain-Bandwidth Product
Slew Rate
GATE DRIVERS
PROTECTION / DISABLE
OCSET Current Source
IOCSET
Disable Threshold
VDISABLE
3
FN9009.6
April 3, 2007
ISL6520
Functional Pin Description
An over-current trip cycles the soft-start function.
VCC
During soft-start, and all the time during normal converter
operation, this pin represents the output of the error amplifier.
Use this pin, in combination with the FB pin, to compensate the
voltage-control feedback loop of the converter.
This is the main bias supply for the ISL6520, as well as the
lower MOSFET’s gate. Connect a well-decoupled 5V supply
to this pin.
FB
This pin is the inverting input of the internal error amplifier. Use
this pin, in combination with the COMP/OCSET pin, to
compensate the voltage-control feedback loop of the converter.
Pulling OCSET to a level below 0.8V will disable the
controller. Disabling the ISL6520 causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm.
LGATE
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET source. This pin is
used to monitor the voltage drop across the upper MOSFET
for over-current protection. This pin is also monitored by the
continuously adaptive shoot-through protection circuitry to
determine when the upper MOSFET has turned off.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/OCSET
This is a multiplexed pin. During a short period of time following
power-on reset (POR), this pin is used to determine the overcurrent threshold of the converter. Connect a resistor (ROCSET)
from this pin to the drain of the upper MOSFET (VCC).
ROCSET, an internal 20A current source (IOCSET), and the
upper MOSFET on-resistance (rDS(ON)) set the converter overcurrent (OC) trip point according to the following equation:
I OCSET xR OCSET
I PEAK = -----------------------------------------------r DS  ON 
(EQ. 1)
Internal circuitry of the ISL6520 will not recognize a voltage
drop across ROCSET larger than 0.5V. Any voltage drop
across ROCSET that is greater than 0.5V will set the
overcurrent trip point to:
0.5V
I PEAK = ---------------------r DS  ON 
(EQ. 2)
4
Connect this pin to the lower MOSFET’s gate. This pin provides
the PWM-controlled gate drive for the lower MOSFET. This pin
is also monitored by the adaptive shoot-through protection
circuitry to determine when the lower MOSFET has turned off.
Do not insert any circuitry between this pin and the gate of the
lower MOSFET, as it may interfere with the internal adaptive
shoot-through protection circuitry and render it ineffective.
Functional Description
Initialization
The ISL6520 automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the
Over-Current Protection (OCP) sampling and hold operation
after the supply voltage exceeds its POR threshold. Upon
completion of the OCP sampling and hold operation, the POR
function initiates the Soft Start operation.
Over Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
rDS(ON), to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor
(ROCSET) programs the over-current trip level (see See
“Typical Application” on page 2.).
Immediately following POR, the ISL6520 initiates the OverCurrent Protection sampling and hold operation. First, the
internal error amplifier is disabled. This allows an internal
20A current sink to develop a voltage across ROCSET. The
ISL6520 then samples this voltage at the COMP pin. This
sampled voltage, which is referenced to the VCC pin, is held
internally as the Over-Current Set Point.
When the voltage across the upper MOSFET, which is also
referenced to the VCC pin, exceeds the Over-Current Set
Point, the over-current function initiates a soft-start sequence.
Figure 1 shows the inductor current after a fault is introduced
while running at 15A. The continuous fault causes the
ISL6520 to go into a hiccup mode with a typical period of
25ms. The inductor current increases to 18A during the Soft
FN9009.6
April 3, 2007
ISL6520
Start interval and causes an over-current trip. The converter
dissipates very little power with this method. The measured
input power for the conditions of Figure 1 is only 1.5W.
(FB pin) voltage, the output voltage is in regulation. This
method provides a rapid and controlled output voltage rise. The
entire startup sequence typically take about 11ms.
OUTPUT INDUCTOR
CURRENT
VOUT
5A/DIV.
500mV/DIV.
COMP/OCSET
1V/DIV.
TIME (5ms/DIV.)
TIME (2ms/DIV.)
FIGURE 1. OVERCURRENT OPERATION
FIGURE 2. START UP SEQUENCE
The over-current function will trip at a peak inductor current
(IPEAK) determined by:
I OCSET x R OCSET
I PEAK = ---------------------------------------------------r DS  ON 
Layout Considerations
1. The maximum rDS(ON) at the highest junction
temperature.
2. The minimum IOCSET from the specification table.
 I 
I PEAK > I OUT  MAX  + ---------- ,
2
whereI is the output inductor ripple current.
For an equation for the ripple current, see“Output Inductor
Selection” on page 7.
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
VIN
ISL6520
UGATE
Q1
PHASE
LGATE
Q2
Soft-Start
The POR function initiates the soft-start sequence after the
overcurrent set point has been sampled. Soft-start clamps the
error amplifier output (COMP pin) and reference input (noninverting terminal of the error amp) to the internally generated
Soft-Start voltage. Figure 2 shows a typical start up interval
where the COMP/OCSET pin has been released from a
grounded (system shutdown) state. Initially, the COMP/OCSET
is used to sample the oversurrent setpoint by disabling the error
amplifier and drawing 20A through ROCSET. Once the overcurrent level has been sampled, the soft start function is
initiated. The clamp on the error amplifier (COMP/OCSET pin)
initially controls the converter’s output voltage during soft start.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). When the
internally generated Soft-Start voltage exceeds the feedback
5
LO
CIN
VOUT
LOAD
(EQ. 3)
where IOCSET is the internal OCSET current source (20A
typical). The OC trip point varies mainly due to the
MOSFET’s rDS(ON) variations. To avoid over-current tripping
in the normal operating load range, find the ROCSET resistor
from the equation above with:
3. Determine IPEAK for
Application Guidelines
CO
RETURN
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors CIN and CO may each
represent numerous physical capacitors. Locate the ISL6520
within 3 inches of the MOSFETs, Q1 and Q2 . The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6520 must be sized to handle up to 1A peak current.
FN9009.6
April 3, 2007
ISL6520
Figure 4 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
the COMP/OCSET pin and locate the resistor, ROSCET close
to the COMP/OCSET pin because the internal current source is
only 20A. Provide local VCC decoupling between VCC and
GND pins. Locate the capacitor, CBOOT as close as practical to
the BOOT and PHASE pins. All components used for feedback
compensation should be located as close to the IC a practical.
BOOT
D1
CBOOT
ISL6520
Q1
LO
-
VOSC
DRIVER
+
PHASE
VOUT
CO
ESR
(PARASITIC)
-
LO
VOUT
+5V
PWM
COMPARATOR
VE/A
PHASE
VCC
VIN
DRIVER
OSC
ZFB
+VIN
Q2
LOAD
ROCSET
+5V
7. Estimate Phase Margin - Repeat if Necessary.
CO
ZIN
+
ERROR
AMP
REFERENCE
DETAILED COMPENSATION COMPONENTS
COMP/OCSET
ZFB
C2
CVCC
GND
C1
C3
R2
R3
R1
COMP
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
VOUT
ZIN
FB
-
+
Feedback Compensation
ISL6520
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulsewidth modulated (PWM) wave with an amplitude of VIN at
the PHASE node. The PWM wave is smoothed by the output
filter (LO and CO).
Modulator Break Frequency Equations
1
F LC = ------------------------------------------2 x L O x C O
1
F ESR = -------------------------------------------2 x ESR x C O
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR . The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage VOSC .
Compensation Break Frequency Equations
(EQ. 4)
The compensation network consists of the error amplifier
(internal to the ISL6520) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1 , R2 ,
R3 , C1 , C2 , and C3) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
6
REFERENCE
1
F Z1 = -----------------------------------2 x R 2 x C 1
1
F P1 = -------------------------------------------------------- C 1 x C 2
2 x R 2 x  ----------------------
 C1 + C2 
1
F Z2 = ------------------------------------------------------2 x  R 1 + R 3  x C 3
1
F P2 = -----------------------------------2 x R 3 x C 3
(EQ. 5)
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
FN9009.6
April 3, 2007
ISL6520
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
FZ1 FZ2
FP1
FP2
Output Inductor Selection
80
OPEN LOOP
ERROR AMP GAIN
GAIN (dB)
60
40
20
20LOG
(R2/R1)
0
20LOG
(VIN/DVOSC)
MODULATOR
GAIN
-20
COMPENSATION
GAIN
-40
-60
CLOSED LOOP
GAIN
FLC
10
100
1K
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
I =
VIN - VOUT
Fs x L
x
VOUT
VOUT = I x ESR
VIN
(EQ. 6)
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor’s ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
7
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6520 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
(EQ. 7)
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk
capacitors to supply the current needed each time Q1 turns
on. Place the small ceramic capacitors physically close to
FN9009.6
April 3, 2007
ISL6520
the MOSFETs and between the drain of Q1 and the source
of Q2 .
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
PUPPER = Io2 x rDS(ON) x D +
PLOWER = Io2 x rDS(ON) x (1 - D)
Where: D is the duty cycle = VOUT / VIN ,
tSW is the switching interval, and
FS is the switching frequency.
+5V
VCC
The ISL6520 requires two N-Channel power MOSFETs.
These should be selected based upon rDS(ON) , gate
supply requirements, and thermal management
requirements.
8
(EQ. 8)
Given the reduced available gate bias voltage (5V),
logic-level or sub-logic-level transistors should be used for
both N-MOSFETs. Caution should be exercised with
devices exhibiting very low VGS(ON) characteristics. The
shoot-through protection present aboard the ISL6520 may
be circumvented by these MOSFETs if they have large
parasitic impedences and/or capacitances that would
inhibit the gate of the MOSFET from being discharged
below its threshold level before the complementary
MOSFET is turned on.
MOSFET Selection/Considerations
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only
the upper MOSFET has switching losses, since the lower
MOSFETs body diode or an external Schottky rectifier
across the lower MOSFET clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not
adequately model power loss due the reverse-recovery of
the lower MOSFET’s body diode. The gate-charge losses
are dissipated by the ISL6520 and don't heat the
MOSFETs. However, large gate-charge increases the
switching interval, tSW which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within
their maximum junction temperature at high ambient
temperature by calculating the temperature rise according
to package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
1 Io x V x t
IN SW x FS
2
DBOOT
+5V
+ VD BOOT
CBOOT
ISL6520
UGATE
Q1
PHASE
-
+
LGATE
NOTE:
VG-S  VCC -VD
Q2
NOTE:
VG-S  VCC
GND
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Figure 7 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from VCC . The boot capacitor,
CBOOT, develops a floating supply voltage referenced to
the PHASE pin. The supply is refreshed to a voltage of VCC
less the boot diode drop (VD) each time the lower
MOSFET, Q2, turns on.
FN9009.6
April 3, 2007
ISL6520
ISL6520 DC/DC Converter Application Circuit
Figure 8 shows an application circuit of a DC/DC Converter.
Detailed information on the circuit, including a complete Bill-
of-Materials and circuit board description, can be found in
Application Note AN9932.
+5V
+
CIN
2 x 330F
0.1F
2 x 1F
VCC
5
ISL6520
6.19k
D1
MONITOR
AND
PROTECTION
1
2 UGATE
COMP/OCSET 7
REF
10.0k
8 PHASE
0.1F
Q1
L1
+
470pF
-
8200pF
4
+
-
FB 6
OSC
1.00k
BOOT
U1
VOUT
LGATE
Q2
3
+
COUT
3 x 330F
0.1F
GND
3.16k
60.4
18000pF
Component Selection Notes:
CIN - Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent.
COUT - Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent.
D1 - 30mA Schottky Diode, MA732 or Equivalent
L1 - 3.1H Inductor, Panasonic P/N ETQ-P6F2ROLFA or Equivalent.
Q1 , Q2 - Intersil MOSFET; HUF76143.
FIGURE 8. 5V to 3.3V 15A DC/DC CONVERTER
9
FN9009.6
April 3, 2007
ISL6520
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e

B S
0.050 BSC
-
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
H
N
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
10
FN9009.6
April 3, 2007
ISL6520
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
b
0.20 REF
0.23
D
0.35
5, 8
4.00 BSC
D1
D2
0.28
9
-
3.75 BSC
1.95
2.10
9
2.25
7, 8
E
4.00 BSC
-
E1
3.75 BSC
9
E2
1.95
e
2.10
2.25
7, 8
0.65 BSC
-
k
0.25
-
-
-
L
0.50
0.60
0.75
8
L1
-
-
0.15
10
N
16
2
Nd
4
3
Ne
4
3
P
-
-
0.60
9

-
-
12
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN9009.6
April 3, 2007
Similar pages