DATASHEET

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ISL6522
®
Buck and Synchronous Rectifier
Pulse-Width Modulator (PWM) Controller
The ISL6522 provides complete control and protection for a
DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive two N-Channel
MOSFETs in a synchronous rectified buck topology. The
ISL6522 integrates all of the control, output adjustment,
monitoring and protection functions into a single package.
The output voltage of the converter can be precisely
regulated to as low as 0.8V, with a maximum tolerance of
±1% over temperature and line voltage variations.
The ISL6522 provides simple, single feedback loop, voltagemode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0–100%.
The ISL6522 protects against overcurrent conditions by
inhibiting PWM operation. The ISL6522 monitors the current
by using the rDS(ON) of the upper MOSFET which eliminates
the need for a current sensing resistor.
Pinouts
SOIC, TSSOP
TOP VIEW
RT
1
14 VCC
OCSET
2
13 PVCC
SS
3
12 LGATE
COMP
4
11 PGND
March 10, 2006
FN9030.8
Features
• Drives two N-Channel MOSFETs
• Operates from +5V or +12V input
• Simple single-loop control design
- Voltage-mode PWM control
• Fast transient response
- High-bandwidth error amplifier
- Full 0–100% duty ratio
• Excellent output voltage regulation
- 0.8V internal reference
- ±1% over line voltage and temperature
• Overcurrent fault monitor
- Does not require extra current sensing element
- Uses MOSFETs rDS(ON)
• Converter can source and sink current
• Small converter size
- Constant frequency operation
- 200kHz free-running oscillator programmable from
50kHz to over 1MHz
• 14-lead SOIC and TSSOP package and 16-lead 5x5mm
QFN Package
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline.
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-free plus anneal available (RoHS compliant)
FB
5
10 BOOT
Applications
EN
6
9
UGATE
GND
7
8
PHASE
• Power supply for Pentium®, Pentium Pro, PowerPC® and
AlphaPC™ microprocessors
• High-power 5V to 3.xV DC-DC regulators
QFN
TOP VIEW
NC
OCSET
RT
VCC
• Low-voltage distributed power supplies
16
15
14
13
SS 1
12 PVCC
COMP 2
11 LGATE
GND
5
6
1
7
8
UGATE
9
PHASE
EN 4
GND
10 PGND
NC
FB 3
BOOT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2002, 2004-2006. All Rights Reserved
PowerPC® is a trademark of IBM. AlphaPC™ is a trademark of Digital Equipment Corporation. Pentium® is a registered trademark of Intel Corporation.
ISL6522
Ordering Information
Ordering Information (Continued)
PART
NUMBER
PART
MARKING
M14.15
ISL6522CR
ISL6522CR
14 Ld SOIC
(Pb-free)
M14.15
ISL6522CRZ ISL6522CRZ
(Note)
0 to 70
14 Ld SOIC
(Pb-free)
M14.15
ISL6522IR
ISL6522IRZ
(Note)
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C)
ISL6522CB
ISL6522CB
0 to 70
14 Ld SOIC
ISL6522CBZ
(Note)
6522CBZ
0 to 70
ISL6522CBZA 6522CBZ
(Note)
PACKAGE
PKG.
DWG. #
ISL6522IB
ISL6522IB
-40 to 85
14 Ld SOIC
M14.15
ISL6522IBZ
(Note)
6522IBZ
-40 to 85
14 Ld SOIC
(Pb-free)
M14.15
ISL6522CV
ISL6522CV
ISL6522CVZ ISL6522CVZ
(Note)
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
0 to 70
16 Ld 5x5 QFN L16.5x5B
0 to 70
16 Ld 5x5 QFN L16.5x5B
(Pb-free)
ISL6522IR
-40 to 85
16 Ld 5x5 QFN L16.5x5B
ISL6522IRZ
-40 to 85
16 Ld 5x5 QFN L16.5x5B
(Pb-free)
0 to 70
14 Ld TSSOP M14.173
0 to 70
14 Ld TSSOP M14.173
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Add “-T” for tape and reel.
ISL6522IV
ISL6522IV
-40 to 85
14 Ld TSSOP M14.173
ISL6522IVZ
(Note)
ISL6522IVZ
-40 to 85
14 Ld TSSOP M14.173
(Pb-free)
Typical Application
12V
+5V OR +12V
VCC
SS
MONITOR AND
PROTECTION
OCSET
EN
BOOT
RT
OSC
UGATE
ISL6522
REF
FB
PVCC
+
-
COMP
2
PHASE
-
+
+12V
+VO
LGATE
PGND
GND
FN9030.8
March 10, 2006
ISL6522
Block Diagram
VCC
POWER-ON
RESET (POR)
EN
10µA
+
OCSET
-
OVER
CURRENT
SOFTSTART
SS
BOOT
4V
200µA
UGATE
PHASE
REFERENCE
0.8VREF
PWM
COMPARATOR
+
-
ERROR
AMP
FB
+
-
INHIBIT
PWM
GATE
CONTROL
LOGIC
PVCC
LGATE
PGND
COMP
OSCILLATOR
RT
3
GND
FN9030.8
March 10, 2006
ISL6522
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . +15.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
θJC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
67
n/a
TSSOP Package (Note 1) . . . . . . . . . .
95
n/a
QFN Package (Notes 2, 3). . . . . . . . . .
36
5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range, ISL6522C . . . . . . . . . . . . 0°C to 70°C
Ambient Temperature Range, ISL6522I. . . . . . . . . . . .-40°C to 85°C
Junction Temperature Range, ISL6522C. . . . . . . . . . . 0°C to 125°C
Junction Temperature Range, ISL6522I . . . . . . . . . .-40°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a highs effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. SeeTech
Brief TB379.
3. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
EN = VCC; UGATE and LGATE Open
-
5
-
mA
EN = 0V
-
50
100
µA
Rising VCC Threshold
VOCSET = 4.5VDC
-
-
10.4
V
Falling VCC Threshold
VOCSET = 4.5VDC
8.1
-
-
V
Enable-Input Threshold Voltage
ISL6522C, VOCSET = 4.5VDC
0.8
-
2.0
V
ISL6522I, VOCSET = 4.5VDC
0.8
-
2.1
V
-
1.27
-
V
ISL6522C, RT = OPEN, VCC = 12
175
200
230
kHz
ISL6522I, RT = OPEN, VCC = 12
160
200
230
6kΩ < RT to GND < 200kΩ
-20
-
+20
%
VCC SUPPLY CURRENT
Nominal Supply
ICC
Shutdown Supply
POWER-ON RESET
Rising VOCSET Threshold
OSCILLATOR
Free Running Frequency
Total Variation
Ramp Amplitude
∆VOSC
RT = OPEN
-
1.9
-
VP-P
VREF
Commercial
-1
-
1
%
Industrial
-2
-
+1
%
-
0.800
-
V
-
88
-
dB
-
15
-
MHz
-
6
-
V/µs
350
500
-
mA
REFERENCE
Reference Voltage Tolerance
Reference Voltage
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
COMP = 10pF
GATE DRIVERS
Upper Gate Source
IUGATE
4
VBOOT - VPHASE = 12V, VUGATE = 6V
FN9030.8
March 10, 2006
ISL6522
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
SYMBOL
Upper Gate Sink
RUGATE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6522C, ILGATE = 0.3A
-
5.5
10
Ω
ISL6522I, ILGATE = 0.3A
-
5.5
7.2
Ω
Lower Gate Source
ILGATE
VCC = 12V, VLGATE = 6V
300
450
-
mA
Lower Gate Sink
RLGATE
ISL6522C, ILGATE = 0.3A
-
3.5
6.5
Ω
ISL6522I, ILGATE = 0.3A
-
3.5
4.5
Ω
170
200
230
µA
-
10
-
µA
PROTECTION
OCSET Current Source
IOCSET
Soft-Start Current
VOCSET = 4.5VDC
ISS
Typical Performance Curves
80
1000
60
CGATE = 3300pF
IVCC (mA)
RESISTANCE (kΩ)
70
RT PULLUP
TO +12V
100
RT PULLDOWN
TO VSS
50
40
CGATE = 1000pF
30
20
10
CGATE = 10pF
10
10
100
SWITCHING FREQUENCY (kHz)
0
100
1000
13 PVCC
3
12 LGATE
COMP
4
11 PGND
FB
5
10 BOOT
EN
6
9
UGATE
GND 7
8
PHASE
VCC
2
SS
RT
OCSET
OCSET
14 VCC
NC
1
QFN
16
15
14
13
SS 1
400
500
600
700
800
900
1000
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
RT
RT
This pin provides oscillator switching frequency adjustment.
By placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
6
5 • 10
Fs ≈ 200kHz + -----------------RT
(RT to GND)
Conversely, connecting a pull-up resistor (RT) from this pin
to VCC reduces the switching frequency according to the
following equation:
7
4 • 10
Fs ≈ 200kHz – -----------------RT
(RT to 12V)
12 PVCC
COMP 2
11 LGATE
GND
9
5
6
7
8
UGATE
EN 4
PHASE
10 PGND
GND
FB 3
NC
SOIC
and
TSSOP
300
SWITCHING FREQUENCY (kHz)
FIGURE 1. RT RESISTANCE vs FREQUENCY
Functional Pin Descriptions
200
5
BOOT
FN9030.8
March 10, 2006
ISL6522
OCSET
LGATE
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. ROCSET, an internal 200µA current source
(IOCS), and the upper MOSFET on-resistance (rDS(ON)) set
the converter overcurrent (OC) trip point according to the
following equation:
Connect LGATE to the lower MOSFET gate. This pin provides
the gate drive for the lower MOSFET. This pin is also
monitored by the adaptive shoot through protection circuitry to
determine when the lower MOSFET has turned off.
I OCS • R OCSET
I PEAK = ------------------------------------------r DS ( ON )
PVCC
Provide a bias supply for the lower gate drive to this pin.
An overcurrent trip cycles the soft-start function.
SS
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-start
interval of the converter.
COMP and FB
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
EN
This pin is the open-collector enable pin. Pull this pin below
1V to disable the converter. In shutdown, the soft-start pin is
discharged and the UGATE and LGATE pins are held low.
GND
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PHASE
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for overcurrent protection. This pin also provides the return
path for the upper gate drive.
UGATE
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET. This pin is also
monitored by the adaptive shoot through protection circuitry to
determine when the upper MOSFET has turned off.
BOOT
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
VCC
Provide a 12V bias supply for the chip to this pin.
Functional Description
Initialization
The ISL6522 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages and the enable (EN) pin. The POR
monitors the bias voltage at the VCC pin and the input
voltage (VIN) on the OCSET pin. The level on OCSET is
equal to VIN Less a fixed voltage drop (see overcurrent
protection). With the EN pin held to VCC, the POR function
initiates soft-start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
+12V power source, VIN and VCC are equivalent and the
+12V power source must exceed the rising VCC threshold
before POR initiates operation.
The POR function inhibits operation with the chip disabled
(EN pin low). With both input supplies above their POR
thresholds, transitioning the EN pin high initiates a soft-start
interval.
Soft-Start
The POR function initiates the soft-start sequence. An internal
10µA current source charges an external capacitor (CSS) on
the SS pin to 4V. Soft-start clamps the error amplifier output
(COMP pin) to the SS pin voltage. Figure 3 shows the softstart interval. At t1 in Figure 3, the SS and COMP voltages
reach the valley of the oscillator’s triangle wave. The
oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2, at which
point the output is in regulation and the clamp on the COMP
pin is released. This method provides a rapid and controlled
output voltage rise.
PGND
This is the power ground connection. Tie the lower MOSFET
source to this pin.
6
FN9030.8
March 10, 2006
ISL6522
VOLTAGE
VSOFT START
VOUT
VCOMP
VOSC(MIN)
CLAMP ON VCOMP RELEASED AT
STEADY STATE
t0
t1
TIME
t2
C SS
t 1 = ----------- ⋅ V OSC ( MIN )
I SS
C SS V OUT SteadyState
t SoftStart = t 2 – t 1 = ----------- ⋅ ------------------------------------------------ ⋅ ∆V OSC
I SS
V IN
Where:
CSS = Soft Start Capacitor
ISS = Soft Start Current = 10µA
VOSC(MIN) = Bottom of Oscillator = 1.35V
VIN = Input Voltage
∆VOSC = Peak to Peak Oscillator Voltage = 1.9V
VOUTSteadyState = Steady State Output Voltage
FIGURE 3. SOFT-START INTERVAL
is reference to VIN. When the voltage across the upper
MOSFET (also referenced to VIN) exceeds the voltage
across ROCSET, the overcurrent function initiates a soft-start
sequence. The soft-start function discharges CSS with a
10µA current sink and inhibits PWM operation. The soft-start
function recharges CSS, and PWM operation resumes with
the error amplifier clamped to the SS voltage. Should an
overload occur while recharging CSS, the soft-start function
inhibits PWM operation while fully charging CSS to 4V to
complete its cycle. Figure 4 shows this operation with an
overload condition. Note that the inductor current increases
to over 15A during the CSS charging interval and causes an
overcurrent trip. The converter dissipates very little power
with this method. The measured input power for the
conditions of Figure 4 is 2.5W.
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by:
I OCSET • R OCSET
I PEAK = -------------------------------------------------r DS ( ON )
where IOCSET is the internal OCSET current source (200µA
is typical). The OC trip point varies mainly due to the
MOSFETs rDS(ON) variations. To avoid overcurrent tripping
in the normal operating load range, find the ROCSET resistor
from the equation above with:
The maximum rDS(ON) at the highest junction temperature.
OUTPUT INDUCTOR
SOFT-START
1. The minimum IOCSET from the specification table.
2. Determine I PEAK for I PEAK > I OUT ( MAX ) + ( ∆I ) ⁄ 2 ,
where ∆I is the output inductor ripple current.
4V
For an equation for the ripple current see the section under
component guidelines titled Output Inductor Selection.
2V
0V
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
presence of switching noise on the input voltage.
15A
10A
Current Sinking
5A
0A
TIME (20ms/DIV)
FIGURE 4. OVERCURRENT OPERATION
Overcurrent Protection
The overcurrent function protects the converter from a
shorted output by using the upper MOSFETs on-resistance,
rDS(ON) to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the overcurrent trip level. An internal 200µA
(typical) current sink develops a voltage across ROCSET that
7
The ISL6522 incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6522 when it is known that
the converter may sink current.
When the converter is sinking current, it is behaving as a boost
converter that is regulating its input voltage. This means that
the converter is boosting current into the VIN rail, the voltage
that is being down-converted. If there is nowhere for this current
to go, such as to other distributed loads on the VIN rail, through
a voltage limiting protection device, or other methods, the
capacitance on the VIN bus will absorb the current. This
situation will cause the voltage level of the VIN rail to increase. If
the voltage level of the rail is boosted to a level that exceeds the
maximum voltage rating of the MOSFETs or the input
capacitors, damage may occur to these parts. If the bias
voltage for the ISL6522 comes from the VIN rail, then the
FN9030.8
March 10, 2006
ISL6522
ISL6522
LO
VOUT
PHASE
+12V
Q2
CO
VCC
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors CIN
and CO each represent numerous physical capacitors.
Locate the ISL6522 within three inches of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the ISL6522 must be sized to
handle up to 1A peak current.
VIN
LO
CIN
Q2
D2
CVCC
CSS
GND
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(VOUT) is regulated to the reference voltage level. The error
amplifier (error amp) output (VE/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of VIN at the
PHASE node. The PWM wave is smoothed by the output filter
(LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ∆VOSC.
VOUT
CO
LOAD
Q1
PHASE
LGATE
Q1
SS
Layout Considerations
UGATE
D1
CBOOT
Application Guidelines
ISL6522
+VIN
BOOT
LOAD
maximum voltage rating of the ISL6522 may be exceeded and
the IC will experience a catastrophic failure and the converter
will no longer be operational. Ensuring that there is a path for
the current to follow other than the capacitance on the rail will
prevent these failure modes.
PGND
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, CSS
close to the SS pin because the internal current source is
only 10µA. Provide local VCC decoupling between VCC and
GND pins. Locate the capacitor, CBOOT as close as practical
to the BOOT and PHASE pins.
8
FN9030.8
March 10, 2006
ISL6522
4. Place 1ST Pole at the ESR Zero
VIN
OSC
5. Place 2ND Pole at Half the Switching Frequency
DRIVER
PWM
COMPARATOR
LO
-
DRIVER
+
PHASE
CO
ESR
(PARASITIC)
ZFB
VE/A
ZIN
-
+
REFERENCE
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
ZFB
C2
C1
VOUT
ZIN
C3
R2
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 with the capabilities of the error
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
100
R3
FZ1 FZ2
FP2
OPEN LOOP
ERROR AMP GAIN
60
FB
+
REF
40
20
20LOG
(R2/R1)
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
1
F ESR = --------------------------------------------2π • ( ESR • C O )
The compensation network consists of the error amplifier
(internal to the ISL6522) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1
F Z1 = ---------------------------------2π • R 2 • C1
1
F P1 = ------------------------------------------------------C1 • C2
2π • R2 •  ----------------------
 C1 + C2
1
F Z2 = -----------------------------------------------------2π • ( R1 + R3 ) • C3
1
F P2 = ---------------------------------2π • R3 • C3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole
(~75% FLC)
20LOG
(VIN/∆VOSC)
0
COMPENSATION
GAIN
MODULATOR
GAIN
-20
1
F LC = --------------------------------------2π • L O • C O
FP1
80
R1
COMP
ISL6522
6. Check Gain against Error Amplifier’s Open-Loop Gain
GAIN (dB)
∆VOSC
VOUT
CLOSED LOOP
GAIN
-40
FLC
-60
10
100
1K
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
3. Place 2ND Zero at Filter’s Double Pole
9
FN9030.8
March 10, 2006
ISL6522
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
equations give the approximate response time interval for
application and removal of a transient load:
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium-Pro be composed of at least forty (40) 1.0µF
ceramic capacitors in the 1206 surface-mount package.
L O × I TRAN
t RISE = ------------------------------V IN – V OUT
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
V IN - V OUT V OUT
∆I = -------------------------------- • ---------------Fs x L
V IN
∆VOUT= ∆I x ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6522 will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time required to
slew the inductor current from an initial current value to the
transient current level. During this interval the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
10
L O × I TRAN
t FALL = -----------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The ISL6522 requires two N-Channel power MOSFETs.
These should be selected based upon rDS(ON), gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses seen
when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower
FN9030.8
March 10, 2006
ISL6522
switch realizes most of the switching losses when the converter
is sinking current (see the equations below).
+12V
Losses while Sourcing Current
VCC
DBOOT
+
2
1
P UPPER = Io × r DS ( ON ) × D + --- ⋅ Io × V IN × t SW × F S
2
PLOWER = Io2 x rDS(ON) x (1 - D)
BOOT
CBOOT
+5V
PVCC OR +12V
LGATE
+
Q2
D2
NOTE:
VG-S ≈ PVCC
PGND
FS is the switching frequency.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from VCC . The boot capacitor, CBOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of VCC
less the boot diode drop (VD) when the lower MOSFET, Q2
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to VCC . For Q2, a
logic-level MOSFET can be used if its absolute gate-tosource voltage rating exceeds the maximum voltage applied
to PVCC.
NOTE:
VG-S ≈ VCC - VD
PHASE
2
1
P LOWER = Io × r DS ( ON ) × ( 1 – D ) + --- ⋅ Io × V IN × t SW × F S
2
Standard-gate MOSFETs are normally recommended for
use with the ISL6522. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-tosource voltage rating determine whether logic-level
MOSFETs are appropriate.
Q1
UGATE
PUPPER = Io2 x rDS(ON) x D
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverserecovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL6522 and do not
heat the MOSFETs. However, large gate-charge increases
the switching interval, tSW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
+5V OR +12V
-
ISL6522
Losses while Sinking Current
Where: D is the duty cycle = VOUT / VIN ,
tSW is the switching interval, and
VD
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to VCC . This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak upper gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and +12VDC
for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
exceeds the maximum voltage applied to PVCC .
+12V
+5V OR LESS
VCC
ISL6522
BOOT
Q1
UGATE
NOTE:
VG-S ≈ VCC - 5V
PHASE
PVCC
+
+5V
OR +12V
LGATE
PGND
Q2
D2
NOTE:
VG-S ≈ PVCC
GND
FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
11
FN9030.8
March 10, 2006
ISL6522
ISL6522 DC-DC Converter Application
Circuit
implemented using the ISL6522 controller without any
modifications. Detailed information on the circuit, including a
complete bill of materials and circuit board description, can
be found in Application Note AN9722. See Intersil’s home
page on the web: http://www.intersil.com.
Figure 11 shows a DC-DC converter circuit for a
microprocessor application, originally designed to employ
the HIP6006 controller. Given the similarities between the
HIP6006 and ISL6522 controllers, the circuit can be
12VCC
VIN
C17-18
2x 1µF
1206
C1-3
3x 680µF
RTN
C12
1µF
1206
R7
10K
C19
VCC
1000pF
14
2 OCSET
6
ENABLE
MONITOR AND
PROTECTION
SS 3
3.01K
Q1
R1
SPARE
U1
ISL6522
REF
VOUT
CR2
MBR
340
11 PGND
7
COMP
C14
Q2
12 LGATE
-+
+
4
R2
1K
L1
8 PHASE
13 PVCC
++
--
5
C20
0.1µF
9 UGATE
OSC
FB
PHASE
TP2
10 BOOT
RT 1
C13
0.1µF
CR1
4148
R6
GND
C6-9
4x 1000µF
RTN
JP1
33pF
C15
R5
0.01µF
15K
COMP
TP1
C16
SPARE
R3
1K
R4
SPARE
Component Selection Notes:
C1-C3 - Three each 680µF 25W VDC, Sanyo MV-GX or equivalent.
C6-C9 - Four each 1000µF 6.3W VDC, Sanyo MV-GX or equivalent.
L1 - Core: micrometals T50-52B; winding: ten turns of 17AWG.
CR1 - 1N4148 or equivalent.
CR2 - 3A, 40V Schottky, Motorola MBR340 or equivalent.
Q1, Q2 - Fairchild MOSFET; RFP25N05
FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT
12
FN9030.8
March 10, 2006
ISL6522
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
α
e
A1
B
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MILLIMETERS
α
14
0o
14
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
13
FN9030.8
March 10, 2006
ISL6522
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
L
A
D
-C-
α
e
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
A2
c
0.10(0.004)
C A M
B S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
E
0.246
L
0.0177
N
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
α
0.65 BSC
0.256
6.25
0.0295
0.45
14
0o
6.50
0.75
14
8o
0o
6
7
8o
Rev. 1 6/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
14
FN9030.8
March 10, 2006
ISL6522
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.28
D
0.33
9
0.40
5, 8
5.00 BSC
D1
D2
9
0.20 REF
-
4.75 BSC
2.95
3.10
9
3.25
7, 8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
2.95
e
3.10
3.25
7, 8
0.80 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
16
2
Nd
4
3
Ne
4
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN9030.8
March 10, 2006
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