DATASHEET

EL7556D
®
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Data Sheet
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August 1, 2005
Integrated Adjustable 6 Amp
Synchronous Switcher
FN7339.1
Features
• Improved temperature and voltage ranges
The EL7556D is an adjustable synchronous DC:DC
switching regulator optimized for a 5V input and 1.0V-3.8V
output. By combining integrated NMOS power FETS with a
fused-lead package, the EL7556D can supply up to 6A
continuous output current without the use of external power
devices or discrete heat sinks, thereby minimizing design
effort and overall system cost.
• 6A continuous load current
• Precision internal 1% reference
• 1.0V to 3.8V output voltage
• Internal power MOSFETs
• >90% efficiency
On-chip resistorless current sensing is used to achieve
stable, highly efficient, current-mode control. The EL7556D
also incorporates the VCC2DET function to directly interface
with the Intel P54 and P55 microprocessors. Depending on
the state of VCC2DET, the output voltage is internally preset
to 3.5V or a user-adjustable voltage using two external
resistors. In both internal and external feedback modes the
active-high PWRGD output indicates when the regulator
output is within ±10% of the programmed voltage. An onboard sensor monitors die temperature (OT) for overtemperature conditions and can be connected directly to
OUTEN to provide automatic thermal shutdown. Adjustable
oscillator frequency and slope compensation allow added
flexibility in overall system design.
• Synchronous switching
The EL7556D is available in a 28-pin SO package and is
specified for operation over the full -40°C to +85°C
temperature range.
• Internal soft-start
• Adjustable slope compensation
• Over-temperature indicator
• Pulse-by-pulse current limiting
• Operates up to 1MHz
• 1.5% typical output accuracy
• Adjustable oscillator with sync
• Remote enable/disable
• Intel P54- and P55-compatible
• VCC2DET interface
• Pb-free plus anneal available (RoHS compliant)
Applications
Ordering Information
PART
NUMBER
• PC motherboards
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL7556DCM
28-Pin SO
-
MDP0027
• 5V to 1.0V DC:DC conversion
EL7556DCM-T13
28-Pin SO
13”
MDP0027
• Portable electronics/instruments
EL7556DCMZ
(See Note)
28-Pin SO
(Pb-free)
-
MDP0027
• P54 and P55 regulators
EL7556DCMZ-T13
(See Note)
28-Pin SO
(Pb-free)
13”
MDP0027
• Local high power CPU supplies
• GTL+ Bus power supply
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL7556D
Pinout
EL7556D
(28-PIN SO)
TOP VIEW
FB1 1
28 FB2
CREF 2
27 CP
CSLOPE 3
26 C2V
COSC 4
25 VSS
VDD 5
24 VHI
VIN 6
23 LX
VSSP 7
22 LX
VIN 8
21 LX
VSSP 9
20 LX
VSSP 10
19 VSSP
VSSP 11
18 VSSP
VSSP 12
17 TEST
VCC2DET 13
16 PWRGD
OUTEN 14
15 OT
2
EL7556D
Absolute Maximum Ratings (TA = 25°C)
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Supply (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0V
Output Pins . . . . . . . . . . . . . . .-0.3V below GND, +0.3V above VDD
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 135°C
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
VDD = VIN = 5V, COSC = 1nF, CSLOPE = 470pF, TA = 25°C, unless otherwise specified.
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
25
mA
GENERAL
IDD
VDD Supply Current
OUTEN = 4V, FOSC = 120kHz
11
IDDOFF
VDD Standby Current
OUTEN = 0
0.1
IVIN
VIN No Load Current
OUTEN = 0
3
5
mA
VOUT1
Output Initial Accuracy
VCC2DET = 4V, IL = 3A (see Fig. 1)
3.450
3.500
3.550
V
VOUT2
Output Initial Accuracy
VCC2DET = 0V, IL = 3A, R3 = 150Ω, R4 =
100Ω (see Fig. 1)
2.450
2.500
2.550
V
VOUTLINE
Output Line Regulation
VDD = 5V, ±10%
-1
1
%
VOUTLOAD
Output Load Regulation
0A < ILOAD < 6A, relative to IL = 3A,
continuous mode of operation (see Fig.1)
-1
1
%
RSHORT
Short Circuit Load Resistance
IL = 6A, prior to continuous application of
RSHORT, OUTEN connected to OT
II MAX
Current Limit
VOUTTC
Output Tempco
TOT
mA
100
mΩ
9
A
±1
%
Over-temperature Threshold
135
°C
THYS
Over-temperature Hysteresis
40
°C
VPWRGD
Power Good Threshold Relative to
Programmed Output Voltage
VDDOFF
Minimum VDD for Shutdown
VDDON
Maximum VDD for Startup
VHYS
Input Hysteresis
MSS
DMAX
-40°C < TA < 85°C
VCC2SEL = 4V, VOUT = 3.50V
±6
±10
±14
3.15
V
4.15
VHYS = VDDON - VDDOFF
%
V
0.5
V
Soft-start Slope
7
V/ms
Maximum Duty Cycle
96
%
CONTROLLER - INPUTS
IPUP
VCC2DET, OUTEN Pull-up Current
ICSLOPE
CSLOPE Charging Current
IFB1
FB1 Input Pull-up Current
ROT
Over-temperature Pull-up Resistance
VIH
VCC2DET, OUTEN Input High
VIL
VCC2DET, OUTEN Input Low
VOH PWGD
Powergood Drive High
ILOAD = 1mA
VOL PWGD
Powergood Drive Low
ILOAD = -1mA
VCC2DET, OUTEN = 0
10
14
18
µA
23
28.5
34
µA
2
OT = 0V
30
40
µA
50
4
kΩ
V
0.8
3.5
V
V
1.0
V
1.273
V
CONTROLLER - REFERENCE
VREF
Reference Accuracy
3
IREF = 0
1.247
1.260
EL7556D
VDD = VIN = 5V, COSC = 1nF, CSLOPE = 470pF, TA = 25°C, unless otherwise specified. (Continued)
Electrical Specifications
PARAMETER
DESCRIPTION
VREFTC
Reference Voltage Tempco
VREFLOAD
Reference Load Regulation
CONDITIONS
MIN
TYP
MAX
50
0 < ILOAD < 100µA
0.5
VDD = 5V, ILOAD = 10mA
7.5
UNIT
ppm/°C
0.5
%/°C
8.7
V
CONTROLLER - DOUBLER
VC2V
Voltage Doubler Output
8.1
CONTROLLER - OSCILLATOR
FRAMP
Oscillator Ramp Amplitude
IOSC CHG
Oscillator Charge Current
IOSC DIS
Oscillator Discharge Current
FOSC
Oscillator Initial Accuracy
tSYNC
Minimum Oscillator Sync Width
1.2
V
0.2V < VOSC < 1.4V
150
µA
0.2V < VOSC < 1.4V
5
mA
105
125
145
50
kHz
ns
POWER - FET
ILEAK
LX Output Leakage to VSS
RDSON
Composite FET Resistance
RDSONTC
RDSON Tempco
0.1
mΩ/°C
tBRM
FET Break Before Make Delay
10
ns
tLEB
High Side FET Minimum on Time (LEB)
140
ns
4
LX = 0V
18
100
µA
30
mΩ
EL7556D
Typical Performance Curves
96
Efficiency vs ILOAD (VOUT =3.5V)
VDD=VIN=5.0V (±10%)
Efficiency vs ILOAD (VDD=5.0V)
100
VDD=4.5V
94
95
VCC=3.5V
90
Efficiency (%)
Efficiency (%)
92
VDD=5V
88
VDD=5.5V
86
90
VCC=2.5V
85
80
VCC=1V
84
75
82
80
0.5
TA=25°C
1.5
2.5
3.5
4.5
5.5
70
0.5
6.5
1.5
2.5
3.5
IOUT(A)
IOUT (A)
Line Regulation (CSLOPE=100pF)
3.54
TA=25°C
VOUT (V)
VOUT (V)
3.52
IOUT=0.5A
3.50
3.49
IOUT=3A
3.48
VIN=5V
VIN=5.5V
3.51
3.50
3.49
3.48
IOUT=6A
3.47
VIN=4.5V
3.47
3.46
4.5
5.0
3.46
5.5
0.5
3.0
IOUT (A)
VIN (V)
0.8
Line Regulation vs CSLOPE (IOUT=3A)
VDD=VIN=5.0V ±10%
0.6
TA=25°C
0.7
TA=25°C
0.5
ΔVOUT (±) (%)
ΔVOUT (±) (%)
VOUT=3.5A
0.5
VOUT=3.5A
0.4
VOUT=2.5A
0.3
0.4
VOUT=2.5A
0.3
0.2
VOUT=1A
0.2
0.1
0.1
VOUT=1A
0.0
50
75
100
125
150
0.0
175
50
75
CSLOPE (pF)
0.8
TA=25°C
125
150
175
150
175
Load Regulation vs CSLOPE
IOUT=3A, +3A, -2.5A
0.7
TA=25°C
0.6
ΔVOUT (±) (%)
0.6
0.5
IOUT=6A
0.4
0.3
0.2
0.5
VIN=4.5V
0.4
0.3
0.2
IOUT=0.5A
0.1
0.0
50
100
CSLOPE (pF)
Line Regulation vs CSLOPE
VIN=VDD=5.0V ±10%
0.7
ΔVOUT (±) (%)
6.0
Load Regulation vs CSLOPE (VIN=5.0V)
IOUT=3A, +3A, -2.5A
0.6
0.8
6.0
TA=25°C
3.53
3.52
3.51
5.5
Load Regulation (CSLOPE=100pF)
3.54
3.53
4.5
VIN=5V
VIN=5.5V
0.1
75
100
125
CSLOPE (pF)
5
150
175
0.0
50
75
100
125
CSLOPE (pF)
EL7556D
Typical Performance Curves
1.5
VOUT vs CSLOPE
(VIN=5.0V, ILOAD=0.5A)
1.5
TA=25°C
1.0
TA=25°C
1.0
VOUT=1V
0.0
Deviation in VOUT (%)
0.5
ΔVOUT (±) (%)
VOUT Variation vs Programmed Output
Voltage [VIDEAL=(1+R3/R4)]
VOUT=2.5V
-0.5
-1.0
VOUT=3.5V
-1.5
-2.0
C
SL
OP
E =1
OS
00
C=
p
0.5
C
F
22
0p
F
0.0
-0.5
-1.0
-2.5
Loop Gain Induced Error
-3.0
50
100
75
125
150
-1.5
1.0
175
1.5
2.0
2.5
3.5
4.0
FOSC vs Temperature
FOSC vs COSC
10k
520
TA=25°C
510
1k
VDD=4.5V
500
FOSC (kHz)
FOSC (kHz)
3.0
VIDEAL (V)
CSLOPE (pF)
100
490
VDD=5.5V
480
VDD=5V
470
10
460
1
10
100
1k
450
100k
0
20
40
COSC (pF)
I(VDD) + I(VIN) vs FOSC
60
50
80
IVIN (mA)
IQ (mA)
VDD=5V
VDD=4.5V
20
10
VDD=5V
8
6
VDD=4.5V
4
10
Discontinuous Mode
0
200
400
600
2
Continuous Mode
800
Discontinuous Mode
0
200
400
600
1000
FOSC (kHz)
1000
2.0
TA=25°C
OUTEN=VDD
VDD=5.5V
35
IDD (mA)
800
IDD + IVIN vs FOSC
IDD (mA) + IVIN
40
Continuous Mode
FOSC (kHz)
I(VDD) vs FOSC
45
140
VDD=5.5V
12
40
50
120
TA=25°C
OUTEN=VDD
14
VDD=5.5V
30
100
I(VIN) vs FOSC
16
TA=25°C
OUTEN=VDD
60
Temperature (°C)
30
25
VDD=5V
20
VDD=4.5V
15
VDD=5.5V
1.5
VDD=5V
VDD=4.5V
10
5
0
200
400
600
FOSC (kHz)
6
800
1000
1.0
10
100
FOSC (kHz)
1000
EL7556D
Typical Performance Curves
Minimum Output Voltage vs FOSC
Power On Reset
40
2.3
TA=25°C
OUTEN=VDD
FOSC=500k
1.9
VOUT (V)
30
IQ (mA)
TJ=120°C
2.1
20
10
VDD=5.5V
1.7
1.5
VDD=5V
1.3
1.1
VDD=4.5V
0.9
0
2.5
3.0
4.0
3.5
4.5
0.7
5.0
VDD(V)
FOSC (kHz)
8.0
39
7.5
37
7.0
35
ILOAD (A)
ΘJA (°C/W)
ΘJA vs Cu Area
41
Board with no
Components
33
31
Board with
Inductor
29
27
25
0.00
1.00
3.00
2.00
4.00
5.00
6.00
36
RDSON (mΩ)
34
32
30
28
26
24
22
50
75
7
6.0
5.5
Still Air
4.0
25
OUTEN connected to OT
30
35
40
45
50
TA (°C)
38
Temperature (°C)
6.5
4.5
RDSON vs Temperature
25
100 LFPM
5.0
Bare Cu Area (in2)
20
0
Maximum ILOAD vs Temperature
7556 Demo Board (31°C/W)
100
125
55
60
65
70
EL7556D
Pin Descriptions
I = Input, O = Output, S = Supply
PIN
NUMBER
PIN NAME
PIN TYPE
FUNCTION
1
FB1
I
Voltage feedback pin for the buck regulator. Active when VCC2DET is logic low. Normally connected to
external resistor divider between VOUT and GND. A 2µA pull-up current forces VOUT to VSS in the event
that FB1 is floating and VCC2DET is inadvertently connected to GND.
2
CREF
I
Bandgap reference bypass capacitor. Typically 0.1µF to VSS.
3
CSLOPE
I
Slope compensation capacitor. Ramp width corresponds to LX duty cycle. CSLOPE to COSC ratio is
normally 1:1.5.
4
COSC
I
Oscillator timing capacitor. FOSC(Hz) can be approximated by: FOSC(Hz) = 0.0001/COSC. COSC in
Farads.
5
VDD
S
Power Supply for PWM control circuitry. Normally the same potential as VIN.
6
VIN
S
Power supply for the buck regulator. Connected to the drain of the high-side NMOS FET.
7
VSSP
S
Ground return for the buck regulator. Connected to the source of the low-side synchronous NMOS FET.
8
VIN
S
Same as pin 6.
9
VSSP
S
Same as pin 7.
10
VSSP
S
Same as pin 7.
11
VSSP
S
Same as pin 7.
12
VSSP
S
Same as pin 7.
13
VCC2DET
I
VCC2DET interface logic input. When driven to logic 1 VOUT = 3.500V. When driven to logic 0 the PWM
uses FB1 to determine VOUT: VOUT = 1.0V*(1+R3/R4).
14
OUTEN
I
The switching regulator output is enabled when logic 1. The reference voltage output operates whenever
the power supply is qualified (VDD>VPOR) regardless of the state of this pin.
15
OT
O
Over temperature indicator. Normally high. Pulls low when die temperature exceeds 135°C, returns to
the high state when die temperature has cooled to 100°C.
16
PWRGD
O
Power good window comparator output. Logic 1 when regulator output is within ±10% of programmed
voltage.
17
TEST
I
Test pin. Must be connected to VSSP in normal operation.
18
VSSP
S
Same as pin 7.
19
VSSP
S
Same as pin 7.
20
LX
O
Inductor drive pin. High current switching output whose average voltage equals the regulator output
voltage.
21
LX
O
Same as pin 20.
22
LX
O
Same as pin 20.
23
LX
O
Same as pin 20.
24
VHI
I
Gate drive to high-side driver. Bootstrapped from LX with a 0.1µF capacitor.
25
VSS
S
Ground return for the control circuitry.
26
C2V
I
Connected to voltage doubler output. Supplies gate drive to the low-side driver.
27
CP
O
Drives the negative side of charge pump capacitor at one-half the oscillator frequency FOSC.
28
FB2
I
Voltage feedback pin. Active when VCC2DET is logic 1. Internally preset to VOUT = 3.5V.
8
EL7556D
Block Diagram
FB1, Pin 1
FB2, Pin 28
PWRGD, Pin 16
CP, Pin 27
+
2-1 MUX
C2V, Pin 26
V2X
+
VHI, Pin 24
VCCDET, Pin 13
+
CSLOPE, Pin 3
Current Sense
VDD and VIN,
Pin 5,6,8
CREF, Pin 27
LEB TDELAY
1.26V
S
+
Current Limit
Q
OUTEN, Pin 14
+
4V
+ PWM
R
CSS
FF
R
S
S
LX, Pin 20-23
Q
VDD
RSS
VDD
COSC, Pin 4
+
S
+
R
VSSP, Pin 912, 18-19
+
UVLO
Zero Cross Detect
OT, Pin 15
Over Temp
Sensor
Applications Information
Circuit Description
General
The EL7556D is a fixed frequency, current mode controlled
DC:DC converter with integrated N-channel power
MOSFETS and a high precision reference. The device
incorporates all of the active circuitry required to implement a
cost effective, user-programmable 6A synchronous buck
converter suitable for use in CPU power supplies. By
combining fused-lead packaging technology with an efficient
synchronous switching architecture, high power outputs
(21W) can be realized without the use of discrete external
heat sinks.
Theory of Operation
The EL7556D is composed of 7 major blocks:
1. PWM Controller
2. Output Voltage Mode Select
3. NMOS Power FETS and Drive Circuitry
4. Bandgap Reference
5. Oscillator
6. Temperature Sensor
7. Power Good and Power On Reset
9
VSS, Pin 25
PWM Controller
The EL7556D regulates output voltage through the use of
current-mode controlled pulse width modulation. The three
main elements in a PWM controller are the feedback loop
and reference, a pulse width modulator whose duty cycle is
controlled by the feedback error signal, and a filter which
averages the logic level modulator output. In a step-down
(buck) converter, the feedback loop forces the timeaveraged output of the modulator to equal the desired output
voltage. Unlike pure voltage-mode control systems currentmode control utilizes dual feedback loops to provide both
output voltage and inductor current information to the
controller. The voltage loop minimizes DC and transient
errors in the output voltage by adjusting the PWM duty-cycle
in response to changes in line or load conditions. Since the
output voltage is equal to the time-average of the modulator
output the relatively large LC time constants found in power
supply applications generally results in low bandwidth and
poor transient response. By directly monitoring changes in
inductor current via a series sense resistor the controller’s
response time is not entirely limited by the output LC filter
and can react more quickly to changes in line or load
conditions. This feed-forward characteristic also simplifies
AC loop compensation since it adds a zero to the overall
loop response. Through proper selection of the currentfeedback to voltage-feedback ratio, the overall loop
response will approach a one pole system. The resulting
system offers several advantages over traditional voltage
EL7556D
control systems, including simpler loop compensation, pulse
by pulse current limiting, rapid response to line variation and
good load step response.
The heart of the controller is a triple-input direct summing
comparator which sums voltage feedback, current feedback
and slope compensating ramp signals together. Slope
compensation is required to prevent system instability which
occurs in current-mode topologies operating at duty-cycles
greater than 50% and is also used to define the open-loop
gain of the overall system. The compensation ramp
amplitude is user adjustable and is set using a single
external capacitor (CSLOPE). Each comparator input is
weighted and determines the load and line regulation
characteristics of the system. Current feedback is measured
by sensing the inductor current flowing through the high-side
switch whenever it is conducting. At the beginning of each
oscillator period the high-side NMOS switch is turned on and
CSLOPE ramps positively from its reset state (VREF
potential). The comparator inputs are gated off for a
minimum period of time (LEB) after the high-side switch is
turned on to allow the system to settle. The Leading Edge
Blanking (LEB) period prevents the detection of erroneous
voltages at the comparator inputs due to switching noise.
When programming low regulator output voltages the LEB
delay will limit the maximum operating frequency of the
circuit since the LEB will result in a minimum duty-cycle
regardless of the PWM error voltage. This relationship is
shown in the performance curves. If the inductor current
exceeds the maximum current limit (ILMAX), a secondary
over-current comparator will terminate the high-side switch.
If ILMAX has not been reached, the regulator output voltage
is then compared to the reference voltage VREF. The
resultant error voltage is summed with the current feedback
and slope compensation ramp. The high-side switch
remains on until all three comparator inputs have summed to
zero, at which time the high-side switch is turned off and the
low-side switch is turned on. In order to eliminate crossconduction of the high-side and low-side switches a 10ns
break-before-make delay is incorporated in the switch driver
circuitry. In the continuous mode of operation the low-side
switch will remain on until the end of the oscillator period. In
order to improve the low current efficiency of the EL7556D, a
zero-crossing comparator senses when the inductor
transitions through zero. Turning off the low-side switch at
zero inductor current prevents forward conduction through
the internal clamping diodes (LX to VSSP) when the low-side
switch turns off, reducing power dissipation. The output
enable (OUTEN) input allows the regulator output to be
disabled by an external logic control signal.
Output Voltage Mode Select
The VCC2DET multiplexes the FB1 and FB2 pins to the
PWM controller. A logic 1 on VCC2DET selects the FB2
input and forces the output voltage to the internally
programmed value of 3.50V. A logic zero on VCC2DET
10
selects FB1 and allows the output to be programmed from
1.0 to 3.8V. In general:
R 3⎞
⎛
V OUT = 1V × ⎜ 1 + -------⎟ × Volt
R 4⎠
⎝
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loopgain are changed. This is shown in the performance curves.
(The output voltage is factory trimmed to minimize error at a
2.50V output). A 2uA pull-up current from FB1 to VIN forces
VOUT to GND in the event that FB1 is not used and the
VCC2DET is inadvertently toggled between the internal and
external feedback mode of operation.
NMOS Power FETs and Drive Circuitry
The EL7556D integrates low resistance (25mΩ) NMOS
FETS to achieve high efficiency at 6A. Gate drive for both
the high-side and low-side switches is derived through a
charge pump consisting of the CP pin and external
components D1-D3 and C5-C6. The CP output is a low
resistance inverter driven at one-half the oscillator
frequency. This is used in conjunction with D2-D3 to
generate a 7.5V (typical) voltage on the C2V pin which
provides gate drive to the low-side NMOS switch and
associated level shifter. In order to use an NMOS switch for
the high-side drive it is necessary to drive the gate voltage
above the source voltage (LX). This is accomplished by
boot-strapping the VHI pin above the C2V voltage with
capacitor C6 and diode D1. When the low-side switch is
turned on the LX voltage is close to GND potential and
capacitor C6 is charged through diodes D1-D3 to
approximately 6.9V. At the beginning of the next cycle the
high side switch turns on and the LX pin begins to rise from
GND to VDD potential. As the LX pin rises the positive plate
of capacitor C6 follows and eventually reaches a value of
approximately 11.2V, for VDD=5V. This voltage is then level
shifted and used to drive the gate of the high-side FET, via
the VHI pin.
Reference
A 1% temperature compensated band gap reference is
integrated in the EL7556D. The external CREF capacitor
acts as the dominant pole of the amplifier and can be
increased in size to maximize transient noise rejection. A
value of 0.1uF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 96%.
Operating frequency can be adjusted through the COSC pin
or can be driven by an external clock source. If the oscillator
is driven by an external source, care must be taken in the
selection of CSLOPE. Since the COSC and CSLOPE values
determine the open loop gain of the system, changes to
COSC require corresponding changes to CSLOPEin order to
EL7556D
maintain a constant gain ratio. The recommended ratio of
COSC to CSLOPE is 1.5:1
Temperature Sensor
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the OT pin will output a logic 0. The upper
and lower trip points are set to 135°C and 100°C,
respectively. To enable thermal shutdown this pin should be
tied directly to OUTEN. Use of this feature is recommended
during normal operation
Power Good and Power On Reset
During power up the output regulator will be disabled until
VIN reaches a value of approximately 4.0V. Approximately
500mV of hysteresis is present to eliminate noise induced
oscillations.
Additional information can be found in Application Note #8
(Measuring the Thermal Resistance of Power SurfaceMount Packages).
If the thermal shutdown pin is connected to OUTEN the IC
will enter thermal shutdown when the maximum junction
temperature is reached. For a thermal shutdown of 135ºC
and power dissipation of 2.2W the ambient temperature is
limited to a maximum value of 67ºC (typical). The ambient
temperature range can be extended with the application of
air flow. For example, the addition of 100LFM reduces the
thermal resistance by approximately 15% and can extend
the operating ambient to 77ºC (typical). Since the thermal
performance of the IC is heavily dependent on the board
layout, the system designer should exercise care during the
design phase to ensure that the IC will operate under the
worst-case environmental conditions.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
A logic 1 on the PWRGD output indicates that regulated
output voltage is within ±10% of the nominally programmed
output voltage. Although small, the typical values of the
PWRGD threshold will vary with changes to external
feedback (and resultant loop gain) of the system. This
dependence is shown in the typical performance curves.
Thermal Management
The EL7556D utilizes “fused lead” packaging technology in
conjunction with the system board layout to achieve a lower
thermal resistance than typically found in standard 28-pin
SO packages. By fusing (or connecting) multiple external
leads to the die substrate within the package, a very
conductive heat path to the outside of the package is
created. This conductive heat path MUST then be connected
to a heat sinking area on the PCB in order to dissipate heat
out and away from the device. The conductive paths for the
EL7556D package are the fused leads: # 7, 9, 10, 11, 12, 18,
and 19. If a sufficient amount of PCB metal area is
connected to the fused package leads, a junction-to-ambient
thermal resistance of approximately 31°C/W can be
achieved (compared to 78°C/W for a standard SO28
package). The general relationship between PCB heatsinking metal area and the thermal resistance for this
package is shown in the Performance Curves section of this
data sheet. It can be readily seen that the thermal resistance
for this package approaches an asymptotic value of
approximately 31°C/W without any airflow.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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