DATASHEET

ES
EW D
®
NO
EL7562
IGNS
N
F OR
D
E
D
32
MEN EL75Sheet
COM SEEData
E
R
T
May 1, 2006
Monolithic 2Amp DC-DC Step-Down
Regulator
FN7295.1
Features
The EL7562 is an integrated, synchronous step-down
regulator with output voltage adjustable from 1.0V to 3.8V. It
is capable of delivering 2A continuous current at up to 95%
efficiency. The EL7562 operates at a constant frequency
pulse width modulation (PWM) mode, making external
synchronization possible. Patented on-chip resistorless
current sensing enables current mode control, which
provides cycle-by-cycle current limiting, over-current
protection, and excellent step load response. The EL7562 is
available in a fused-lead 16 Ld QSOP package. With proper
external components, the whole converter fits into a less
than 0.5 in2 area. The minimal external components and
small size make this EL7562 ideal for desktop and portable
applications.
• Integrated synchronous MOSFETs and current mode
controller
• 2A continuous output current
• Up to 95% efficiency
• 3.3V or 5V nominal input voltage
• Adjustable output from 1V to 3.8V
• Cycle-by-cycle current limit
• Precision reference
• ±0.5% load and line regulation
• Adjustable switching frequency to 1MHz
• Oscillator synchronization possible
• Internal soft-start
The EL7562 is specified for operation over the 0°C to +70°C
temperature range.
• Over-temperature protection
Pinout
• 16 Ld QSOP package
• Under-voltage lockout
• Pb-free plus anneal available (RoHS compliant)
EL7562
(16 LD QSOP)
TOP VIEW
Applications
• DSP, CPU core and IO supplies
• Logic/Bus supplies
C3
C4
0.1µF 270pF
1 SGND
PGND 16
• Portable equipment
C5
2 COSC
• DC-DC converter modules
VREF 15
R3
0.1µF R2
3 VDD
C1
100µF
C2
0.1µF
4 PGND
VDRV 13
5 PGND
LX 12
6 VIN
LX 11
7 VIN
VHI 10
8 EN
PGND 9
R1 2.37kΩ
1kΩ
Please refer to page 4 for 3.3V input Application Diagram
Manufactured under U.S. Patent No. 57,323,974
Ordering Information
VO
(3.3V,
2A)
100µF
C7
C6
0.1µF
VIN
(4.5V- 5.5V)
• GTL + Bus power supply
FB 14
39Ω
PART NUMBER
PART
TAPE &
MARKING REEL
EL7562CU
7562CU
-
16 Ld QSOP MDP0040
EL7562CU-T7
7562CU
7”
16 Ld QSOP MDP0040
EL7562CU-T13
7562CU
13”
16 Ld QSOP MDP0040
EL7562CUZ
(Note)
7562CUZ
-
16 Ld QSOP MDP0040
(Pb-free)
EL7562CUZ-T7
(Note)
7562CUZ
7”
16 Ld QSOP MDP0040
(Pb-free)
EL7562CUZ-T13 7562CUZ
(Note)
13”
16 Ld QSOP MDP0040
(Pb-free)
PACKAGE
PKG.
DWG. #
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage between VIN or VDD and GND . . . . . . . . . . . . +6.5V
VLX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN +0.3V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VDD +0.3V
VHI Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VLX +6V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Ambient Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER
VDD = VIN = 5V, TA = TJ = 25°C, COSC = 270pF, unless otherwise specified.
DESCRIPTION
VREF
Reference Accuracy
VREFTC
Reference Temperature Coefficient
VREFLOAD
Reference Load Regulation
VRAMP
Oscillator Ramp Amplitude
IOSC_CHG
Oscillator Charge Current
IOSC_DIS
CONDITIONS
MIN
TYP
MAX
UNIT
1.24
1.26
1.28
V
50
0 < IREF < 50µA
ppm/°C
-1
%
1.15
V
0.1V < VOSC < 1.25V
200
µA
Oscillator Discharge Current
0.1V < VOSC < 1.25V
8
mA
IVDD+VDRV
VDD+VDRV Supply Current
VEN = 4V, FOSC = 120kHz
IVDD_OFF
VDD Standby Current
EN = 0
VDD_OFF
VDD for Shutdown
VDD_ON
VDD for Startup
TOT
Over-temperature Threshold
135
°C
THYS
Over-temperature Hysteresis
20
°C
ILEAK
Internal FET Leakage Current
ILMAX
Peak Current Limit
RDSON
FET On Resistance
RDSONTC
RDSON Tempco
VFB
Output Initial Accuracy
ILOAD = 0A
VFB_LINE
Output Line Regulation
VIN = 5V, ΔVIN = 10%, ILOAD = 0A
0.5
%
VFB_LOAD
Output Load Regulation
0.1A < ILOAD < 1A
0.5
%
VFB_TC
Output Temperature Stability
-40°C < TA < 85°C, ILOAD = 0.5A
±1
%
IFB
Feedback Input Pull Up Current
VFB = 0V
100
VEN_HI
EN Input High Level
(Note)
VEN_LO
EN Input Low Level
IEN
Enable Pull Up Current
6.5
mA
1.5
mA
2.5
2.7
V
2.6
3
V
1
EN = 0, LX = 5V (low FET), LX = 0V (high
FET)
20
3
Wafer level test only
60
0.970
120
0.985
1.000
200
4
-4
mΩ
mΩ/°C
V
nA
V
1
VEN = 0
µA
A
0.2
NOTE: VEN_HI is typically 2/3 of VDD. For VDD = 3.3V, VEN_HI is 2.2V typical.
2
2
-2.5
V
µA
Closed-Loop AC Electrical Specifications
PARAMETER
VS = VIN = 5V, TA = TJ = 25°C, COSC = 270pF, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
493
580
667
kHz
FOSC
Oscillator Initial Accuracy
tSYNC
Minimum Oscillator Sync Width
25
ns
MSS
Soft-start Slope
0.5
V/ms
tBRM
FET Break Before Make Delay
15
ns
tLEB
High Side FET Minimum On Time
150
ns
DMAX
Maximum Duty Cycle
95
%
Pin Descriptions
PIN
NUMBER
PIN NAME
1
SGND
Control circuit negative supply
2
COSC
Oscillator timing capacitor; FOSC can be approximated by: FOSC (kHz) = 0.1843/COSC, COSC in µF
3
VDD
4
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
5
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
6
VIN
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
7
VIN
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
8
EN
Chip enable, active high; a 2µA internal pull-up current enables the device if the pin is left open
9
PGND
10
VHI
Positive supply of the high-side driver
11
LX
Inductor drive pin; high current digital output whose average voltage equals the regulator output voltage
12
LX
Inductor drive pin; high current digital output whose average voltage equals the regulator output voltage
13
VDRV
14
FB
15
VREF
Bandgap reference bypass capacitor; typically 0.1µF to GND
16
PGND
Ground return of the regulator
PIN FUNCTION
Control circuit positive supply
Ground return of the regulator
Positive supply of the low-side driver and input voltage for the high-side boot strap
Voltage feedback input; connected to an external resistor divider between VOUT and GND; a 125nA pull-up current
forces VOUT to VS in the event that FB is floating
3
Application Diagram for 3.3V Input
C3
C4
0.1µF
270pF
1 SGND
PGND 16
C5
2 COSC
VREF 15
0.1µF
R3
3 VDD
FB 14
39Ω
C1
C2
100µF
0.1µF
VIN
(3V-3.6V)
4 PGND
VDRV 13
5 PGND
LX 12
D3
D4
C8
C9
0.1µF
0.1µF
VO
(2.5V, 2A)
L1
6 VIN
LX 11
7 VIN
VHI 10
8 EN
PGND 9
EL7562
(16 Ld QSOP)
4
D2
C6
0.1µF
4.7µF
C7
R2
100µF
1.54kΩ
R1
1kΩ
Typical Performance Curves
Efficiency vs IO
VIN=5V
Power Loss vs IO
VIN=5V
100
0.7
VO=2.5
95
VO=3.3
0.6
85
VO=1.8
80
VO=1.5
Power Loss (W)
Efficiency (%)
90
VO=1.2
75
70
FS=500kH
65
0.5
VO=3.3
0.4
VO=2.5
0.3
VO=1.8
VO=1.2
0.2
VO=1.5
0.1
L=Coilcraft DO3316P60
0.1
0
1
2
0
0.5
LOAD CURRENT IO (A)
2
1.5
2
Load Regulation
VO=3.3V
100
0.8
VIN=4.5
95
0.6
85
Output Voltage (%)
VIN=5V
90
Efficiency (%)
1.5
(A)
(A)
LOAD
LoadCURRENT
Current IOIO
Efficiency vs IO
VO=3.3V
VIN=5.5
80
75
70
VIN=5.5
0.4
0.2
VIN=5V
0
VIN=4.5
-0.2
-0.4
65
-0.6
60
0
0.5
1
1.5
0
2
0.5
LOAD CURRENT IO (A)
1
LOAD CURRENT IO (A)
Line Regulation
VO=3.3V
VREF vs Temperature
0.6
1.258
1.256
0.4
IO=0.1A
1.254
VREF (V)
0.2
VO (%)
1
IO=1A
0
IO=2A
-0.2
1.252
1.25
1.248
1.246
-0.4
-0.6
4.5
1.244
1.242
4.7
4.9
5.1
VIN (V)
5
5.3
5.5
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
80
90 100 110
Typical Performance Curves
(Continued)
Input Current vs Temperature
(Enable connected to GND)
Oscillator Frequency vs Temperature
0.96
390
0.92
380
375
370
VIN=5V
0.9
VIN=4.5
0.88
0.86
0.84
365
0.82
360
0.8
0
10
20
30
40
50
60
70
80
90 100 110
TEMPERATURE (°C)
1400
1200
1000
800
600
400
200
0
0
200
400
600
COSC (pF)
6
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
Switching Frequency vs COSC
FS (kHz)
VIN=5.5
0.94
385
Input Current (A)
Oscillator Frequency (kHz)
COSC=390p
800
1000
80
90 100 110
Block Diagram
0.1µF
VREF
Junction
Temperature
Voltage
Reference
270pF
COSC
VDRV
Oscillator
VHI
Controller
Supply
39Ω
5V
VDD
VIN
0.1µF
Power
0.1µF
PWM
Controlle
FET
4.7µH
Drivers
VOUT
Power
100µF
FET
PGND
EN
2370Ω
1kΩ
Current
Sense
SGND
FB
Applications Information
Circuit Description
General
The EL7562 is a fixed frequency, current mode controlled
DC-DC converter with integrated N-channel power
MOSFETs and a high precision reference. The device
incorporates all the active circuitry required to implement a
cost effective, user-programmable 2A synchronous stepdown regulator suitable for use in DSP core power supplies.
Theory of Operation
The EL7562 is composed of 5 major blocks:
1. PWM Controller
2. NMOS Power FETs and Drive Circuitry
3. Bandgap Reference
4. Oscillator
5. Thermal Shut-down
PWM Controller
The EL7562 regulates output voltage through the use of
current-mode controlled pulse width modulation. The three
main elements in a PWM controller are the feedback loop
and reference, a pulse width modulator whose duty cycle is
controlled by the feedback error signal, and a filter which
7
averages the logic level modulator output. In a step-down
(buck) converter, the feedback loop forces the timeaveraged output of the modulator to equal the desired output
voltage. Unlike pure voltage-mode control systems, currentmode control utilizes dual feedback loops to provide both
output voltage and inductor current information to the
controller. The voltage loop minimizes DC and transient
errors in the output voltage by adjusting the PWM duty-cycle
in response to changes in line or load conditions. Since the
output voltage is equal to the time-averaged of the modulator
output, the relatively large LC time constant found in power
supply applications generally results in low bandwidth and
poor transient response. By directly monitoring changes in
inductor current via a series sense resistor the controller's
response time is not entirely limited by the output LC filter
and can react more quickly to changes in line and load
conditions. This feed-forward characteristic also simplifies
AC loop compensation since it adds a zero to the overall
loop response. Through proper selection of the currentfeedback to voltage-feedback ratio the overall loop response
will approach a one-pole system. The resulting system offers
several advantages over traditional voltage control systems,
including simpler loop compensation, pulse by pulse current
limiting, rapid response to line variation and good load step
response.
The heart of the controller is an input direct summing
comparator which sum voltage feedback, current feedback,
slope compensation ramp and power tracking signals
together. Slope compensation is required to prevent system
instability that occurs in current-mode topologies operating
at duty-cycles greater than 50% and is also used to define
the open-loop gain of the overall system. The slope
compensation is fixed internally and optimized for 500mA
inductor ripple current. The power tracking will not contribute
any input to the comparator steady-state operation. Current
feedback is measured by the patented sensing scheme that
senses the inductor current flowing through the high-side
switch whenever it is conducting. At the beginning of each
oscillator period the high-side NMOS switch is turned on.
The comparator inputs are gated off for a minimum period of
time of about 150ns (LEB) after the high-side switch is
turned on to allow the system to settle. The Leading Edge
Blanking (LEB) period prevents the detection of erroneous
voltages at the comparator inputs due to switching noise. If
the inductor current exceeds the maximum current limit
(ILMAX) a secondary over-current comparator will terminate
the high-side switch on time. If ILMAX has not been reached,
the feedback voltage FB derived from the regulator output
voltage VOUT is then compared to the internal feedback
reference voltage. The resultant error voltage is summed
with the current feedback and slope compensation ramp.
The high-side switch remains on until all four comparator
inputs have summed to zero, at which time the high-side
switch is turned off and the low-side switch is turned on.
However, the maximum on-duty ratio of the high-side switch
is limited to 95%. In order to eliminate cross-conduction of
the high-side and low-side switches a 15ns break-beforemake delay is incorporated in the switch drive circuitry. The
output enable (EN) input allows the regulator output to be
disabled by an external logic control signal.
Output Voltage Setting
In general:
R ⎞
⎛
V OUT = 0.985 × ⎜ 1 + ------2-⎟
R 1⎠
⎝
NMOS Power FETs and Drive Circuitry
The EL7562 integrates low on-resistance (60mΩ) NMOS
FETs to achieve high efficiency at 2A. In order to use an
NMOS switch for the high-side drive it is necessary to drive
the gate voltage above the source voltage (LX). This is
accomplished by bootstrapping the VHI pin above the LX
voltage with an external capacitor CVHI and internal switch
and diode. When the low-side switch is turned on and the LX
voltage is close to GND potential, capacitor CVHI is charged
through internal switch to VDRV, typically 5V. At the
beginning of the next cycle the high-side switch turns on and
the LX pins begin to rise from GND to VIN potential. As the
LX pin rises the positive plate of capacitor CVHI follows and
eventually reaches a value of VDRV+VIN, typically 10V, for
VDRV=VIN=5V. This voltage is then level shifted and used to
drive the gate of the high-side FET, via the VHI pin. A value
of 0.1µF for CVHI is recommended.
Reference
A 1.5% temperature compensated bandgap reference is
integrated in the EL7562. The external VREF capacitor acts
as the dominant pole of the amplifier and can be increased
in size to maximize transient noise rejection. A value of
0.1µF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 95%.
Operating frequency can be adjusted through the COSC pin
or can be driven by an external source. If the oscillator is
driven by an external source care must be taken in selecting
the ramp amplitude. Since CSLOPE value is derived from the
COSC ramp, changes to COSC ramp will change the
CSLOPE compensation ramp which determine the open-loop
gain of the system.
When external synchronization is required, always choose
COSC such that the free-running frequency is at least 20%
lower than that of sync source to accommodate component
and temperature variations. Figure 1 shows a typical
connection.
For VIN = 5V
100p
R ⎞
⎛
V OUT = 0.975 × ⎜ 1 + ------2-⎟
R 1⎠
⎝
External
Oscillato
1
16
2
15
3
14
6
11
7
10
8
9
BAT54
FOR VIN = 3.3V
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loopgain is changed. This is shown in the performance curves. A
100nA pull-up current from FB to VDD forces VOUT to GND
in the event that FB is floating.
EL7562
FIGURE 1. OSCILLATOR SYNCHRONIZATION
8
Thermal Shut-down
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the system is in fault state and will be shut
down. The upper and low trip-points are set to 135°C and
115°C respectively.
The demo board is a good example of layout based on these
principles. Please refer to the EL7562 Application Brief for
the layout.
Start-up Delay
A capacitor can be added to the EN pin to delay the
converter start-up (Figure 2) by utilizing the pull-up current.
The delay time is approximately:
t d ( ms ) = 1200 × C ( μF )
1
1
2
1
3
1
6
1
7
1
8
C
VOU
VIN
VO
td
9
EL7562
TIME
FIGURE 2. START-UP DELAY
Layout Considerations
The layout is very important for the converter to function
properly. Power Ground (
) and Signal Ground (--)
should be separated to ensure that the high pulse current in
the Power Ground never interferes with the sensitive signals
connected to Signal Ground. They should only be connected
at one point (normally at the negative side of either the input
or output capacitor).
The trace connected to pin 14 (FB) is the most sensitive
trace. It needs to be as short as possible and in a “quiet”
place, preferably between PGND or SGND traces.
In addition, the bypass capacitor connected to the VDD pin
needs to be as close to the pin as possible.
The heat of the chip is mainly dissipated through the PGND
pins. Maximizing the copper area around these pins is
preferable. In addition, a solid ground plane is always helpful
for the EMI performance.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
Similar pages