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Data
Sheet
February 19, 2014
T
N
1-888-I
ISL6455, ISL6455A
Triple Output Regulator with Single
Synchronous Buck and Dual LDO
Features
The ISL6455 is a highly integrated triple output regulator
which provides a single chip solution for FPGAs and wireless
chipset power management. The device integrates an
adjustable high efficiency synchronous buck regulator with
two adjustable ultra low noise LDO regulators. Either the
ISL6455 or ISL6455A can be selected based on whether
3.3V ±10% or 5V ±10% is required as an input voltage.
• PWM output voltage adjustable.
- 0.8V to 2.5V with ISL6455 (VIN = 3.3V)
- 0.8V to 3.3V with ISL6455A (VIN = 5.0V)
• Fully integrated synchronous buck regulator + dual LDO
The synchronous current mode control PWM regulator with
integrated N- Channel and P-Channel power MOSFET
provides adjustable voltages based on external resistor
setting. Synchronous rectification with internal MOSFETs is
used to achieve higher efficiency and reduced number of
external components. Operating frequency is typically
750kHz, allowing the use of smaller inductor and capacitor
values. The device can be synchronized to an external clock
signal in the range of 500kHz to 1MHz. The PG_PWM
output indicates loss of regulation on PWM output.
The ISL6455 also has two LDO adjustable regulators using
internal PMOS transistors as pass devices. LDO2 features
ultra low noise typically below 30µVRMS to aid VCO stability.
The EN_LDO pin controls LDO1 and LDO2 outputs. The
ISL6455 also integrates a RESET function, which eliminates
the need for additional RESET IC required in WLAN and
other applications. The IC asserts a RESET signal whenever
the VIN supply voltage drops below a preset threshold,
keeping it asserted for at least 25ms after VIN has risen
above the reset threshold. The PG_LDO output indicates
loss of regulation on either of the two LDO outputs. Other
features include overcurrent protection and thermal
shutdown for all of the three outputs. High integration and
the thin Quad Flat No-lead (QFN) package makes ISL6455
an ideal choice for powering FPGAs and small form factor
wireless cards such as PCMCIA, mini-PCI and Cardbus-32.
Ordering Information
• High output current. . . . . . . . . . . . . . . . . . . . . . . . . 600mA
• Dual LDO adjustable options
- LDO1, 1.2V to Vin - 0.3V (3.3Vmax). . . . . . . . . . 300mA
- LDO2, 1.2V to Vin - 0.3V (3.3Vmax). . . . . . . . . . 300mA
• Ultra-compact DC/DC converter design
• Stable with small ceramic output capacitors and no load
• High conversion efficiency
• Low shutdown supply current
• Low dropout voltage for LDOs
- LDO1 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA
- LDO2 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA
• Low output voltage noise
- <30µVRMS (typical) for LDO2 (VCO supply)
• PG_LDO and PG_PWM (PWM and LDO) outputs
• Extensive circuit protection and monitoring features
- PWM overvoltage protection
- Overcurrent protection
- Shutdown
- Thermal shutdown
• Integrated RESET output for microprocessor reset
• Proven reference design for total WLAN system solution
• QFN package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale package footprint Improves PCB
efficiency and is thinner in Profile
• Pb-free (RoHS compliant)
PART NUMBER*
PART
TEMP.
PACKAGE
(Note)
MARKING RANGE (°C) (Pb-Free)
PKG.
DWG. #
ISL6455IRZ
64 55IRZ
-40 to +85
24 Ld QFN L24.4x4B
ISL6455AIRZ
64 55AIRZ
-40 to +85
24 Ld QFN L24.4x4B
Add “-TK” or T5K suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
1
FN9196.1
Applications
• WLAN cards
- PCMCIA, Cardbus32, MiniPCI cards
- Compact flash cards
• Hand-held instruments
Related Literature
• TB363 - Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)
• TB389 - PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6455, ISL6455A
Pinout
EN_LDO
PG_LDO
VIN
PVCC
LX
PGND
ISL6455, ISL6455A (24 LD QFN)
TOP VIEW
24
23
22
21
20
19
18 GND
1
SGND
FB_LDO2 2
17 CT
4
15
GND_LDO
5
14 EN
VOUT1
6
13 SYNC
9
10
11
RESET
12
PG_PWM
8
FB_PWM
7
CC2
CC1
VOUT2
16 VOUT
VIN_LDO
3
VIN_LDO
FB_LDO1
Typical Application Schematic
3.3V
C9
1.0µF
C10
10µF
L1
C8
8.2µH
1
33nF
3.3V
CC1
EN
R3
PG_LDO
10k
2
GND
PGND
LX
12
24
9
13
ISL6455
5
4
14
6
23
3
15
17
7
8
C5
4.7µF
10µF
18
16
10
2
VOUT
EN_LDO
VOUT2
GND_LDO
Vout2
C4
10µF
Ra
VOUT1
FB_LDO1
C3
10µF
Rb
Rc
Vout1
Rd
3.3V
C1
10nF
NOTE: All capacitors are ceramic.
Vopwm
C7
11
RESET
C2
19
FB_LDO2
SYNC
20
CC2
PG_PWM
21
VIN_LDO
Rf
22
VIN_LDO
FB_PWM
PVCC
10k
VIN
R1
CT
Re
SGND
0.1µF
C6
33nF
FN9196.1
February 19, 2014
ISL6455, ISL6455A
Functional Block Diagram
VIN_LDO
Gm
10nF
CT
RESET
VIN_LDO
BAND
GAP
REF
RESET
VIN_LDO
+
-
1.2V
3.3V
10k
POR
PG_LDO
VOUT1
VOUT1
LDO1
WINDOW
COMP.
POR
Rc
0
10µF
FB_LDO1
Rd
EN
CC1
EN_LDO
VOUT2
+
-
VOUT2
LDO2
THERMAL
SHUTDOWN
+150°C
RTN
CC2
33nF
GND_LDO
VIN
33nF
Gm
CONTROL
LOGIC
Ra
WINDOW
COMP.
0
10µF
FB_LDO2
Rb
VIN
PVCC
3.3V
CURRENT
SENSE
SGND
SLOPE
COMPENSATION
SOFTSTART
EN
FB_PWM
EA
GM
PWM
OVERCURRENT,
OVERVOLTAGE
LOGIC
8.2µH
LX
GATE
DRIVE
VOUT
10µF
COMPENSATION
PGND
750kHz
OSCILLATOR
Re
EN
POWER GOOD
PWM
VOUT
GND
Rf
UVLO
PWM
REFERENCE
0.45V
VOUT
SYNC
3.3V
10k
EN
PG_PWM
3.3V
10k
10k
3
FN9196.1
February 19, 2014
ISL6455, ISL6455A
Absolute Maximum Ratings
Thermal Information
Supply Voltage VIN, PVCC, VIN _LDO. . . . . . . . GND -0.3V to +6.0V
Max Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . 600mA
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
24 Ld QFN (Note 1) . . . . . . . . . . . . . . .
42
6
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature Range . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V for ISL6455 and
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = -40°C to +85° (Note 2),
typical values are at TA = +25°C.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless
otherwise specified. Temperature limits established by characterization and are not production tested
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6455
3.0
3.3
3.6
V
ISL6455A
4.2
5.0
5.5
V
3.0
-
5.5
V
VCC SUPPLY
VIN_PWM Supply Voltage Range
VIN_LDO Supply Voltage Range
Operating Supply Current (Note 4) for ISL6455
VIN = VIN_LDO = PVCC = 3.3V
fSW = 750kHz, COUT = 10µF, IL = 0mA
-
2.5
3.1
mA
Operating Supply Current (Note 4) for ISL6455A
VIN = VIN_LDO = PVCC = 5.0V
fSW = 750kHz, COUT = 10µF, IL = 0mA
-
3.5
4.5
mA
Shutdown Supply Current
ISL6455 and ISL6455A
EN = EN_LDO = GND
-
5
10
µA
Input Bias Current (EN pin)
EN = EN_LDO = GND/VIN
-1.5
1.0
1.5
µA
VIN_PWM UVLO Threshold for ISL6455
VTR
2.55
2.65
2.71
V
VTF
2.51
2.56
2.61
V
VTR
3.94
4.05
4.13
V
VTF
3.78
3.89
3.97
V
VIN_LDO UVLO Threshold for ISL6455 and
ISL6455A
VTR
2.46
2.64
2.82
V
VTF
2.53
2.59
2.66
V
Thermal Shutdown Temperature (Note 6)
Rising Threshold
-
150
-
°C
-
20
-
°C
ISL6455
0.8
-
2.5
V
ISL6455A
0.8
-
3.3
V
FB_PWM Initial Voltage Accuracy (Note 7)
VREF = 0.45V, IOUT = 3mA, TA = -40°C to +85°C
-0.9
-
0.9
%
FB_PWM Line Regulation
IO = 3mA, VIN = PVCC = 3.0V - 3.6V (ISL6455)
or 4.2V - 5.5V (6455A)
-0.5
-
0.5
%
FB_PWM Load Regulation
IO = 3mA to 500mA, VIN = PVCC = 3.0V - 3.6V
(ISL6455) or 4.2V - 5.5V (ISL6455A)
-1.1
-
+1.1
%
700mA
-
1300
mA
-
170
-
m
VIN_PWM UVLO Threshold for ISL6455A
Thermal Shutdown Hysteresis (Note 6)
SYNCHRONOUS BUCK PWM REGULATOR
Output Voltage
Peak Output Current Limit
IOUT = 200mA
PMOS rDS(ON)
4
FN9196.1
February 19, 2014
ISL6455, ISL6455A
Electrical Specifications
Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V for ISL6455 and
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = -40°C to +85° (Note 2),
typical values are at TA = +25°C.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless
otherwise specified. Temperature limits established by characterization and are not production tested
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
NMOS rDS(ON)
IOUT = 200mA
-
50
-
m
Efficiency
IOUT = 200mA, VIN = 3.3V, VOUT = 1.8V
-
93
-
%
Soft-Start Time
4096 Clock Cycles @ 750kHz
-
5.5
-
ms
OSCILLATOR
Oscillator Frequency
TA = -40°C to +85°C
620
750
880
kHz
Frequency Synchronization Range (fSYNC)
Clock signal on SYNC pin
500
-
1000
kHz
SYNC High Level Input Voltage
As % of VIN
70
-
-
%
SYNC Low Level Input Voltage
As % of VIN
-
-
30
%
Sync Input Leakage Current
SYNC = GND or VIN
-1.0
-
1.0
A
Min Duty Cycle of External Clock Signal (Note 6)
-
20
-
%
Max Duty Cycle of External Clock Signal (Note 6)
-
80
-
%
PG_PWM
Rising Threshold
1.2mA source/sink, FB_PWM vs 0.45V VREF
+5.5
8.0
+10.5
%
Falling Threshold
FB_PWM vs 0.45V VREF
-10.5
-8.0
-5.5
%
Leakage Current
PG_PWM = GND or VIN
-
0.01
0.1
A
LDO1 SPECIFICATIONS
Output Voltage Range
VIN_VLDO > 3.0V
1.2
-
2.7
V
Output Voltage Range
VIN_VLDO > 3.6V
1.2
-
3.3
V
FB_LDO1 Voltage Accuracy (Note 7)
IOUT = 10mA
-1.5
-
1.5
%
Maximum Output Current (Note 6)
VIN = 3.6V
300
-
-
mA
350
420
600
mA
-
150
300
mV
Output Current Limit (Note6)
Dropout Voltage (Note 4)
IOUT = 300mA
FB_LDO1 Line Regulation
IOUT = 10mA, VIN_LDO = 3.0-5.5V
-0.5
-
0.5
%/V
FB_LDO1 Load Regulation
IOUT = 10mA to 300mA
-0.5
-
0.5
%
Output Voltage Noise (Note 6)
10Hz < f < 100kHz, IOUT = 10mA
COUT = 2.2µ2F
-
65
-
VRMS
COUT = 10µF
-
60
-
VRMS
LDO2 SPECIFICATIONS
Output Voltage Range
VIN_VLDO > 3.0V
1.2
-
2.7
V
Output Voltage Range
VIN_VLDO > 3.6V
1.2
-
3.3
V
FB_LDO2 Voltage Accuracy (Note 7)
IOUT = 10mA
-1.5
-
1.5
%
Maximum Output Current (Note 6)
VIN = 3.6V
300
-
-
mA
350
420
600
mA
-
150
300
mV
Output Current Limit (Note 6)
Dropout Voltage (Note 4)
IOUT = 300mA
FB_LDO2 Line Regulation
IOUT = 10mA, VIN_LDO = 3.0V - 5.5V
-0.5
-
0.5
%/V
FB_LDO2 Load Regulation
IOUT = 10mA to 300mA
-0.5
-
0.5
%
5
FN9196.1
February 19, 2014
ISL6455, ISL6455A
Electrical Specifications
Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V for ISL6455 and
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = -40°C to +85° (Note 2),
typical values are at TA = +25°C.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless
otherwise specified. Temperature limits established by characterization and are not production tested
PARAMETER
TEST CONDITIONS
Output Voltage Noise (Note 6)
MIN
TYP
MAX
UNITS
COUT = 2.2µF
-
30
-
µVRMS
COUT = 10µF
-
20
-
µVRMS
10Hz < f < 100kHz, IOUT = 10mA
ENABLE (EN and (EN_LDO)
EN High Level Input Voltage
As % of VIN
70
-
-
%
EN Low Level Input Voltage
As % of VIN
-
-
30
%
0.8 x
VCC
-
-
V
-
-
0.3
V
RESET BLOCK SPECIFICATIONS
RESET (reset released)
ISL6455, ISOURCE = 500µA, VIN = 2.90V
RESET (reset asserted)
ISL6455, ISINK = 1.2mA, VIN = 2.50V
RESET Rising Threshold
ISL6455
2.71
2.77
2.84
V
RESET Falling Threshold
ISL6455
2.69
2.75
2.81
V
RESET (reset released)
ISL6455A, ISOURCE = 800µA, VIN = 4.70V
0.8 x
VCC
-
-
V
RESET (reset asserted)
ISL6455A, ISINK = 3.2mA, VIN = 4.10V
-
-
0.4
V
RESET Rising Threshold
ISL6455A
4.19
4.27
4.35
V
RESET Falling Threshold
ISL6455A
4.16
4.24
4.32
V
RESET Threshold Hysteresis
ISL6455
-
20
-
mV
RESET Threshold Hysteresis
ISL6455A
-
30
-
mV
RESET Active Timeout Period (Note 5)
CT = 0.01µF
-
25
-
ms
-
1.2
-
V
+11
+15
+17
%
-17
-15
-11
%
POWER GOOD (PG_LDO)
Minimum Input Voltage for Valid PG_LDO
PGOOD Threshold (Rising)
FB_LDO vs 1.184V VREF
PGOOD Threshold (Falling)
PGOOD Output Voltage Low
IOL = 1.2mA
-
-
0.4
V
PGOOD Output Leakage Current
PG_LDO = GND or VIN
-
0.01
0.1
µA
FB_PWM vs 0.45V VREF
28
31
34
%
PWM OUTPUT OVERVOLTAGE
Overvoltage Threshold
NOTES:
3. This is the VIN current consumed when the device is active but not switching. Does not include gate drive current.
4. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V.
5. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01µF) the RESET time is 25ms; at 1000nF (0.1µF) the
RESET time would be 250ms.
6. Limits established by characterization and are not production tested.
7. Add the external feedback resistor mismatch error to get initial VOUT accuracy.
6
FN9196.1
February 19, 2014
ISL6455, ISL6455A
PG_LDO Timing Diagram
VIN
VUVLO
VUVLO
VPG
VPG
t
RISING
MAX +18%
VFB_LDO
PG_LDO
THRESHOLD
VOLTAGE
FALLING
MIN -17%
t
PG_LDO
OUTPUT
OUTPUT
UNDEFINED
OUTPUT
UNDEFINED
t
NOTE:
8. VPG is the minimum input voltage for a valid PG_LDO.
7
FN9196.1
February 19, 2014
ISL6455, ISL6455A
Pin Descriptions
PVCC - Positive supply for the power (internal FET) stage of
the PWM section.
SGND - Analog ground for the PWM. All internal control
circuits are referenced to this pin.
EN - The PWM controller is enabled when this pin is HIGH,
and disabled when the pin is pulled LOW. It is a CMOS
logic-level input (referenced to VIN).
VIN_LDO - This is the input voltage pin for LDO1 and LDO2.
EN_LDO - LDO1 and LDO2 are enabled when this pin is
HIGH, and disabled when the pin is pulled LOW. It is a
CMOS logic-level input (referenced to VIN).
CT - Timing capacitor pin to set the 25ms minimum pulse
width for the RESET signal.
RESET - This pin is the output of the reset supervisory
circuit, which monitors VIN_PWM. The IC asserts a RESET
signal whenever the supply voltage drops below a preset
threshold. It is kept asserted for a minimum of 25ms after
VCC (VIN) has risen above the reset threshold. The output is
push-pull. The device will continue to operate until VIN drops
below the UVLO threshold.
When EN = LOW then RESET = HIGH and the moment EN
is made HIGH the RESET will pulse LOW for a period of
25ms minimum (VIN > Reset threshold). If VIN < reset
threshold then it will switch low and stay low for a period of
25ms after VIN_PWM crosses the reset threshold.
PG_LDO - This is a high impedance open drain output that
provides the status of both LDOs. When either of the outputs
are out of regulation, PG_LDO goes LOW. Add a pull-up
resistor approximately 10k from PG_LDO to VIN.
CC1 - This is the compensation capacitor connection for
LDO1. Connect a 0.033µF capacitor from CC1 to
GND_LDO.
VOUT2 - This pin is the output of LDO2. Bypass with a
minimum 2.2µF, low ESR capacitor to GND_LDO for stable
operation.
GND_LDO - Ground pin for LDO1 and LDO2.
VOUT1 - This pin is the output of LDO1. Bypass with a
minimum 2.2µF, low ESR capacitor to GND_LDO for stable
operation.
PGND - Power ground for the PWM controller stage.
VOUT - This I/O pin senses the output voltage of the PWM
converter for the purpose of detecting the over and
undervoltage conditions.
PG_PWM - This pin is an active pull-down able to sink 1mA
(min). This output is HIGH IMPEDANCE when VOUT is
within ±8% (typical). For pull-up, add a resistor
approximately 10k from PG_PWM to VIN
FB_LDO1 and FB_LDO2 - These pins are used to set the
LDO output with the proper selection of resistors. i.e. Ra and
Rb for LDO1 and Rc and Rd for LDO2. Resistors should be
chosen to provide a minimum current of 200µA load for each
LDO output.
LX - The LX pin is the switching node of synchronous buck
converter, connected internally at the junction point of the
upper MOSFET source and lower MOSFET drain. Connect
this pin to the output inductor.
VIN - This pin is the power supply for the PWM controller
stage and must be closely decoupled to ground.
SYNC - This is the external clock synchronization input. The
device can be synchronized to 500kHz to 1MHz switching
frequency. If unused then it should be tied to GND or VCC
GND - Tie this pin to the ground plane with a low impedance,
shortest possible path.
FB_PWM- This is used to set the value of the output voltage
of the PWM with external resistors Re and Rf.
CC2 - This is the compensation capacitor connection for
LDO2. Connect a 0.033µF capacitor from CC2 to
GND_LDO.
8
FN9196.1
February 19, 2014
ISL6455, ISL6455A
Functional Description
The ISL6455 is a 3-in-1 multi-output regulator designed for
FPGA and wireless chipset power applications. The device
integrates a single synchronous buck regulator with dual
LDOs. The PWM output can be set by choosing appropriate
values for Re and Rf. At a setting of 1.8V the synchronous
buck regulator provides for an efficiency greater than 92%.
The LDO1 can be set with resistor pair Rc and Rd. The
LDO2 can be set with the resistor pair Ra and Rb.
Undervoltage lock-out (UVLO) prevents the converter from
turning on when the input voltage is less than 2.6V typical.
Additional blocks include output overcurrent protection,
thermal sensor, PGOOD detectors, RESET function and
shutdown logic.
Synchronous Buck Regulator
The synchronous buck regulator with integrated N-Channel
and P-Channel power MOSFETs and external voltage
setting resistors provides for adjustable voltages from the
PWM. Synchronous rectification with internal MOSFETs is
used to achieve higher efficiency and reduced number of
external components. Operating frequency is typically
750kHz allowing the use of smaller inductor and capacitor
values. The device can be synchronized to an external clock
signal in the range of 500kHz to 1MHz. The PG_PWM
output indicates loss of regulation on PWM output.
The PWM architecture uses a peak current mode control
scheme with internal slope compensation. At the beginning
of each clock cycle, the high side P-channel MOSFET is
turned on. The current in the inductor ramps up and is
sensed via an internal circuit. The error amplifier sets the
threshold for the PWM comparator. The high side switch is
turned off when the sensed inductor current reaches this
threshold. After a minimum dead time preventing shoot
through current, the low side N-Channel MOSFET will be
turned on, and the current ramps down again. As the clock
cycle is completed, the low side switch will be turned off and
the next clock cycle starts.
The control loop is internally compensated reducing the
amount of external components.
The switch current is internally sensed and the maximum
peak current limit is 1300mA.
Synchronization
The typical operating frequency for the converter is 750kHz
if no clock signal is applied to SYNC pin. It is possible to
synchronize the converter to an external clock within a
frequency range from 500kHz to 1MHz. The device
automatically detects the rising edge of the first clock and
will synchronize immediately to the external clock. If the
clock signal is stopped, the converter automatically switches
back to the internal clock and continues operation without
interruption. The switch-over will be initiated if no rising edge
9
on the SYNC pin is detected for a duration of two internal
1.3µs clock cycles.
Soft-Start
As the EN (Enable) pin goes high, the soft-start function will
generate an internal voltage ramp. This causes the start-up
current to slowly rise preventing output voltage overshoot
and high in-rush currents. The soft-start duration is typically
5.5ms with 750kHz switching frequency. When the soft-start
is completed, the error amplifier will be connected directly to
the internal voltage reference. The SYNC input is ignored
during soft-start.
Enable PWM
Logic low on EN pin forces the PWM section into shutdown.
In shutdown all the major blocks of the PWM including power
switches, drivers, voltage reference, and oscillator are
turned off.
Power Good (PG_PWM)
When chip is enabled, this output is asserted HIGH, when
VOUT is within 8% of VOPWM value and active low outside
this range. When the PWM is disabled, the output is active
low.
Leave the PG_PWM pin unconnected when not used.
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM
cycle. Should it exceed the overcurrent limit, a 4-bit up/down
counter counts up two LSB. Should it not be in overcurrent,
the counter counts down one LSB, (but the counter will not
"rollover" or count below 0000). If > 33% of the PWM cycles
go into overcurrent, the counter rapidly reaches count 1111
and the PWM output is shut down and the soft-start counter
is reset. After 16 clocks the PWM, output is enabled and the
SS cycle is started.
If VOUT exceeds the overvoltage limit for 32 consecutive
clock cycles, the PWM output is shut off and the SS counters
reset. The chip waits for the output voltage to go below
undervoltage (8% below nominal) then goes through two
dummy soft-start cycles (PWM disabled for 2 SS cycles =
11ms) and then starts a normal soft-start cycle.
PG_LDO
PG_LDO is an open drain pulldown NMOS output that will
sink 1mA at 0.4V maximum. It goes to the active low state if
either LDO output is out of regulation by a value greater than
15%. When the LDO is disabled, the output is active low.
LDO Regulators
Each LDO consists of a 1.184V reference, error amplifier,
MOSFET driver, P-Channel pass transistor, and dual-mode
comparator. The voltage is set by means of two resistors: the
Ra and Rb for LDO2 and Rc and Rd for LDO1. The 1.184V
band gap reference is connected to the error amplifier’s
inverting input. The error amplifier compares this reference
FN9196.1
February 19, 2014
ISL6455, ISL6455A
to the selected feedback voltage and amplifies the
difference. The MOSFET driver reads the error signal and
applies the appropriate drive to the P-Channel pass
transistor. If the feedback voltage is lower than the reference
voltage, the pass transistor gate is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the
pass transistor gate is driven higher, allowing less current to
pass to the output.
Internal P-Channel Pass Transistors
Both the LDO Regulators in ISL6455 feature a typical 0.5
rDS(on) P-channel MOSFET pass transistor. This provides
several advantages over similar designs using PNP bipolar
pass transistors. The P-Channel MOSFET requires no base
drive, which reduces quiescent current considerably. PNP
based regulators waste considerable current in dropout
when the pass transistor saturates. They also use high base
drive currents under large loads. The ISL6455 does not have
these drawbacks.
Integrated RESET for MAC/Baseband Processors
The ISL6455 includes a microprocessor supervisory block.
This block eliminates an extra RESET IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the VIN_PWM supply voltage decreases below a
preset threshold, and keeps it asserted for a programmable
time period set by the external capacitor CT.
UVLO Reset threshold is always lower than the RESET
threshold. This insures that as VIN falls, the reset goes low
before the LDOs and PWM are shut off.
Integrator Circuitry
Both ISL6455 LDO Regulators use external 33nF
compensation capacitors for minimizing load and line
regulation errors and for lowering output noise. When the
output voltage shifts due to varying load current or input
voltage, the integrator capacitor voltage is raised or lowered
to compensate for the systematic offset at the error amplifier.
Compensation is limited to ±5% to minimize transient
overshoot when the device goes out of dropout, current limit,
or thermal shutdown.
Shutdown
Driving the EN_LDO pin low will put LDO1 and LDO2 into
the shutdown mode. Driving the EN pin low will put the PWM
into shutdown mode. Pulling both the EN and EN_LDO pins
low simultaneously, puts the ISL6455, ISL6455A in a
shutdown mode, and supply current drops to 15µA typical.
Protection Features for the LDOs
Current Limit
The ISL6455 and ISL6455A monitor and control the pass
transistor’s gate voltage to limit the output current. The
current limit for both LDO1 and LDO2 is 330mA. The output
10
can be shorted to ground without damaging the part due to
the current limit and thermal protection features.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL6455, ISL6455A. When the junction temperature (TJ)
exceeds +150°C, the thermal sensor sends a signal to the
shutdown logic, turning off the pass transistor and allowing
the IC to cool. The pass transistor turns on again after the
IC’s junction temperature typically cools by +20°C, resulting
in an intermittent output condition during continuous thermal
overload. Thermal overload protection protects the ISL6455,
ISL6455A against fault conditions. For continuous operation,
the absolute maximum junction temperature rating of
+150°C in not to be exceeded.
Operating Region and Power Dissipation
The maximum power dissipation of ISL6455 depends on the
thermal resistance of the IC package and circuit board, the
temperature difference between the die junction and ambient
air, and the rate of air flow. The power dissipated in the
device is:
PT = P1 + P2 + P3, where:
P1 = IOUT1 x VOUT1 x n, n is the efficiency of the PWM
P2 = IOUT2 (VIN – VOUT2)
P3 = IOUT3 (VIN- VOUT3)
The maximum power dissipation is:
Pmax = (Tjmax – TA)/JA
Where Tjmax = +150°C, TA = ambient temperature, and JA
is the thermal resistance from the junction to the surrounding
environment.
The ISL6455, ISL6455A package feature an exposed
thermal pad on its underside. This pad lowers the thermal
resistance of the package by providing a direct heat
conduction path from the die to the PC board. Additionally,
the ISL6455 and ISL6455A ground (GND_LDO and PGND)
performs the dual function of providing an electrical
connection to system ground and channeling heat away.
Connect the exposed bottom pad direct to the GND_LDO
ground plane.
Application Information
LDO Regulator Capacitor Selection and Regulator
Stability
Capacitors are required at the ISL6455, ISL6455A LDO
regulators’ input and output for stable operation over the
entire load range and the full temperature range. Use >1µF
capacitor at the input of LDO regulators, VIN_LDO pins. The
input capacitor lowers the source impedance of the input
supply. Larger capacitor values and lower ESR provide
better PSRR and line transient response. The input
FN9196.1
February 19, 2014
ISL6455, ISL6455A
capacitor must be located at a distance of not more than 0.5
inches from the VIN pins of the IC and returned to a clean
analog ground. Any good quality ceramic capacitor can be
used as an input capacitor.
The output capacitor must meet the requirements of
minimum amount of capacitance and ESR for both LDOs.
The ISL6455 is specifically designed to work with small
ceramic output capacitors. The output capacitor’s ESR
affects stability and output noise. Use an output capacitor
with an ESR of 50m or less to insure stability and optimum
transient response. For stable operation, a ceramic
capacitor, with a minimum value of 3.3µF, is recommended
for VOUT1 for 300mA output current, and 3.3µF is
recommended for VOUT2 at 300mA load current. There is no
upper limit to the output capacitor value. A larger capacitor
can reduce noise and improve load transient response,
stability and PSRR. A higher value output capacitor (10µF) is
recommended for LDO2 when used to power VCO circuitry
in wireless chipsets. The output capacitor should be located
very close to VOUT pins to minimize impact of PC board
inductances and the other end of the capacitor should be
returned to a clean analog ground.
PWM Regulator Component Selection
120m, its RMS ripple current rating will always meet the
application requirements. The RMS ripple current is
calculated as shown in Equation 1:
VO
1 – -------VI
1
I RMS  C  = V O  -----------------  ----------------Lf
O
2 3
(EQ. 1)
The overall output ripple voltage is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage
ripple caused by charge and discharging the output
capacitor as shown in Equation 2:
O
1 – V
------
VI 
1

V O = V O  -----------------   -------------------------- + ESR
 L  f  8  C  f

O




(EQ. 2)
Where the highest output voltage ripple occurs at the highest
input voltage.
TABLE 2. RECOMMENDED CAPACITORS
CAPACITOR
VALUE
ESR/m
10µF
<50
VENDOR PART
NUMBER
TDK
C2012X5R0J106M
COMMENTS
Ceramic
INDUCTOR SELECTION
A 8.2µH typical output inductor is used with the ISL6455 and
a 12µH typical with the ISL6455A PWM section. Values less
than this may cause stability problems because of the
internal compensation of the regulator. The important
parameters of the inductor that need to be considered are
the current rating of the inductor and the DC resistance of
the inductor. The DC resistance of the inductor will influence
directly the efficiency of the converter. Therefore, an inductor
with lowest DC resistance should be selected for highest
efficiency. In order to avoid saturation of the inductor, the
inductor should be rated at least for the maximum output
current plus the inductor ripple current. (See Table 1).
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a
pulsating input current, a low ESR input capacitor is required
for best input voltage filtering and minimizing the
interference with other circuits caused by high input voltage
spikes.
The input capacitor should have a minimum value of 10µF
and can be increased without any limit for better input
voltage filtering. The input capacitor should be rated for the
maximum input ripple current calculated as shown in
Equation 3:
TABLE 1. RECOMMENDED INDUCTORS
OUTPUT INDUCTOR
CURRENT
VALUE
VENDOR PART
NUMBER
COMMENTS
600mA
8.2µH
Coilcraft
MSS6122-822MX
ISL6455
600mA
12µH
Coilcraft
MSS6122-123MX
ISL6455A
V O
VO 
I RMS = I O  max   --------   1 – --------
VI 
VI 
(EQ. 3)
The worst case RMS ripple current occurs at D = 0.5.
OUTPUT CAPACITOR SELECTION
For the best performance, a low ESR output capacitor is
needed. If an output capacitor is selected with an ESR value
Ceramic capacitors show good performance because of
their low ESR value, and because they are less sensitive to
voltage transients, compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin
of the IC for best performance.
ISL6455, ISL6455A
Output Voltage Setting
The equations for the Output voltages are shown in Equation
4:
0.45
VOUT = -----------  Re + Rf 
Rf
1.184
VOUT1 = ---------------  Ra + Rb 
Rb
(EQ. 4)
1.184
VOUT2 = ---------------  Rc + Rd 
Rd
The output resistors should be selected so that the minimum
output load is about 200µA.
Layout Considerations
As for all switching power supplies, the layout is an important
step in the design of ISL6455, ISL6455A based power
supply due to the high switching frequency and low noise
LDO implementations.
Allocate two board levels as ground planes, with many vias
between them to create a low impedance, high-frequency
plane. Tie all the device ground pins through multiple vias
each to this ground plane, as close to the device as possible.
Also tie the exposed pad on the bottom of the device to this
ground plane.
Use wide and short traces for the high current paths. The
input capacitor should be placed as close as possible to the
IC pins as well as the inductor and output capacitor. Use a
common ground node to minimize the effects of ground
noise.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN9196.1
February 19, 2014
ISL6455, ISL6455A
Package Outline Drawing
L24.4x4B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4.00
4X 2.5
A
20X 0.50
B
PIN 1
INDEX AREA
PIN #1 CORNER
(C 0 . 25)
24
19
1
18
4.00
2 . 34 ± 0 . 15
13
0.15
(4X)
12
7
0.10 M C A B
0 . 07
24X 0 . 23 +- 0
. 05 4
24X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0 . 1
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 34 )
( 20X 0 . 5 )
C
0 . 2 REF
5
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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