DATASHEET

ESIGNS
FO R N E W D
D
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D
N
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M
M
A R TS
NOT RECO
ACEMENT P
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P
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RECOMMEN
ZL6105
ZL8101 and
Adaptive Digital DC/DC Controller with Current Sharing
ZL2004-01
Features
The ZL2004-01 is specialized version of the ZL2004 DC/DC
controller that has been optimized for high output accuracy
within a given set of operating conditions. The ZL2004-01 is
otherwise identical to the ZL2004 in features and functionality.
The ZL2004-01 has been optimized for use with the ZL1505
MOSFET driver and discrete MOSFETs.
• Power Conversion
The ZL2004-01 integrates a proprietary Digital-DC
communication bus for current sharing and inter device
communication. Adaptive algorithms improve light load
efficiency. All operating features can be configured by simple pinstrap selection, resistor selection or through the on-board serial
port. The PMBus™-compliant ZL2004-01 uses the SMBus™ serial
interface for communication with other Digital-DC products or a
host controller.
• Adaptive performance optimization algorithms
Related Literature
• Digital soft-start/stop
• Efficient synchronous buck controller
• ± 0.2% VOUT set-point accuracy
• 8.0V to 10.0V input range
• 0.9V to 1.1V output range
• Fast load transient response
• Active current sharing
• DCR current sensing with digitally adjustable current sense range
• RoHS compliant (5mmx5mm) QFN package
• Power Management
• Precision delay and ramp-up
• See FN6846, ZL2004 “Adaptive Digital DC-DC Controller with
Current Sharing”
• Power-good/enable
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• SMBus communication (PMBus compliant)
• Output voltage and current protection
• Internal non-volatile memory (NVM)
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
EN PG SS
V (0,1)
VMON
MGN
SYNC
FC
ILIM CFG FLEX
LDO
POWER
MANAGEMENT
DDC
SCL
SDA
SALRT
V25 VR VDD
NONVOLATILE
MEMORY
PWM
CONTROLLER
I2 C
MONITOR
ADC
SA (0,1)
VTRK
VSEN+/XTEMP
LEVEL
SHIFTER
PWMH
CURRENT
SENSE
ISENA
ISENB
PWML
TEMP
SENSOR
SGND DGND
FIGURE 1. BLOCK DIAGRAM
May 23, 2011
FN6847.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ZL2004-01
Ordering Information
PART NUMBER
(Notes 1, 4)
PART
MARKING
TEMP RANGE
(°C)
SHIPPING CONTAINER
PACKAGE
Tape & Reel
(Pb-free)
PKG. DWG. #
ZL2004ALNN-01 (Note 2)
2004-01
0 to +65
490 pieces
32 Ld QFN
L32.5x5D
ZL2004ALNNT-01 (Note 2)
2004-01
0 to +65
100 pieces
32 Ld QFN
L32.5x5D
ZL2004ALNNT1-01 (Note 2)
2004-01
0 to +65
1000 pieces
32 Ld QFN
L32.5x5D
ZL2004ALNF-01 (Note 3)
2004-01
0 to +65
490 pieces
32 Ld QFN
L32.5x5G
ZL2004ALNFT-01 (Note 3)
2004-01
0 to +65
100 pieces
32 Ld QFN
L32.5x5G
ZL2004ALNFT1-01 (Note 3)
2004-01
0 to +65
1000 pieces
32 Ld QFN
L32.5x5G
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ZL2004-01. For more information on MSL please see techbrief TB363.
Pin Configuration
2
PG
SS
EN
CFG
MGN
DDC
XTEMP
V25
ZL2004-01
(32 LD QFN)
TOP VIEW
32
31
30
29
28
27
26
25
DGND
1
24
VDD
SYNC
2
23
VR
SA0
3
22
PWMH
SA1
4
21
SGND
20
PWML
EXPOSED PADDLE
CONNECT TO SGND
18
ISENB
SALRT
8
17
NC
9
10
11
12
13
14
15
16
VSEN-
7
VSEN+
SDA
VRTK
ISENA
NC
19
VIMON
6
V1
SCL
V0
5
FC
ILIM
FN6847.2
May 23, 2011
ZL2004-01
Pin Descriptions
PIN
SYMBOL
TYPE
(Note 5)
1
DGND
PWR
2
SYNC
I/O, M
(Note 6)
Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external
clock or to output internal clock.
3
SA0
I, M
4
SA1
Serial address select pins. Used to assign unique address for each individual device or to enable certain
management features.
5
ILIM
I, M
Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB.
6
SCL
I/O
Serial clock. Connect to external host and/or to other ZL devices.
7
SDA
I/O
Serial data. Connect to external host and/or to other ZL devices.
8
SALRT
O
Serial alert. Connect to external host if desired.
9
FC
I
Loop compensation selection pin.
10
V0
I, M
Output voltage selection pins. Used to set VOUT set-point and VOUT max.
11
V1
12
VMON
I, M
External voltage monitoring (Can be used for external driver bias monitoring for Power-good).
13, 17
NC
14
VTRK
I
Tracking sense input. Used to track an external voltage source.
15
VSEN+
I
Differential Output voltage sense feedback. Connect to positive output regulation point.
16
VSEN-
I
Differential Output voltage sense feedback. Connect to negative output regulation point.
18
ISENB
I
Differential voltage input for current sensing.
19
ISENA
I
Differential voltage input for current sensing. High voltage (DCR).
20
PWML
O
PWM Gate low signal.
21
SGND
PWR
22
PWMH
O
23
VR
PWR
Internal 5V reference used to power internal drivers.
24
VDD
(Note 7)
PWR
Supply voltage.
25
V25
PWR
Internal 2.5V reference used to power internal circuitry.
26
XTEMP
I
External temperature sensor input. Connect to external 2N3904 (Base Emitter junction).
27
DDC
I
Single wire DDC bus (Current sharing, interdevice communication).
28
MGN
I
VOUT margin control.
29
CFG
M
Configuration pin. Used to control the switching phase offset, sequencing and other management features.
30
EN
I
Enable. Active signal enables PWM switching.
31
SS
I, M
32
PG
O
EPAD
SGND
PWR
DESCRIPTION
Digital ground. Connect to low impedance ground plane.
No Connect.
Connect to low impedance ground plane. Internal connection to SGND.
PWM Gate High signal.
Soft-start delay and ramp select. Sets the delay from when EN is asserted until the output voltage starts to
ramp and the ramp time.
Power-good output.
Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.
NOTES:
5. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins.
6. The SYNC pin can be used as a logic pin, a clock input or a clock output.
7. VDD is measured internally and the value is used to modify the PWM loop gain.
3
FN6847.2
May 23, 2011
ZL2004-01
Absolute Maximum Ratings (Note 8)
Thermal Information
DC Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic I/O Voltage
CFG, DDC, EN, FC, FLEX, ILIM, MGN, PG, SA (0,1)
SALRT, SCL, SDA, SS, SYNC, VMON, V (0,1) . . . . . . . . . . . . -0.3V to 6.5V
Analog Input Voltages
VSEN+, VSEN-, VTRK, XTEMP . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ISENA, ISENB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
MOSFET Drive Reference (VR). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Logic reference (V25). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Ground Voltage Differential (VDGND- VSGND)
DGND, SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
32 Ld QFN Package (Notes 9, 10) . . . . . . .
35
5
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Supply Voltage Range, (VDD). . . . . . . . . . . . . . . . . . . . . . . . . 8V to 10V
Output Voltage Range (VOUT) . . . . . . . . . . . . . . . . . 0.9V to 1.1V, 1.0V (Typ)
Operating Frequency (FSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400kHz Typ
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . 0°C to +65°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
8. All voltages are measured with respect to SGND.
9. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
10. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 8.6 V, VOUT = 1.0 V, TA = 0°C to +65°C unless otherwise noted. Typical values are at TA = +25°C. The
following specifications describe the ZL2004-01 electrical specifications that differ from the ZL2004. Please refer to the ZL2004 data sheet for the full
operating specification limits for the remaining functions not described herein. Boldface limits apply over the operating temperature range, 0°C to
+65°C.
PARAMETER
CONDITIONS
MIN
(Note 11)
TYP
MAX
(Note 11)
UNIT
–
16
30
mA
INPUT AND SUPPLY CHARACTERISTICS
IDD Supply Current at FSW = 400kHz
GH no load, GL no load,
MISC_CONFIG[7] = 1
IDDS Shutdown Current
EN = 0V No I2C/SMBus activity
–
2
5
mA
VR Reference Output Voltage
VDD > 6V, IVR < 50mA
4.5
5.2
5.7
V
V25 Reference Output Voltage
VR > 3V, IV25 < 50mA
2.25
2.5
2.75
V
OUTPUT CHARACTERISTICS
Output Voltage Adjustment Range
VIN > VOUT
0.9
–
1.1
V
Output Voltage Setpoint Accuracy (Note 12)
VIN = 8.6V, VOUT = 1V
TA = 0°C to + 65°C,
ILOAD = 0A to 40A
-0.2
–
0.2
%
-1.0
-
1.0
%
–
400
–
kHz
-5
–
5
%
2.85
–
16
V
PMBus READ_VOUT Accuracy
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency (Note 13)
SYNC pin floating or NVM configured for
400kHz
Switching Frequency Set-point Accuracy
FAULT PROTECTION CHARACTERISTICS
Configurable via I2C/SMBus
UVLO Threshold Range
NOTES:
11. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
12. VOUT set-point measured at the termination of the VSEN+ and VSEN- sense points.
13. The ZL2004-01 has been optimized for operation at 400kHz only. Please consult the factory for requirements at other operating frequencies.
4
FN6847.2
May 23, 2011
ZL2004-01
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
5/11/11
FN6847.2
CHANGE
On page 1:
Added “Related Literature”
On page 2:
Added following parts to “Ordering Information”:
ZL2004ALNN-01
ZL2004ALNF-01
ZL2004ALNFT-01
ZL2004ALNFT1-01
Added lead finish Note 3 for ALNF parts.
On page 4:
Updated note in Min Max column of “Electrical Specifications” table from "Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested." to "Compliance to datasheet limits is assured by one or more
methods: production test, characterization and/or design."
On page 7:
Added “Package Outline Drawing” L32.5x5G for ALNF parts.
4/9/10
FN6847.1
On page 4, changed max value from 5.5 to 5.7 for “VR Reference Output Voltage”.
3/23/10
2/19/09
Converted to New Intersil Template. Added spec to existing parameter on the device in Electrical Specifications
Table “Output Characteristics”: PMBus READ_VOUT Accuracy -1.0 (MIN), 1.0 (MAX) %. Changed Temp Range in
ordering information from “-40°C to +85°C” to “0°C to +65°C” matching information in Thermal Information.
Added over-temp note and reference Electrical spec table Min and Max columns. Added ordering information
table, Pin Configuration and Pin Description Table, POD, Revision History and Products Information.
Updated POD L32.5x5D to latest released version. Change to POD is as follows:
Updated POD to new standards by adding land pattern and moving dimensions from table onto drawing.
FN6847.0
Assigned file number FN6847 to datasheet as this will be the first release with an Intersil file number. Replaced
header and footer with Intersil header and footer. Updated disclaimer information to read "Intersil and it's
subsidiaries including Zilker Labs, Inc." No changes to datasheet content.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ZL2004-01
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
5
FN6847.2
May 23, 2011
ZL2004-01
Package Outline Drawing
L32.5x5D
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
4X 3.5
5.00
28X 0.50
A
B
25
6
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
32
1
5.00
24
3 .50
EXP. DAP
17
(4X)
8
0.15
16
TOP VIEW
9
32X 0.40 ± 0.10
4 32X 0.23
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
MAX 0.90
C
SEATING PLANE
0.08 C
( 4. 80 TYP )
(
SIDE VIEW
( 28X 0 . 5 )
3.50 )
(32X 0 . 23 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 32X 0 . 60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6
FN6847.2
May 23, 2011
ZL2004-01
Package Outline Drawing
L32.5x5G
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 3.5
5.00
28X 0.50
A
B
25
6
PIN 1
INDEX AREA
32
6
PIN #1
INDEX AREA
1
5.00
24
3 .50
EXP. DAP
17
(4X)
8
0.15
16
9
TOP VIEW
32X 0.40 ± 0.10
4 32X 0.23
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
MAX 1.00
( 4. 80 TYP )
(
C
SEATING PLANE
0.08 C
( 28X 0 . 5 )
SIDE VIEW
3.50 )
(32X 0 . 23 )
C
0 . 2 REF
5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7
FN6847.2
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