Application Note 1948 ZL8801-4PH-DEMO1Z Demonstration Board User Guide Description Key Features The ZL8801 is a dual-phase digital DC to DC controller optimized for current sharing. As many as 4 ZL8801’s can be operated in parallel to provide even phase counts between 2 and 8 phases. The ZL8801 incorporates compensation-free ChargeMode control to achieve single-cycle transient response. • 160A 4-phase synchronous buck converter with ChargeMode™ control The ZL8801 supports a wide range of output voltages (0.54V to 5.5V) operating from input voltages between 4.5Vand 14V. The ZL8801-4PH-DEMO1Z evaluation board is a 6-layer board configured as a 4-phase 160A synchronous buck converter. Sequencing, margining, fault spreading and other features can be evaluated using this board. A USB to PMBus™ adapter module is used to connect the evaluation board to a host PC running Microsoft Windows. • VIN range 4.5V to 14V • VOUT range 0.54V to 3.6V • I2C/SMBus interface, PMBus compatible • Output voltage and current protection References • ZL8801 datasheet Ordering Information Specifications TABLE 1. EVALUATION BOARD SPECIFICATIONS SPEC • On-the-fly VOUT control • Configurable with PMBus DESCRIPTION MIN TYP MAX UNIT VIN Input Voltage Range 6.5 14 V VOUT Output Voltage Range, Default VOUT = 1V 0.6 3.6 V IOUT Rated Output Current 0 160 A fSW Switching Frequency 400 1000 kHz VRIPPLE Output Ripple Voltage ±1 PART NUMBER DESCRIPTION ZL8801-4PH-DEMO1Z ZL8801 Demonstration Kit (Demonstration Board, USB Adapter, Cable) % FIGURE 1. ZL8801-4PH-DEMO1Z BOARD September 25, 2014 AN1948.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design), PowerNavigator, ChargeMode and Digital-DC are trademarks owned by Intersil Corporation or one of its subsidiaries.All other trademarks mentioned are the property of their respective owners. Application Note 1948 VDRV VIN EN PG SCL SDA DDC SY NC VDD EN0 PG0 SCL SDA DDC SY NC PWMH0 PWML0 ISENA0 ISENB0 ZL8801 PWMH1 PWML1 ISENA1 ISENB1 VOUT VSEN0P VSEN0N GND VDD EN0 PG0 SCL SDA DDC SY NC PWMH0 PWML0 ISENA0 ISENB0 ZL8801 PWMH1 PWML1 ISENA1 ISENB1 VSEN0P VSEN0N GND FIGURE 2. ZL8801-4PH-DEMO1Z BLOCK DIAGRAM Submit Document Feedback 2 AN1948.0 September 25, 2014 Application Note 1948 Functional Description Quick Start Guide The ZL8801-4PH-DEMO1Z provides all circuitry required to demonstrate most of the features of the ZL8801 in a multidevice current sharing application. The ZL8801-4PH-DEMO1Z has a functionally-optimized ZL8801 circuit layout that allows efficient operation up to the maximum output current (with airflow). Power and load connections are provided by Banana jacks. Stand Alone Operation When the ZL8801-4PH-DEMO1Z board is removed from the shipping box it is ready to be powered on by using the Enable Switch. PMBus operation can be configured by using the PowerNavigator™ GUI. Headers are provided at opposite ends of the board for connecting a USB to SMBus Dongle and for daisy chaining other Intersil Digital Power Evaluation and Demo Boards. A majority of the features of the ZL8801, such as compensation free ChargeMode control, soft-start delay, ramp times, supply sequencing, and voltage margining are available on this evaluation board. For sequencing and Fault Spreading demonstration, the board can be connected to any other demonstration board that supports the Digital-DC™ (DDC) bus. Voltage Tracking is not supported on the ZL8801-4PH-DEMO1Z. Figure 1 shows the top view of the PWB. Operating Range 1. Set Enable switch to “Disable”. 2. Apply Load to VOUT+/VOUT-. 3. Connect the USB to SMBus adapter to J4 of the ZL8801-4PH-DEMO1Z. 4. Connect the USB adapter cable to the host computer. 5. Connect VIN+/VIN- to a suitable input power source (supply turned off). 6. Install jumpers J1 and J2 to use onboard VRDRV linear regulator. 7. Turn input power supply on. 8. Set Enable switch to “Enable”. 9. Monitor ZL8801-4PH-DEMO1Z board with an oscilloscope. 10. To demonstrate advanced features like Sequencing, and Fault Spreading connect other compatible Intersil Digital Power boards to J5 and J8. USB (PMBus) Operation 1. Set the Enable switch to “Disable”. 2. Apply load to VOUT+/VOUT-. The ZL8801-4PH-DEMO1Z is preconfigured to the following specifications: TABLE 2. VIN VOUT IOUT fSW FAULT RESPONSE 6.5V to 14V 1.0V 40A/Ph, 160A 515kHz Shutdown 3. Connect the USB to SMBus adapter to J4 of the ZL8801-4PH-DEMO1Z. 4. Connect the USB adapter cable to the host computer. 5. Connect VIN+/VIN- to a suitable input power source (supply turned off). 6. Install jumpers J1 and J2 to use onboard VRDRV linear regulator. 7. Install the PowerNavigator software on the host computer. The ZL8801-4PH-DEMO1Z’s dual ZL8801 controllers reside at address 0x20 and 0x21. The preconfigured operation parameters can be changed by using the PowerNavigator GUI. 8. Turn the input power source on, the demo board comes configured to produce an output voltage of 1.0V. Use the GUI or modify the configuration file to operate at Vout up to 3.6V. The ZL8801-4PH-DEMO1Z has been optimized for a nominal switching frequency of 515kHz, this frequency provides a good compromise between packaging density and efficiency relative to the selected power train. The switching frequency can be changed to operate anywhere between 300kHz and 1000kHz. 9. Run the PowerNavigator program and select the “Monitor Hardware” option and then click the Start button. PCB Layout Guidelines 10. Using the Monitor View change the enable mode to “PMBus Enable”. 11. Click on the Enable button to turn on the ZL8801-4PH-DEMO1Z and use the GUI to monitor. The ZL8801-4PH-DEMO1Z Board layout has been optimized for power density, electrical and thermal performance. The following key features are: •Thermal vias connected to a large common SGND plane is used for each ZL8801 on Inner 1. •ISENSE nets are Kelvin connected to each output inductor. •VSENSE nets are Kelvin connected to the point of regulation. •One SGND plane established for both ZL8801 controllers. •SGND plane for each controller duplicated on bottom layer with thermal vias to aid in heat removal. Submit Document Feedback 3 AN1948.0 September 25, 2014 Application Note 1948 Default Configuration File The ZL8801-4PH-DEMO1Z comes preconfigured with the following configuration files ZL8801_0x20.txt and ZL8801_0x21.txt the files are printed below for convenience. # ZL8801_0x20 RESTORE_FACTORY STORE_DEFAULT_ALL STORE_USER_ALL RESTORE_DEFAULT_ALL STORE_DEFAULT_ALL RESTORE_USER_ALL FREQUENCY_SWITCH INTERLEAVE SEQUENCE TON_DELAY TON_RISE TOFF_DELAY TOFF_FALL TRACK_CONFIG ON_OFF_CONFIG VOUT_COMMAND VOUT_MAX VOUT_MARGIN_HIGH VOUT_MARGIN_LOW VOUT_MARGIN_RATIO VOUT_DROOP VOUT_OV_FAULT_LIMIT VOUT_OV_FAULT_RESPONSE VOUT_UV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE VOUT_CAL_OFFSET VOUT_TRANSITION_RATE MIN_VOUT_REG VIN_OV_WARN_LIMIT VIN_OV_FAULT_LIMIT VIN_OV_FAULT_RESPONSE VIN_UV_WARN_LIMIT VIN_UV_FAULT_LIMIT VIN_UV_FAULT_RESPONSE POWER_GOOD_ON POWER_GOOD_DELAY IOUT_OC_FAULT_LIMIT IOUT_UC_FAULT_LIMIT IOUT0_CAL_GAIN IOUT0_CAL_OFFSET IOUT1_CAL_GAIN IOUT1_CAL_OFFSET IOUT_AVG_OC_FAULT_LIMIT IOUT_AVG_UC_FAULT_LIMIT IIN_CAL_GAIN OT_WARN_LIMIT OT_FAULT_LIMIT OT_FAULT_RESPONSE UT_WARN_LIMIT UT_FAULT_LIMIT UT_FAULT_RESPONSE DEADTIME DEADTIME_CONFIG DEADTIME_MAX ISENSE_CONFIG USER_CONFIG MFR_USER_CONFIG DDC_CONFIG OVUV_CONFIG DEADTIME DEADTIME_CONFIG ASCR_CONFIG TRACK_CONFIG DDC_GROUP USER_GLOBAL_CONFIG STORE_USER_ALL Submit Document Feedback 515 0x0000 0x0000 5 5 5 5 0x00 0x17 1.0 3.5 1.05 0.95 0xCA80 0.20 1.20 0x80 0.80 0X80 0.0 1.0 150 13.0 14.4 0x80 6.50 6.00 0x80 0.90 5.00 62 -50.0 0.25 -1.60 0.25 -1.60 62.0 -62.0 0.0 110.0 125.0 0x80 -30.0 -45.0 0x80 0x0C0C 0x8686 0x0C0C 0x5A04 0x0603 0x0002 0x103 0x00 0x2020 0x8686 0x15A00C8 0x00 0x202000 0x0002 4 # ZL8801-1 0x21 RESTORE_FACTORY STORE_DEFAULT_ALL STORE_USER_ALL RESTORE_DEFAULT_ALL STORE_DEFAULT_ALL RESTORE_USER_ALL FREQUENCY_SWITCH INTERLEAVE SEQUENCE TON_DELAY TON_RISE TOFF_DELAY TOFF_FALL TRACK_CONFIG ON_OFF_CONFIG VOUT_COMMAND VOUT_MAX VOUT_MARGIN_HIGH VOUT_MARGIN_LOW VOUT_MARGIN_RATIO VOUT_DROOP VOUT_OV_FAULT_LIMIT VOUT_OV_FAULT_RESPONSE VOUT_UV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE VOUT_CAL_OFFSET VOUT_TRANSITION_RATE MIN_VOUT_REG VIN_OV_WARN_LIMIT VIN_OV_FAULT_LIMIT VIN_OV_FAULT_RESPONSE VIN_UV_WARN_LIMIT VIN_UV_FAULT_LIMIT VIN_UV_FAULT_RESPONSE POWER_GOOD_ON POWER_GOOD_DELAY IOUT_OC_FAULT_LIMIT IOUT_UC_FAULT_LIMIT IOUT0_CAL_GAIN IOUT0_CAL_OFFSET IOUT1_CAL_GAIN IOUT1_CAL_OFFSET IOUT_AVG_OC_FAULT_LIMIT IOUT_AVG_UC_FAULT_LIMIT IIN_CAL_GAIN OT_WARN_LIMIT OT_FAULT_LIMIT OT_FAULT_RESPONSE UT_WARN_LIMIT UT_FAULT_LIMIT UT_FAULT_RESPONSE DEADTIME DEADTIME_CONFIG DEADTIME_MAX ISENSE_CONFIG USER_CONFIG MFR_USER_CONFIG DDC_CONFIG OVUV_CONFIG DEADTIME DEADTIME_CONFIG ASCR_CONFIG TRACK_CONFIG DDC_GROUP USER_GLOBAL_CONFIG STORE_USER_ALL 515 0x0000 0x0000 5 5 5 5 0x00 0x17 1.0 3.5 1.05 0.95 0xCA80 0.20 1.20 0x80 0.80 0x80 0.0 1.0 150 13.0 14.4 0x80 6.50 6.00 0x80 0.90 5.00 62 -50.0 0.25 -1.60 0.25 -1.60 62.0 -62.0 0.0 110.0 125.0 0x80 -30.0 -45.0 0x80 0x0C0C 0x8686 0x0C0C 0x5A04 0x0603 0x0004 0x2103 0x00 0xC0C 0x8686 0x15A00C8 0x00 0x202000 0x0004 AN1948.0 September 25, 2014 Submit Document Feedback ZL8801-4PH-DEMO1Z Schematic (Phase 1,2) VDRV VIN C40 10uF 16V VDRV C41 10uF 16V R71 1 VIN U9 ZL8800 SG 33 5 SCL SDA DDC PG1 PG2 HW_EN SYNC SALT_1,2 SCL SDA DDC PG1 PG2 R48 R49 R47 22.1 22.1 22.1 1 2 14 12 37 HW_EN SYNC R51 42 22.1 44 3 Place near L1 15 Q10 2N3904 Q11 2N3904 Place near L2 C48 100p 50V 16 41 C52 100p 50V 29 PWM1 IINN IINP PWMH0 PWML SCL SDA DDC PG0 PG1 25 24 SG C44 10uF 16V SG R55 100K 6 10 43 11 21 VMON C56 0.01uF 25V ISENA0 ISENB0 ISENB1 ISENA1 XTEMP0P VOUT P1A 30 2 12-15,28,34 VOUT P1B R50 953 C47 100uF 6.3V C46 1uF 16V 22 23 28 29 1A0 C49 1uF 10V XTEMP0N XTEMP1P FB2 1000 Ohm R52 1 5 7 R53 30.0K 6 VTRKP VTRKN VDRV UVLO MGN1 MGN0 PWMH1 PWML1 26 27 VMON VS0 EN1 VS1 VDRVEN SA V25 36 5 P2 EN_DR2 SG VR5 32 VSEN1P VSEN0P VSEN0N VSEN1N DG SG EPAD 4 45 39 19 20 38 7 C58 10uF 16V SG C54 10uF 16V VSEN+ VSEN- C55 10uF 16V R54 953 P2A C53 1uF 16V P2B 16-26 L2 0.220nH GL2 27,35 EN_DR2 XX3 C57 10uF 16V 3 1 31 2A1 2B1 C50 C51 22uF 22uF 16V 16V 8-11,33 U5 FDMF5821DC XTEMP1N Address Set to 0x20 R72 61.9K L1 0.220nH 16-26 1B0 SALRT R57 19.6K R56 6.65K 8-11,33 SYNC SG VMON 6 U4 FDMF5821DC 4,32 C45 10uF 16V PWM2 17 18 30 13 9 8 7 C39 22uF 16V GL1 27,35 29 40 5 3 1 31 P1 EN_DR1 EN_DR1 EN0 C38 22uF 16V 4,32 30 2 12-15,28,34 VSEN+ VSEN- Application Note 1948 SALT_1,2 FB1 1000 Ohm 31 VR6 VDD 34 35 R45 R46 1 30.0K C43 1uF 10V AN1948.0 September 25, 2014 Submit Document Feedback ZL8801-4PH-DEMO1Z Schematic (Interface) Interface R6-R9 = 6.8K R7 R9 R6 R8 VI2c VI2c C9 10uF FROM PREQUEL J4 + Vin Monitor - J5 1 2 3 4 5 6 SDA SALRT SCL GND Vi2c MSTR_EN SDA SALRT SCL GND Vi2c MSTR_EN 1 2 3 4 5 6 1 1 2 1 2 3 4 5 6 MSTR_SYNC 1 2 RSVD1 3 GND 4 DDC 5 RSVD2 6 RSVD3 C10 10uF 25V C26 100uF 6.3V C27 100uF 6.3V VOUT VOUT 2 4 G-ADJ 1 R12 2.74K R11 909 SYNC SDA SCL DDC C28 100uF 6.3V C29 100uF 6.3V VDR C31 100uF 6.3V C32 100uF 6.3V C33 680uF 4V C34 680uF 4V C35 680uF 4V C12 22uF 16V + P3 + P4 C14 330u 16V C15 22uF 16V C16 22uF 16V C36 680uF 4V 1 VOUT + VDD Monitor - R20 100 2 C11 10uF 16V C13 330u 16V C30 100uF 6.3V 1 XX1 J13 1 2 VSEN+ VSEN- VSEN+ VSEN- GND XX2 1 P5 GND 1 P6 VDR R14 10.0K R15 10.0K SW1 3 2 1 ESW MSTR_EN Disable Monitor Enable HW_EN C21 1uF 25V + VDRV GND VDR_OUT P1 R19 100K Title Interface + VIN GND P2 Application Note 1948 VOUT C24 C25 10uF 100uF 10V 6.3V VIN VIN 1 C23 10uF 10V 3 VDRV J2 + SYNC - SYNC R13 49.9 2 VIN SMA_NO-POP J11 J8 MSTR_SYNC RSVD1 GND DDC RSVD2 RSVD3 U1 REG1117A J1 J3 6 J7 VDRV VDR_IN TO SEQUEL AN1948.0 September 25, 2014 Submit Document Feedback ZL8801-4PH-DEMO1Z Schematic (Phase 3,4) VDRV VIN C61 10uF 16V R74 1 VDRV C62 10uF 16V VIN U6 ZL8800 SG 33 VDD 35 34 7 SCL SDA DDC PG3 PG4 HW_EN SYNC SCL SDA DDC PG3 PG4 R60 R61 R62 22.1 22.1 22.1 1 2 14 12 37 HW_EN 42 SYNC R64 22.1 44 15 Place near L3 Q12 2N3904 Place near L4 C63 100p 50V 16 41 C68 100p 50V 40 17 18 SALT_3,4 VMON SALT_3,4 3 30 13 8 9 6 10 43 11 21 VMON Address Set to 0x21 C76 0.01uF 25V R73 61.9K FB3 1000 Ohm 31 VR6 29 PWM3 IINP IINN 25 24 PWMH0 PWML SCL SDA DDC PG0 PG1 5 7 6 C60 22uF 16V 8-11,33 U7 FDMF5821DC 3 1 31 P3 EN_DR3 SG C65 10uF 16V SG VOUT P3A 4,32 C66 10uF 16V L3 0.220nH 16-26 GL3 27,35 EN_DR3 EN0 C59 22uF 16V 30 2 12-15,28,34 VOUT P3B R63 953 C67 1uF 16V SYNC 3B0 22 23 28 29 ISENA0 ISENB0 ISENB1 ISENA1 XTEMP0P 3A0 C69 1uF 10V XTEMP0N XTEMP1P FB4 1000 Ohm XTEMP1N 29 PWM4 VTRKP VTRKN 26 27 PWMH1 PWML1 SALRT VDRV UVLO MGN0 MGN1 VMON VS0 EN1 VS1 VDRVEN SA V25 36 5 VR5 32 39 19 20 38 7 VSEN1P VSEN0P VSEN0N VSEN1N DG SG EPAD 4 45 R68 21.5K XX4 C77 10uF 16V C78 10uF 16V SG 7 6 C74 10uF 16V VSEN+ VSEN- C75 10uF 16V R67 953 8-11,33 U8 FDMF5821DC P4A C72 1uF 16V P4B 16-26 L4 0.220nH GL4 27,35 EN_DR4 SG 5 R66 30.0K 3 1 31 P4 EN_DR4 SG R65 1 4A1 4B1 C70 C71 22uF 22uF 16V 16V 4,32 30 2 12-15,28,34 VSEN+ VSEN- Application Note 1948 Q13 2N3904 R58 R59 1 30.0K C64 1uF 10V AN1948.0 September 25, 2014 Application Note 1948 ZL8801 Schematic (Power-Good Logic) PG P1_OK P2_OK P3_OK D11 GRN VI2c D7 GRN VI2c R30 10.0K PG1 PG1 PG2 PG2 R23 10.0K R24 10.0K R32 10.0K D8 GRN R26 392 R33 392 D9 GRN R27 392 6 D1 3 D2 S1 1 S2 4 P4_OK D10 GRN R28 392 R29 392 2 G1 5 G2 Q2 FDG6303N 6 D1 PG3 PG3 2 G1 PG4 PG4 5 G2 6 1 S1 3 D2 5 G2 Q4 FDG6303N S1 1 D1 2 G1 3 D2 S2 4 Q6 FDG6303N S2 4 6 D1 2 G1 1 S1 3 D2 5 G2 Q8 FDG6303N S2 4 Submit Document Feedback 8 AN1948.0 September 25, 2014 Application Note 1948 Bill of Materials ITEM QTY REFERENCE VALUE TOL RATING TYPE PCB FOOTPRINT MANUFACTURER PART NUMBER 1 1 C9 10µF 10% 10V X7R SM0805 Taiyo Yuden LMK212B7106KG-TD 2 1 C10 10µF 10% 25V X5R SM1206 Panasonic - ECG ECJ-3YB1E106K 3 17 C11, C40, C41, C44, C45, C54, C55, C57, C58, C61, C62, C65, C66, C74, C75, C77, C78 10µF 10% 16V X5R SM0805 TDK C2012X5R1C106K/0.85 4 11 C12, C15, C16, C38, C39, C50, C51, C59, C60, C70, C71 22µF 20% 16V X5R SM1206 Murata GRM31CR61C226ME15L 5 2 C13, C14 330µF 20% 16V 6 1 C21 1µF 10% 25V X5R SM0603 Taiyo Yuden TMK107BJ105KA-T 7 2 C23, C24 10µF 10% 10V X7R SM0805 Murata GRM21BR71A106KE51L 8 9 C25, C26, C27, C28, C29, C30, C31, C32, C47 100µF 6.3V X5R SM1210 Taiyo Yuden JMK325BJ107MY-T 9 4 C33, C34, C35, C36 680µF 20% 4V Kemet T530Y687M004ATE005 10 4 C43, C49, C64, C69 1µF 10% 10V X7R SM0603 Taiyo Yuden LMK107B7105KA-T 11 4 C46, C53, C67, C72 1µF 10% 16V X7R SM0603 TDK Corporation C1608X7R1C105K 12 4 C48, C52, C63, C68 100pF 5% 50V C0G SM0402_WSS MURATA GRM1555C1H101JZ01D 13 2 C56, C76 0.01µF 10% 25V X7R SM0402 Kemet C0402C103K3RACTU 14 5 D7, D8, D9, D10, D11 GRN 2V 15 4 FB1, FB2, FB3, FB4 1000Ω 150mA 16 4 J1, J2, J3, J13 17 2 18 AL POLY SM_CAP_10.5X10.5_PXA_FLD AL POLY SM7343_KEMET_T530_BC United Chemi-Con APXA160ARA331MJC0G SM0805 Chicago Miniature CMD17-21VGC Ferrite SM0402 Taiyo Yuden BK1005HM102-T 2 POS VERT SIP2/100 Samtec TSW-102-07-L-S J4, J7 HDR_3X2_RA RA HDRM3DUALRA100X100 SAMTEC TSW-103-08-T-D-RA 2 J5, J8 SKT_3X2_RA RA HDRF3DUALRA100X100 SAMTEC SSQ-103-02-T-D-RA 19 1 J11 SMA_NO-POP SMA_PCB_VJACK Emerson 142-9701-211 20 4 L1, L2, L3, L4 0.220nH 70 ITG SL3732_R22KHF 21 2 P1, P2 JACK 15A Emerson 108-0740-001 Inductor IND_SL3732_RXXXXX JACK 22 2 P3, P4 23 2 P5, P6 GND CON_LUG 24 4 Q2, Q4, Q6, Q8 FDG6303N 25 4 Q10, Q11, Q12, Q13 2N3904 26 4 R6, R7, R8, R9 6.8k 1% 1/16W 27 1 R11 909 28 1 R12 29 1 30 CON_LUG Dual N-Chan SC70_6 Fairchild FDG6303N NPN SOT-23 ON SEMI MMBT3904LT1G SM0402 Panasonic - ECG ERJ-2RKF6801X 1% 100mW THK FILM SM0603 Panasonic - ECG ERJ-3EKF9090V 2.74k 1% 100mW THK FILM SM0603 Panasonic - ECG ERJ-3EKF2741V R13 49.9 1% 100mW THK FILM SM0402 Panasonic - ECG ERJ-2RKF49R9X 2 R14, R15 10.0k 1% 63mW THK FILM SM0402 Panasonic - ECG ERJ-2RKF1002X 31 1 R19 100k 1% 63mW THK FILM SM0402 Panasonic - ECG ERJ-2RKF1003X 32 1 R20 100 1% 100mW THK FILM SM0805 Panasonic - ECG ERJ-6ENF1000V 33 4 R23, R24, R30, R32 10.0k 1% Yageo RC0402FR-0710KL 34 5 R26, R27, R28, R29, R33 392 1% Panasonic - ECG ERJ-3EKF3920V Submit Document Feedback 9 25V 40V 1/16W SM0402 THK FILM SM0603 AN1948.0 September 25, 2014 Application Note 1948 Bill of Materials (Continued) ITEM QTY 35 6 REFERENCE VALUE R45, R52, R58, R65, R71, R74 1 TOL RATING TYPE PCB FOOTPRINT MANUFACTURER PART NUMBER 1% 1/16W SM0603 Panasonic - ECG ERJ-3RQF1R0V 1/16W 36 4 R46, R53, R59, R66 30.0k 1% SM0603 Panasonic - ECG ERJ-2GEJ303X 37 8 R47, R48, R49, R51, R60, R61, R62, R64 22.1 1% SM0402 Panasonic ERJ-2RKF22R1X 38 4 R50, R54, R63, R67 953 1% Resistor SM0603 Panasonic ERJ-3EKF9530V 39 1 R55 100k 1% 1/16W SM0402 Vishay/Dale CRCW0402100KFKED 40 1 R56 6.65k 1% 1/16W SM0402 Panasonic - ECG ERJ-2RKF6651X 41 1 R57 19.6k 1% 1/16W SM0402 Panasonic - ECG ERJ-2RKF1962X 42 1 R68 21.5k 1% 1/16W SM0402 Panasonic - ECG ERJ-2RKF2152X 43 2 R72, R73 61.9k 1% 1/16W SM0402 Panasonic - ECG ERJ-2RKF6192X 44 1 SW1 SW_SPDT SW_TOG_ULTRAMIN_SPDT NKK G13AP-RO 45 1 U1 REG1117A SOT_223_1234 Texas Instruments REG1117A 46 4 U4, U5, U7, U8 FDMF5821DC PQFN31_SPS_5X5_P5S Fairchild FDMF5821DC 47 2 U6, U9 ZL8800 MLF44_7X7_DP Intersil ZL8801 Submit Document Feedback 10 PCB VERT 30V AN1948.0 September 25, 2014 Application Note 1948 100 100 95 95 90 90 85 1.8V 1.5V 1.2V 80 EFFICIENCY (%) EFFICIENCY (%) Typical Performance Curves 2.5V 1.0V 75 70 65 85 55 40 60 80 100 120 140 50 160 0 20 40 LOAD CURRENT (A) 95 100 95 90 90 EFFICIENCY (%) EFFICIENCY (%) 85 1.8V 2.5V 1.2V 75 1.0V 70 65 80 50 80 140 160 100 120 140 1.8V 2.5V 1.0V 65 55 60 1.5V 70 55 40 120 1.2V 75 60 20 100 85 60 50 0 80 FIGURE 4. EFFICIENCY VIN = 12V, fSW = 400kHz 100 1.5V 60 LOAD CURRENT (A) FIGURE 3. EFFICIENCY VIN = 12V, fSW = 300kHz 80 2.5V 65 60 20 1.8V 70 55 0 1.5V 1.0V 75 60 50 1.2V 80 160 0 20 40 60 80 100 120 140 160 LOAD CURRENT (A) LOAD CURRENT (A) FIGURE 6. EFFICIENCY VIN = 12V, fSW = 615kHz FIGURE 5. EFFICIENCY VIN = 12V, fSW = 515kHz 100 95 EFFICIENCY (%) 90 85 80 1.5V 1.8V 2.5V 1.2V 75 70 1.0V 65 60 55 50 0 20 40 60 80 100 120 140 160 LOAD CURRENT (A) FIGURE 7. EFFICIENCY VIN = 12V, fSW = 800kHz Submit Document Feedback 11 AN1948.0 September 25, 2014 Application Note 1948 Measured Data TYPICAL IMMEDIATE OFF TURN-ON RAMP VOUT = 1V, fSW = 515kHz, IOUT = 50A TYPICAL STATIC OUTPUT RIPPLE VOLTAGE VOUT = V, IOUT =50A, VIN = 12V, fSW = 515kHz 8mVP-P VOUT VOUT = 1V RESONANT ARTIFACT DUE TO ELECTRONIC LOAD CABLE INDUCTANCE FIGURE 8. STATIC RIPPLE TYPICAL TURN-ON RAMP VIN = 12V, VOUT = 1V, fSW = 515kHz, IOUT = 50A MULTI_PHASE_RAMP_GAIN = 1 FIGURE 9. TURN-OFF RAMP TRANSIENT RESPONSE IOUT = 20 TO 40A 10A/µs VIN = 12V, VOUT = 1V, fSW = 515kHz ASCR GAIN = 275, RESIDUAL = 100 VOUT = 1V TUNE WITH MIN_VOUT_REG AN MULTI_PHASE_RAMP_GAIN TO MINIMIZE VP-P = 30mV VSYNC 200mV START-UP ANOMALY FIGURE 10. TURN-ON RAMP Submit Document Feedback 12 FIGURE 11. TRANSIENT RESPONSE AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Evaluation Board and Dongle OUTPUT VOLTAGE CONNECTION KELVIN CONNECTED VOUT MEASUREMENT CONNECTION ENABLE SWITCH ZL8801s RAIL PG LAMP INSERT JUMPERS TO USE ON BOARD VDRV REGULATOR J1, J2 CONNECT OTHER INTERSIL DIGITAL POWER BOARDS HERE CONNECT USB TO PMBus DONGLE HERE KELVIN CONNECTED VIN MEASUREMENT CONNECTION INPUT VOLTAGE CONNECTION EXTERNAL VDRV INPUT TYPICALLY USED FOR EFFICIENCY MEASUREMENTS. REMOVE J1, J2 AND CONNECT +5V EXTERNAL VDRV VOLTAGE FIGURE 12. ZL8801-4PH-DEMO1Z CRITICAL COMPONENT LOCATION USB CONNECTION TO HOST COMPUTER CONNECT TO ZL8801-4PH-DEMO1Z J4 DEMO BOARD FIGURE 13. USB TO PMBus DONGLE Submit Document Feedback 13 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout FIGURE 14. TOP SILKSCREEN Submit Document Feedback 14 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 15. TOP ETCH Submit Document Feedback 15 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 16. INNER 1 Submit Document Feedback 16 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 17. INNER 2 Submit Document Feedback 17 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 18. INNER 3 Submit Document Feedback 18 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 19. INNER 4 Submit Document Feedback 19 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 20. INNER 5 Submit Document Feedback 20 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 21. INNER 6 Submit Document Feedback 21 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 22. BOTTOM ETCH Submit Document Feedback 22 AN1948.0 September 25, 2014 Application Note 1948 ZL8801-4PH-DEMO1Z Layout (Continued) FIGURE 23. BOTTOM SILKSCREEN Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 23 AN1948.0 September 25, 2014