DATASHEET

HA-2510/883
Data Sheet
August 13, 2015
FN3697.5
High Slew Rate Operational Amplifier
Features
The HA-2510/883 is a high performance operational
amplifier which sets the standards for maximum slew rate
and wide bandwidth operation in moderately powered,
internally compensated, monolithic devices. In addition to
excellent dynamic characteristics, this dielectrically isolated
amplifier also offers low offset current and high input
impedance.
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The 50V/s minimum slew rate and fast settling time of
the HA-2510/883 are ideally suited for high speed D/A,
A/D, and pulse amplification designs. The HA-2510/883’s
superior bandwidth and 750kHz minimum full power
bandwidth are extremely useful in RF and video
applications. To insure compliance with slew rate and
transient response specifications, all devices are 100%
tested for AC performance characteristics over full
temperature limits. To improve signal conditioning accuracy,
the HA-2510/883 provides a maximum offset current of 25nA
and a minimum input impedance of 50M, both at 25oC, as
well as offset voltage adjust capability.
• Low Offset Current . . . . . . . . . . . . . . . . . . . . . . 25nA (Min)
10nA (Typ)
Ordering Information
PART
NUMBER
PART
MARKING
• High Slew Rate . . . . . . . . . . . . . . . . . . . . . . .50V/s (Min)
65V/s (Typ)
• Wide Power Bandwidth . . . . . . . . . . . . . . . . 750kHz (Min)
• High Input Impedance . . . . . . . . . . . . . . . . . . 50M (Min)
100M (Typ)
• Wide Small Signal Bandwidth . . . . . . . . . . . .12MHz (Typ)
• Fast Settling Time (0.1% of 10V Step) . . . . . . 250ns (Typ)
• Low Quiescent Supply Current . . . . . . . . . . . . 6mA (Max)
• Internally Compensated For Unity Gain Stability
Applications
• Data Acquisition Systems
• RF Amplifiers
TEMP.
RANGE
(oC)
PACKAGE
HA2-2510/883 HA2-2510/883 -55 to 125 8 Pin Can
PKG.
DWG.
#
T8.C
• Video Amplifiers
• Signal Generators
• Pulse Amplification
HA7-2510/883 HA7-2510/883 -55 to 125 8 Ld CERDIP F8.3A
(No longer
available or
supported)
Pinouts
HA-2510/883
(METAL CAN)
TOP VIEW
HA-2510/883
(CERDIP)
TOP VIEW
COMP
BAL
1
-IN
2
+IN
3
V-
4
8
+
8
COMP
7
V+
6
OUT
5
BAL
BAL
1
+
2
-IN
+IN
7
V+
6 OUT
5
3
BAL
4
V-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas LLC 2002, 2004, 2005, 2006, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HA-2510/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VPeak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage 15V
VINCM  1/2 (V+ - V-)
RL  2k
JC
JA
Metal Can Package . . . . . . . . . . . . . . . . . 160oC/W 75oC/W
CERDIP Package. . . . . . . . . . . . . . . . . . . 120oC/W 30oC/W
Package Power Dissipation Limit at 75oC for TJ  175oC
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .625mW
CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .870mW
Package Power Dissipation Derating Factor Above 75oC
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3mW/oC
CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379
for details.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VSUPPLY = 15V, RSOURCE = 100, RLOAD = 500k, VOUT = 0V, Unless Otherwise Specified.
PARAMETER
SYMBOL
Input Offset
Voltage
VIO
Input Bias Current
+IB
CONDITIONS
VCM = 0V
VCM = 0V, +RS = 100k, -RS = 100
-IB
Input Offset
Current
Common Mode
Range
VCM = 0V, +RS = 100, -RS = 100k
IIO
VCM = 0V, +RS = 100k, -RS = 100k
+CMR
V+ = 5V, V- = -25V
-CMR
Large Signal
Voltage Gain
V+ = 25V, V- = -5V
+AVOL
VOUT = 0V and +10V, RL = 2k
-AVOL
Common Mode
Rejection Ratio
VOUT = 0V and -10V, RL = 2k
VCM = +10V, V+ = +5V, V- = -25V, VOUT
= -10V
+CMRR
VCM = -10V, V+ = +25V, V- = -5V, VOUT =
+10V
-CMRR
2
GROUP A
SUBGROUPS
TEMP (oC)
MIN
MAX
UNITS
1
25
-8
8
mV
2, 3
125, -55
-18
10
mV
1
25
-200
200
nA
2, 3
125, -55
-400
400
nA
1
25
-200
200
nA
2, 3
125, -55
-400
400
nA
1
25
-25
25
nA
2, 3
125, -55
-50
50
nA
1
25
+10
-
V
2, 3
125, -55
+10
-
V
1
25
-
-10
V
2, 3
125, -55
-
-10
V
4
25
10
-
kV/V
5, 6
125, -55
7.5
-
kV/V
4
25
10
-
kV/V
5, 6
125, -55
7.5
-
kV/V
1
25
80
-
dB
2, 3
125, -55
80
-
dB
1
25
80
-
dB
2, 3
125, -55
80
-
dB
FN3697.5
August 13, 2015
HA-2510/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: VSUPPLY = 15V, RSOURCE = 100, RLOAD = 500k, VOUT = 0V, Unless Otherwise Specified.
PARAMETER
Output Voltage
Swing
SYMBOL
CONDITIONS
+VOUT
RL = 2k
-VOUT
Output Current
RL = 2k
+IOUT
VOUT = -10V
-IOUT
Quiescent Power
Supply Current
VOUT = +10V
+ICC
VOUT = 0V,
IOUT = 0mA
-ICC
Power Supply
Rejection Ratio
VOUT = 0V,
IOUT = 0mA
VSUP = 10V, V+ = +20V, V- = -15V,
V+ = +10V, V- = -15V
+PSRR
VSUP = 10V, V+ = +15V, V- = -20V,
V+ = +15V, V- = -10V
-PSRR
Offset Voltage
Adjustment
+VIOAdj
Note 2
-VIOAdj
Note 2
GROUP A
SUBGROUPS
TEMP (oC)
MIN
MAX
UNITS
4
25
10
-
V
5, 6
125, -55
10
-
V
4
25
-
-10
V
5, 6
125, -55
-
-10
V
4
25
10
-
mA
5, 6
125, -55
7.5
-
mA
4
25
-
-10
mA
5, 6
125, -55
-
-7.5
mA
1
25
-
6
mA
2, 3
125, -55
-
6.5
mA
1
25
-6
-
mA
2, 3
125, -55
-6.5
-
mA
1
25
80
-
dB
2, 3
125, -55
80
-
dB
1
25
80
-
dB
2, 3
125, -55
80
-
dB
1
25
VIO-1
-
mV
2, 3
125, -55
VIO-1
-
mV
1
25
VIO+1
-
mV
2, 3
125, -55
VIO+1
-
mV
NOTE:
2. Offset adjustment range is [VIO (Measured) 1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VSUPPLY = 15V, RSOURCE = 50, RLOAD = 2k, CLOAD = 50pF, AVCL = +1V/V, Unless Otherwise Specified.
PARAMETER
Slew Rate
SYMBOL
CONDITIONS
VOUT = -5V to +5V, 25% +SR  75%
+SR
VOUT = +5V to -5V, 75% -SR  25%
-SR
Rise and Fall Time
VOUT = 0 to +200mV, 10% tr  90%
tr
VOUT = 0 to -200mV, 10% tf  90%
tf
3
GROUP A
SUBGROUPS
TEMP (oC)
MIN
MAX
UNITS
7
25
50
-
V/s
8A, 8B
125, -55
45
-
V/s
7
25
50
-
V/s
8A, 8B
125, -55
45
-
V/s
7
25
-
50
ns
8A, 8B
125, -55
-
60
ns
7
25
-
50
ns
8A, 8B
125, -55
-
60
ns
FN3697.5
August 13, 2015
HA-2510/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: VSUPPLY = 15V, RSOURCE = 50, RLOAD = 2k, CLOAD = 50pF, AVCL = +1V/V, Unless Otherwise Specified.
PARAMETER
SYMBOL
Overshoot
CONDITIONS
+OS
VOUT = 0 to +200mV
-OS
VOUT = 0 to -200mV
GROUP A
SUBGROUPS
TEMP (oC)
MIN
MAX
UNITS
7
25
-
40
%
8A, 8B
125, -55
-
50
%
7
25
-
40
%
8A, 8B
125, -55
-
50
%
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = 15V, RLOAD = 2k, CLOAD = 50pF, Unless Otherwise Specified.
PARAMETER
SYMBOL
Differential Input
Resistance
RIN
CONDITIONS
VCM = 0V
Full Power
Bandwidth
FPBW
VPEAK = 10V
Minimum Closed Loop
Stable Gain
CLSG
RL = 2k, CL = 50pF
Quiescent Power
Consumption
PC
VOUT = 0V, IOUT = 0mA
NOTES
TEMP (oC)
MIN
MAX
UNITS
3
25
50
-
M
3, 4
25
750
-
kHz
3
-55 to 125
1
-
V/V
3, 5
-55 to 125
-
195
mW
NOTES:
3. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
4. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2VPEAK).
5. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.)
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
SUBGROUPS (SEE TABLES 1 AND 2)
1
1 (Note 6), 2, 3, 4, 5, 6, 7, 8A, 8B
Group A Test Requirements
1, 2, 3, 4, 5, 6, 7, 8A, 8B
Groups C and D Endpoints
1
NOTE:
6. PDA applies to Subgroup 1 only.
4
FN3697.5
August 13, 2015
HA-2510/883
Die Characteristics
SUBSTRATE POTENTIAL (Powered Up):
Unbiased
TRANSISTOR COUNT:
40
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-2510/883
+IN
-IN
BAL
COMP
V-
V+
BAL
OUT
Burn-In Circuit
HA7-2510/883
1
R1
D2
2
-
3
+
4
V-
8
V+
7
6
C3
C1
D1
5
C2
R1 = 1M, 5%, 1/4W (Min)
C1 = C2 = 0.01F/Socket (Min) or 0.1F/Row (Min)
C3 = 0.01F/Socket (10%)
D1 = D2 = 1N4002 or Equivalent/Board
|(V+) - (V-)| = 30V
5
FN3697.5
August 13, 2015
HA-2510/883
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
August 13, 2015
FN3697.5
CHANGE
Added Revision History beginning with Rev 5.
Added About Intersil Verbiage.
Updated Ordering Information Table on page 1.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
6
FN3697.5
August 13, 2015
HA-2510/883
Metal Can Packages (Can)
T8.C MIL-STD-1835 MACY1-X8 (A1)
REFERENCE PLANE
A
8 LEAD METAL CAN PACKAGE
e1
L
L2
L1
INCHES
SYMBOL
ØD2
A
A
k1
Øe
ØD ØD1
2
N
1

Øb1
Øb
F

k
C
L
BASE AND
SEATING PLANE
Q
BASE METAL
Øb1
LEAD FINISH
Øb2
SECTION A-A
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
3.  is the basic spacing from the centerline of the tab to terminal 1
and is the basic spacing of each lead or lead position (N -1
places) from looking at the bottom of the package.
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.165
0.185
4.19
4.70
-
Øb
0.016
0.019
0.41
0.48
1
Øb1
0.016
0.021
0.41
0.53
1
Øb2
0.016
0.024
0.41
0.61
-
ØD
0.335
0.375
8.51
9.40
-
ØD1
0.305
0.335
7.75
8.51
-
ØD2
0.110
0.160
2.79
4.06
-
e
e1
0.200 BSC
5.08 BSC
0.100 BSC
-
2.54 BSC
-
F
-
0.040
-
1.02
-
k
0.027
0.034
0.69
0.86
-
k1
0.027
0.045
0.69
1.14
2
12.70
19.05
1
1.27
1
L
0.500
0.750
L1
-
0.050
L2
0.250
-
6.35
-
1
Q
0.010
0.045
0.25
1.14
-
-

45o BSC
45o BSC
45o BSC
45o BSC
N
8
8

3
3
4
Rev. 0 5/18/94
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
7
FN3697.5
August 13, 2015
HA-2510/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
E
M
(b)
-BC A-B S
SECTION A-A
D S
D
BASE
PLANE
-C-
SEATING
PLANE
Q
A
L
S1

eA
A A
b2
e
b
ccc M
(c)
b1
M
bbb S
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
LEAD FINISH
c1
C A-B S
eA/2
c
aaa M C A - B S D S
D S
INCHES
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
5
E
0.220
0.310
5.59
7.87
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
3.81 BSC
-
eA/2
NOTES:
1. Index area: A notch or a pin one identification mark shall be
located adjacent to pin one and shall be located within the
shaded area shown. The manufacturer’s identification shall not
be used as a pin one identification mark.
MILLIMETERS
L
0.150 BSC
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7

90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
8
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN3697.5
August 13, 2015
Similar pages