DATASHEET

Single 8-Channel CMOS Analog Multiplexer
HI-508/883
Features
The HI-508/883 is an eight channel single-ended multiplexer.
This monolithic CMOS multiplexer includes an array of eight
analog switches, a digital decode circuit for channel selection,
a voltage reference for logic thresholds, and an ENABLE input
for device selection when several multiplexers are present.
• This Circuit is Processed in Accordance to MIL-STD-883 and
is Fully Conformant Under the Provisions of Paragraph 1.2.1.
The Dielectric Isolation (DI) process used in fabrication of this
device eliminates the problem of latch-up. Also, DI offers much
lower substrate leakage and parasitic capacitance than
conventional junction-isolated CMOS. Switches are guaranteed
to break-before-make, so that two channels are never shorted
together. The switching threshold for each digital input is
established by an internal +5V reference, providing a
guaranteed minimum 2.4V for logic “1” and Maximum 0.8V for
logic “0”. This allows direct interface without pull-up resistors
to signals from most logic families: CMOS, TTL, DTL and some
PMOS. For protection against transient overvoltage, the digital
inputs include a series 200Ω resistor and a diode clamp to
each supply. If input overvoltage protection is needed, the
HI-548/883 and HI-549/883 multiplexers are recommended.
For further information see Application Note AN520.
Ordering Information
PART #
PART
MARKING
HI1-0508/883 HI1-508/883
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• TTL/CMOS Compatible . . . . . . . . . . . . . . . . . . 2.4V (Logic “1”)
• Access Time (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0µs
• 44V Maximum Power Supply
• Break-Before-Make Switching
• No Latch-up
Applications
• Data Acquisition Systems
• Precision Instrumentation
• Demultiplexing
• Selector Switch
Functional Diagram
TEMP. RANGE
(°C)
-55 to 125
• Low On Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400Ω
PACKAGE
PKG.
DWG. #
16 Ld CerDIP F16.3
Pin Configuration
OUT
IN 1
IN 2
DECODER/
DRIVER
IN 8
HI-508/883
(16 LD CERDIP)
TOP VIEW
A0 1
16 A1
ENABLE 2
15 A2
LEVEL
SHIFT
† DIGITAL INPUT
PROTECTION
†
†
†
†
14 GND
-VSUPPLY 3
May 3, 2012
FN8290.0
5V
REF
IN 1 4
13 +VSUPPLY
IN 2 5
12 IN 5
IN 3 6
11 IN 6
IN 4 7
10 IN 7
OUT 8
9 IN 8
1
A1 A2
A0
EN
TRUTH TABLE HI-508/883
A2
A1
A0
EN
“ON” CHANNEL
X
X
X
L
None
L
L
L
H
1
L
L
H
H
2
L
H
L
H
3
L
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HI-508/883
Absolute Maximum Ratings
Thermal Information
Voltage Between Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
+VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
-VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
Analog Input Voltage, +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +2V
Analog Input Voltage, -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -2V
Digital Input Voltage, +VEN, +VA . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V
Digital Input Voltage, - VEN, -VA . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY +4V
or 20mA, whichever occurs first
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed at 1ms, 10% Duty Cycle Max) . . . . . . . . 40mA
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤2000V
Thermal Resistance
θJA (°C/W) θJC (°C/W)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . .
83
21
Power Dissipation (At +75°C)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.20W
Power Dissipation Derating Factor (Above +75°C)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0mW/°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . .+275°C
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage (±VSUPPLY) . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V
Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.4V to +VSUPPLY
Max RMS Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 2.4V, unless otherwise specified.
D.C. PARAMETERS
Input Leakage Current
SYMBOL
IIH
IIL
Source “OFF”
Leakage Current
+IS(OFF)
-IS(OFF)
Drain “OFF”
Leakage Current
+ID(OFF)
-ID(OFF)
Channel “ON”
Leakage Current
+ID(ON)
-ID(ON)
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
Measure inputs sequentially,
connect all unused inputs to GND
1, 2, 3
+25, +125, -55
-1.0
1.0
µA
1, 2, 3
+25, +125, -55
-1.0
1.0
µA
VS = +10V, VD = -10V, VEN = 0.8V,
All unused inputs = -10V
1
+25
-10
10
nA
2, 3
+125, -55
-50
50
nA
1
+25
-10
10
nA
2, 3
+125, -55
-50
50
nA
1
+25
-10
10
nA
2, 3
+125, -55
-200
200
nA
1
+25
-10
10
nA
2, 3
+25 to +125
-200
200
nA
1
+25
-10
10
nA
2, 3
+125, -55
-200
200
nA
1
+25
-10
10
nA
2, 3
+125, -55
-200
200
nA
CONDITIONS
VS = -10V, VD = +10V, VEN = 0.8V,
All unused inputs = +10V
VD = +10V, VEN = 0.8V,
All unused inputs = -10V
VD = -10V, VEN = 0.8V,
All unused inputs = +10V
VS = VD = +10V
All unused inputs = -10V
VS = VD = -10V
All unused inputs = +10V
Positive Supply Current
+I
VA = 0V, VEN = 2.4V
1, 2, 3
+25, +125, -55
-
2.4
mA
Negative Supply Current
-I
VA = 0V, VEN = 2.4V
1, 2, 3
+25, +125, -55
-1.0
-
mA
Standby Positive Supply
Current
+ISBY
VA = 0V, VEN = 0V
1, 2, 3
+25, +125, -55
2.4
mA
Standby Negative Supply
Current
-ISBY
VA = 0V, VEN = 0V
1, 2, 3
+25, +125, -55
-1.0
-
mA
Switch “ON” Resistance
+RDS1
1
+25
-
300
Ω
2, 3
+125, -55
-
400
Ω
1
+25
-
300
Ω
2, 3
+125, -55
-
400
Ω
-RDS1
2
VS = 10V, ID = 1mA
VS = -10V, ID = -1mA
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HI-508/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 2.4V, unless otherwise specified.
D.C. PARAMETERS
SYMBOL
Logic Level Voltage
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
VAL
Note 1
1, 2, 3
+25, +125
-
0.8
V
VAH
Note 1
1, 2, 3
-55
2.4
-
V
MAX
UNITS
TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 2.4V, unless otherwise specified.
PARAMETERS
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
25
Break-Before-Make Time
Delay
tD
RL = 200Ω, CL = 12.5pF
9
+25
Propagation Delay Times:
Address Inputs to I/O
Channel Times
tA
RL = 10MΩ, CL = 14pF
9
+25
500
ns
10, 11
+125, -55
1000
ns
9
+25
500
ns
10, 11
+125, -55
1000
ns
9
+25
500
ns
10, 11
+125, -55
1000
ns
MAX
UNITS
Enable to I/O
tON(EN)
tOFF(EN)
RL = 200Ω, CL = 12.5pF
RL = 200Ω, CL = 12.5pF
ns
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 2.4V, unless otherwise specified.
PARAMETERS
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
(°C)
MIN
Capacitance Address Input
CA
V+ = V- = 0V, f = 1MHz
2
+25
10
pF
Capacitance Output Switch
COS
V+ = V- = 0V
f = 1MHz
2
+25
45
pF
Capacitance Input Switch
CIS
V+ = V- = 0V, f = 1MHz
2
+25
12
pF
2
+25
10
mV
2, 3
+25
Charge Transfer Error
VCTE
VS = GND, VGEN = 0V to 5V
Off Isolation
VISO
VEN = 0.8V, RL = 1kΩ, CL = 15pF,
VS = 7VRMS, f = 100kHz
-50
dB
NOTES:
1. Used for forcing conditions for all DC Tests, unless otherwise specified.
2. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design release and upon design changes which would affect these characteristics.
3. Worst case isolation occurs on channel 4 due to proximity of the output pins.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-in)
Final Electrical Test Parameters
Group A Test Requirements
Groups C & D Endpoints
SUBGROUPS (See Tables 1, 2, 3)
1
1 (Note 4), 2, 3, 9, 10, 11
1, 2, 3, 9, 10, 11
1
NOTE:
4. PDA applies to Subgroup 1 only. No other subgroups are included in PDA.
3
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HI-508/883
Test Circuits
INPUT LEAKAGE CURRENT
ID(OFF)
IS(OFF)
ID(OFF)
ID(ON)
SUPPLY CURRENTS
CHARGE TRANSFER ERROR
ID(ON)
OFF CHANNEL ISOLATION
RDS
R
ON
V
M
= --------I
D
D
(1) Includes all factors and
scope or voltmeter
capacitance
4
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HI-508/883
Switching Waveforms
BREAK-BEFORE-MAKE DELAY (tOPEN)
BREAK-BEFORE-MAKE DELAY (tOPEN)
+15V
3.5V
ADDRESS
DRIVE (VA)
0V
IN 1
50Ω
A1
50%
+3.5V
tOPEN
VA INPUT
2V/DIV.
IN 2
THRU
IN 7
VA
OUTPUT
50%
+5V
A2
CH 1 ON
HI-508/883
A0
IN 8
EN
OUT
V-
GND
CH 8 ON
VOUT
200Ω
OUTPUT
1V/DIV.
12.5pF
-15V
100ns/DIV.
ACCESS TIME vs LOGIC LEVEL (HIGH)
ACCESS TIME
+15V
V+
ADDRESS
DRIVE (VA)
50%
0V
+10V
90%
tA
CH 1 ON
A1 HI-508/883
50Ω
OUTPUT
IN 2
THRU
IN 7
A2
VA
VA INPUT
2V/DIV.
±10V
IN 1
A0
±
3.5V
IN 8
10V
PROBE
-10V
3.5V
EN
GND
OUT
V-
OUTPUT
5V/DIV.
10MΩ
14pF
-15V
CH 8 ON
200ns/DIV.
ENABLE DELAY
tON(EN), tOFF(EN)
ENABLE DELAY
tON(EN), tOFF(EN)
ENABLE DRIVE
+15V
3.6V
A2
0V
A1
OUTPUT
A0
90%
t ON(EN)
ENABLE DRIVE
2V/DIV.
HI-548/883
50%
90%
+10V
IN 1
50Ω
(EN)
CH1 ON
OUT
EN
VA
t OFF
IN 2
THRU
IN 8
GND
V-
200Ω
-15V
OUTPUT
2V/DIV.
12.5pF
CH1 OFF
100ns/DIV.
5
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HI-508/883
Burn-In Circuit
HI-508/883 CERDIP
5V
-15V
D1
C1
1
A0
A1 16
2
ENABLE
A2 15
3
-V
4
IN 1
GND 14
+15V
+V 13
D2
R1
5
IN 2
IN 5 12
6
IN 3
IN 6 11
7
IN 4
IN 7 10
8
OUT
IN 8 9
C2
10kΩ
NOTES:
R1 = 10kΩ ± 5% 1/2W or 1/4W (per socket)
C1, C2 = 0.01µF (per socket) or 0.1µF (per row)
D1, D2 = 1N4002 (or equivalent) (per board)
6
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HI-508/883
Schematic Diagrams
ADDRESS DECODER
V+
P
P
P
A0 OR A0
A1 OR A1
P
P
P
N
N
N
TO P-CHANNEL
DEVICE OF
THE SWITCH
N
N
TO N-CHANNEL
DEVICE OF
THE SWITCH
A2 OR A2
N
ENABLE
V-
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
V+
P3
P5
P1
A
P4
N1
V+
D1
P6
P7
N6
N7
P8
P9
P10
N9
N10
VL
200Ω
VR
D2
AIN
N8
P2
V-
N4
A
N5
N2
N3
V-
All N-Channel bodies to V-, all P-Channel bodies to V+, unless otherwise indicated.
7
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HI-508/883
Schematic Diagrams
(Continued)
MULTIPLEX SWITCH
FROM DECODE
N18
V+
N17
N19
P17
IN
OUT
V+
P18
FROM DECODE
TTL REFERENCE CIRCUIT
V+
P15
Q1P
Q2P
Q3P
Q4P
Q5N
Q8N
Q6P
Q7P
VR
P16
R2
VL
N12
D3
R3
N13
N14
N15
Q12N
GND
V-
8
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HI-508/883
Die Characteristics
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
DIE DIMENSIONS:
81.9mils x 90.2mils x 19mils
TRANSISTOR COUNT:
243
METALLIZATION:
PROCESS:
Type: Al
Thickness: 16kÅ ±2kÅ
CMOS-DI
GLASSIVATION:
Type: Nitride
Thickness: 7kÅ ± 0.7kÅ
Metallization Mask Layout
HI-508/883
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HI-508/883
Design Information
The information contained in this section has been developed through characterization and is for use as
application and design information only. No guarantee is implied.
400
100nA
300
10nA
LEAKAGE CURRENT (A)
ON RESISTANCE (Ω)
Typical Performance Curves
+125°C
200
+25°C
100
-55°C
0
-15
-10
-5
0
5
VIN ANALOG INPUT (V)
10
OFF OUTPUT
LEAKAGE CURRENT
ID(OFF)
ID(ON)
1nA
OFF INPUT
LEAKAGE CURRENT
IS(OFF)
100pA
10pA
25
15
FIGURE 1. ON RESISTANCE vs ANALOG INPUT VOLTAGE,
TEMPERATURE
50
125
8
60
VSUPPLY = ±15V
-55°C
50
SUPPLY CURRENT (mA)
SWITCH CURRENT (mA)
100
FIGURE 2. LEAKAGE CURRENT vs TEMPERATURE
70
+25°C
40
+125°C
30
20
6
4
2
10
0
75
TEMPERATURE (°C)
VSUPPLY = ±10V
0
2
4
6
8
10
12
VOLTAGE ACROSS SWITCH (±VIN)
FIGURE 3. ON CHANNEL CURRENT vs VOLTAGE
10
14
16
0
1K
10K
100K
TOGGLE FREQUENCY (Hz)
1M
10M
FIGURE 4A. SUPPLY CURRENT vs TOGGLE FREQUENCY
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
SYMBOL
E
M
-Bbbb S
C A-B S
-C-
2
0.36
0.58
3
1.14
1.65
-
0.045
0.58
1.14
4
0.018
0.20
0.46
2
0.008
0.015
0.20
-
0.840
0.36
b1
0.014
0.023
b2
0.045
0.065
b3
0.023
c
0.008
c1
D
E
0.220
α
eA
eA/2
aaa M C A - B S
D S
-
0.66
0.026
A A
ccc M C A - B S
5.08
0.200
A
e
-
0.014
b2
b
MAX
b
L
S1
MIN
A
Q
SEATING
PLANE
MAX
M
(b)
D
BASE
PLANE
MILLIMETERS
MIN
b1
SECTION A-A
D S
INCHES
(c)
c
e
D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be measured
at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
lead paddle. For this configuration dimension b3 replaces dimension
b2.
0.310
5.59
0.100 BSC
NOTES
0.38
3
21.34
5
7.87
5
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
α
90o
105o
90o
-
7
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
16
5. This dimension allows for off-center lid, meniscus, and glass overrun.
16
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
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