DATASHEET

DATASHEET
Single 16/Differential 8-Channel CMOS Analog
Multiplexers with Active Overvoltage Protection
HI-546/883, HI-547/883
Features
The HI-546/883 and HI-547/883 are analog multiplexers with
active overvoltage protection and guaranteed rON matching.
Analog input levels may greatly exceed either power supply
without damaging the device or disturbing the signal path of
other channels. Active protection circuitry assures that signal
fidelity is maintained even under fault conditions that would
destroy other multiplexers.
• This circuit is processed in accordance to MIL-STD-883 and
is fully conformant under the provisions of Paragraph 1.2.1.
Analog inputs can withstand constant 70VP-P levels with ±15V
supplies. Digital inputs will also sustain continuous faults up to
4V greater than either supply. In addition, signal sources are
protected from short circuiting should multiplexer supply loss
occur. Each input presents 1kΩ of resistance under this
condition. These features make the HI-546/883 and
HI-547/883 ideal for use in systems where the analog inputs
originate from external equipment or separately powered
circuitry. Both devices are fabricated with 44V dielectrically
isolated CMOS technology. The HI-546/883 is a single
16-channel, and the HI-547/883 is an 8-channel differential
version. If input overvoltage protection is not needed, the
HI-506/883 and HI-507/883 multiplexers are recommended.
For further information see application note AN520.
• Analog signal range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• No channel interaction during overvoltage
• Guaranteed rON matching
• 44V maximum power supply
• Break-before-make switching
• Access time (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0µs
• Power dissipation (max) . . . . . . . . . . . . . . . . . . . . . . . . 45mW
Applications
• Data acquisition systems
• Control systems
• Telemetry
Ordering Information
PART #
PART
MARKING
HI1-0546/883 HI1-546/883
TEMP. RANGE
(°C)
PACKAGE
-55 to +125 28 Ld CerDIP F28.6
HI4-0546/883 HI4-0546 /883 -55 to +125 28 Ld CLCC
HI1-0547/883 HI1-547/883
1
J28.A
-55 to +125 28 Ld CerDIP F28.6
HI4-0547/883 HI4-0547 /883 -55 to +125 28 Ld CLCC
November 19, 2014
FN7994.1
PKG.
DWG. #
J28.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 1989, 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HI-546/883, HI-547/883
Pin Configurations
HI-547/883
(28 LD CERDIP)
TOP VIEW
HI-546/883
(28 LD CERDIP)
TOP VIEW
+VSUPPLY
+VSUPPLY
28 OUT
1
28 OUT A
1
OUT B 2
27 -VSUPPLY
NC 2
27 -VSUPPLY
NC 3
26 IN 8
NC 3
26 IN 8A
IN 16 4
25 IN 7
IN 8B 4
25 IN 7A
IN 15 5
24 IN 6
IN 7B 5
24 IN 6A
IN 14 6
23 IN 5
IN 6B 6
23 IN 5A
IN 13 7
22 IN 4
IN 5B 7
22 IN 4A
IN 12 8
21 IN 3
IN 4B 8
21 IN 3A
9
20 IN 2
IN 3B 9
20 IN 2A
IN 10 10
19 IN 1
IN 2B 10
19 IN 1A
18 ENABLE
IN 1B 11
18 ENABLE
IN 11
IN 9 11
GND 12
17 ADDRESS A0
GND 12
17 ADDRESS A0
VREF 13
16 ADDRESS A1
VREF 13
16 ADDRESS A1
ADDRESS A3 14
15 ADDRESS A2
NC 14
15 ADDRESS A2
HI-547/883
(28 LD CLCC)
TOP VIEW
IN 16
NC
NC
+VSUPPLY
OUT
-VSUPPLY
IN 8
IN 8B
NC
OUT B
+VSUPPLY
OUT A
-VSUPPLY
IN 8A
HI-546/883
(28 LD CLCC)
TOP VIEW
4
3
2
1
28
27
26
4
3
2
1
28
27
26
IN 15 5
25 IN 7
IN 7B 5
25 IN 7A
IN 14 6
24 IN 6
IN 6B 6
24 IN 6A
IN 13 7
23 IN 5
IN 5B 7
23 IN 5A
IN 12 8
22 IN 4
IN 4B 8
22 IN 4A
IN 11 9
21 IN 3
IN 3B 9
21 IN 3A
20 IN 2
IN 2B 10
20 IN 2A
19 IN 1
IN 1B 11
19 IN 1A
IN 10 10
12
13
14
15
16
17
18
12
13
14
15
16
17
18
GND
VREF
A3
A2
A1
A0
ENABLE
GND
VREF
NC
A2
A1
A0
ENABLE
IN 9 11
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HI-546/883, HI-547/883
Functional Diagrams
HI-546/883
TRUTH TABLE HI-546/883
OUT
1k
IN 1
IN 2
1k
DECODER/
DRIVER
1k
IN 16
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
5V
REF
LEVEL
SHIFT
† DIGITAL INPUT
PROTECTION
†
†
†
†
†
VREF A0 A1 A2 A3 EN
A3
A2
A1
A0
EN
“ON” CHANNEL
X
X
X
X
L
None
L
L
L
L
H
1
L
L
L
H
H
2
L
L
H
L
H
3
L
L
H
H
H
4
L
H
L
L
H
5
L
H
L
H
H
6
L
H
H
L
H
7
L
H
H
H
H
8
H
L
L
L
H
9
H
L
L
H
H
10
H
L
H
L
H
11
H
L
H
H
H
12
H
H
L
L
H
13
H
H
L
H
H
14
H
H
H
L
H
15
H
H
H
H
H
16
HI-547/883
TRUTH TABLE HI-547/883
1k
OUT A
IN 1A
1k
IN 8A
IN 1B
OUT B
1k
1k
DECODER/
DRIVER
IN 8B
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
5V
REF
LEVEL
SHIFT
† DIGITAL INPUT
PROTECTION
†
VREF A0
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3
†
†
†
A1
A2
EN
A2
A1
A0
EN
“ON” CHANNEL PAIR
X
X
X
L
None
L
L
L
H
1
L
L
H
H
2
L
H
L
H
3
L
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
FN7994.1
November 19, 2014
HI-546/883, HI-547/883
Absolute Maximum Ratings
Thermal Information
Voltage Between Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
+VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
-VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Analog Input Voltage, +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +20V
Analog Input Voltage, -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -20V
Digital Input Voltage, +VEN, +VA . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V
Digital Input Voltage, - VEN, -VA . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY +4V
or 20mA, whichever occurs first
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed at 1ms, 10% Duty Cycle Max) . . . . . . . . 40mA
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤2000V
Thermal Resistance
JA (°C/W) JC (°C/W)
CerDIP Package (Notes 1, 2). . . . . . . . . . . .
50
18
CLCC Package (Notes 1, 2) . . . . . . . . . . . . .
81
20
Power Dissipation
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0W
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.23W
Power Dissipation Derating Factor (Above +75°C)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.0mW/°C
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3mW/°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . +275°C
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Operating Supply Voltage (±VSUPPLY) . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V
Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4V to VSUPPLY
Max RMS Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For JC, the "case temp" location is the center of the ceramic on the package underside.
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified.
D.C. PARAMETERS
Input Leakage Current
SYMBOL
IIH
IIL
Source “OFF”
Leakage Current
+IS(OFF)
-IS(OFF)
Drain “OFF”
Leakage Current
+ID(OFF)
-ID(OFF)
Channel “ON”
Leakage Current
+ID(ON)
-ID(ON)
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4
CONDITIONS
Measure inputs sequentially,
connect all unused inputs to GND
VS = +10V, VD = -10V, VEN = 0.8V,
All unused inputs = -10V
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
1, 2, 3
+25, +125, -55
-1.0
1.0
µA
1, 2, 3
+25, +125, -55
-1.0
1.0
µA
1
+25
-10
10
nA
2, 3
+125, -55
-50
50
nA
1
+25
-10
10
nA
2, 3
+125, -55
-50
50
nA
1
+25
-10
10
nA
HI-546/883
2, 3
+125, -55
-300
300
nA
HI-547/883
2, 3
+125, -55
-200
200
nA
1
+25
-10
10
nA
HI-546/883
2, 3
+25 to +125
-300
300
nA
HI-547/883
2, 3
+125, -55
-200
200
nA
1
+25
-10
10
nA
HI-546/883
2, 3
+125, -55
-300
300
nA
HI-547/883
2, 3
+125, -55
-200
200
nA
1
+25
-10
10
nA
HI-546/883
2, 3
+125, -55
-300
300
nA
HI-547/883
2, 3
+125, -55
-200
200
nA
VS = -10V, VD = +10V, VEN = 0.8V,
All unused inputs = +10V
VD = +10V, VEN = 0.8V,
All unused inputs = -10V
VD = -10V, VEN = 0.8V,
All unused inputs = +10V
VIN (selected channels) = VD = +10V
VS = unused inputs = -10V
VIN (selected channels) = VD = -10V
VS = unused inputs = +10V
FN7994.1
November 19, 2014
HI-546/883, HI-547/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified.
D.C. PARAMETERS
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
1, 2, 3
+25, +125, -55
-2.0
2.0
µA
1, 2, 3
+25, +125, -55
-2.0
2.0
µA
ID(OFF)
Overvoltage Protected,
VS = 33V, VD = 0V, VEN = 0.8V
Leakage Current Into the
Overvoltage VS applied at ≤25% duty cycle
Drain Terminal of an “OFF”
VS = -33V, VD = 0V, VEN = 0.8V
Switch
VS applied at ≤25% duty cycle
Positive Supply Current
+I
VA = 0V, VEN = 4.0V
1, 2, 3
+25, +125, -55
-
2.0
mA
Negative Supply Current
-I
VA = 0V, VEN = 4.0V
1, 2, 3
+25, +125, -55
-1.0
-
mA
Standby Positive Supply
Current
+ISBY
VA = 0V, VEN = 0V
1, 2, 3
+25, +125, -55
2.0
mA
Standby Negative Supply
Current
-ISBY
VA = 0V, VEN = 0V
1, 2, 3
+25, +125, -55
--1.0
-
mA
Switch “ON” Resistance
+rDS1
VS = 10V, ID = 100µA
1
+25
-
1500
Ω
2, 3
+125, -55
-
1800
Ω
-rDS1
Logic Level Voltage
Difference in Switch “ON”
Resistance Between
Channels
VS = -10V, ID = -100µA
1
+25
-
1500
Ω
2, 3
+125, -55
-
1800
Ω
VAL1
Notes 3, 4
1, 2, 3
+25, +125, -55
-
0.8
V
VAH1
Notes 3, 4
1, 2, 3
+25, +125, -55
4.0
-
V
VAL2
Note 5
1, 2, 3
+25, +125, -55
-
0.8
V
VAH2
Note 5
1, 2, 3
+25, +125, -55
6.0
-
V
+rDS1
 +r DS1 MAX  –  +r DS1 MIN   100
-------------------------------------------------------------------------------------------+r DS1 AVE
1
+25
-
7
%
-rDS1
 -r DS1 MAX  –  -r DS1 MIN   100
-----------------------------------------------------------------------------------------r DS1 AVE
1
+25
-
7
%
MAX
UNITS
TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified.
PARAMETERS
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
25
Break-Before-Make Time
Delay
tD
RL = 1kΩ, CL = 12.5pF
9
+25
Propagation Delay Times:
Address Inputs to I/O
Channel Times
tA
RL = 10MΩ, CL = 14pF
9
+25
500
ns
10, 11
+125, -55
1000
ns
9
+25
500
ns
10, 11
+125, -55
1000
ns
9
+25
500
ns
10, 11
+125, -55
1000
ns
MAX
UNITS
Enable to I/O
tON(EN)
tOFF(EN)
RL = 1kΩ, CL = 12.5pF
RL = 1kΩ, CL = 12.5pF
ns
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified.
PARAMETERS
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
(°C)
6
+25
12
pF
MIN
Capacitance Address Input
CA
V+ = V- = 0V, f = 1MHz
Capacitance Output Switch
COS
V+ = V- = 0V
HI-546/883
6
+25
85
pF
f = 1MHz
HI-547/883
6
+25
50
pF
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TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: VSUPPLY = 15V, VSUPPLY = 15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified. (Continued)
PARAMETERS
NOTE
TEMPERATURE
(°C)
V+ = V- = 0V, f = 1MHz
6
SYMBOL
Capacitance Input Switch
CIS
CONDITIONS
Charge Transfer Error
VCTE
VS = GND, VGEN = 0V to 5V
Off Isolation
VISO
VEN = 0.8V, RL = 1kΩ, CL = 15pF,
VS = 7VRMS, f = 100kHz
MIN
MAX
UNITS
+25
15
pF
6
+25
10
mV
6, 7
+25
-50
dB
NOTES:
3. Used for forcing conditions for all DC Tests, unless otherwise specified.
4. To drive from DTL/TTL circuits, 1kΩ pull-up resistors to +5.0V supply are recommended.
5. VREF = +10V.
6. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design release and upon design changes which would affect these characteristics.
7. Worst case isolation occurs on channel 8B due to proximity of the output pins.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-in)
Final Electrical Test Parameters
Group A Test Requirements
Groups C & D Endpoints
SUBGROUPS (See Tables 1, 2, 3)
1
1 (Note 8), 2, 3, 9, 10, 11
1, 2, 3, 9, 10, 11
1
NOTE:
8. PDA applies to Subgroup 1 only. No other subgroups are included in PDA.
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HI-546/883, HI-547/883
Test Circuits
INPUT LEAKAGE CURRENT
ID(OFF)
IS(OFF)
ID(ON)
ID(OFF) OVERVOLTAGE
RDS
SUPPLY CURRENTS
CHARGE TRANSFER ERROR
OFF CHANNEL ISOLATION
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Switching Waveforms
BREAK-BEFORE-MAKE DELAY (tOPEN)
BREAK-BEFORE-MAKE DELAY (tOPEN)
*SIMILAR CONNECTION FOR HI-547/883
ACCESS TIME vs LOGIC LEVEL (HIGH)
ACCESS TIME
*SIMILAR CONNECTION FOR HI-547/883
ENABLE DELAY
tON(EN), tOFF(EN)
ENABLE DELAY
tON(EN), tOFF(EN)
*SIMILAR CONNECTION FOR HI-547/883
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HI-546/883, HI-547/883
Burn-In Circuits
HI-546/883, HI-547/883 CERDIP
NOTES:
R1, R2 = 10kΩ ±5% 1/2W or 1/4W (per socket)
C1, C2 = 0.01µF (per socket) or 0.1µF (per row)
D1, D2 = 1N4002 (or equivalent) (per board)
HI-546/883, HI-547/883 CLCC
NOTES:
R1, R2 = 10kΩ ±5% 1/2W or 1/4W (per socket)
C1, C2 = 0.01µF (per socket) or 0.1µF (per row)
D1, D2 = 1N4002 (or equivalent) (per board)
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Schematic Diagrams
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
TTL REFERENCE
CIRCUIT
V+
R10
R9
Q1
VREF
Q4
D3
GND
LEVEL SHIFTER
V+
OVERVOLTAGE
PROTECTION
P
P
P
N
R2
P
P
P
P
R5
V+
R3
D1
P
LEVEL
SHIFTED
ADDRESS
TO
DECODE
R7
R6
N
P
R4
D2
R1
200Ω
P
N
N
N
N
R8
N
N
N
N
V-
GND
V-
ADD
IN
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HI-546/883, HI-547/883
Schematic Diagrams
(Continued)
ADDRESS DECODER
V+
P
P
P
P
A0 OR A0
A1 OR A1
P
P
P
N
N
N
N
N
A2 OR A2
TO P-CHANNEL
DEVICE OF
THE SWITCH
TO N-CHANNEL
DEVICE OF
THE SWITCH
N
A3 OR A3
N
ENABLE
DELETE A3 OR A3 INPUT FOR HI-547/883
V-
MULTIPLEX SWITCH
FROM
DECODE
OVERVOLTAGE PROTECTION
N
V+
P
R11
1k
D6
Q5
D7
D4
D5
N
IN
OUT
N
Q6
V-
P
FROM
DECODE
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HI-546/883, HI-547/883
Die Characteristics
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
DIE DIMENSIONS:
TRANSISTOR COUNT:
83.9 mils x 159 mils x 19 mils
485
METALLIZATION:
PROCESS:
Type: Al
Thickness: 16kÅ ±2kÅ
CMOS-DI
GLASSIVATION:
Type: Nitride
Thickness: 7kÅ ± 0.7kÅ
Metallization Mask Layouts
HI-546/883
EN
(18)
A0
(17)
A1 A2
(16) (15)
A3 VREF
(14) (13)
HI-547/883
GND
(12)
EN
(18)
A0
(17)
A1 A2
(16) (15)
NC VREF
(14) (13)
GND
(12)
IN 1
(19)
IN 9
(11)
IN 1A
(19)
IN 2
(20)
IN 10
(10)
IN 2A
(20)
IN 1B
(11)
IN 2B
(10)
IN 3
(21)
IN 11
(9)
IN 3A
(21)
IN 3B
(9)
IN 4
(22)
IN 12
(8)
IN 4A
(22)
IN 4B
(8)
IN 5
(23)
IN 6
(24)
IN 13
(7)
IN 14
(6)
IN 5A
(23)
IN 6A
(24)
IN 5B
(7)
IN 6B
(6)
IN 7
(25)
IN 15
(5)
IN 7A
(25)
IN 7B
(5)
IN 8
(26)
IN 16
(4)
IN 8A
(26)
IN 8B
(4)
V- (27)
OUT (28)
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+V (1)
12
NC (2)
V- (27)
OUT A (28)
+V (1)
OUT B(2)
FN7994.1
November 19, 2014
HI-546/883, HI-547/883
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
November 19, 2014
FN7994.1
Ordering Information table on page 1, in "Part Marking" col, the last 2 entries swapped places. "HI1 ..." moved
to the 3rd row, and "HI4 ..." moved to the last row.
Page 4 - added Theta JA and Theta JC Notes 1 and 2.
Revision History and About Intersil sections added to page 13.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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13
FN7994.1
November 19, 2014
HI-546/883, HI-547/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
(c)
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
b2
b
ccc M
C A-B S
eA/2
-
0.232
-
5.92
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
1.490
-
37.85
5
E
0.500
0.610
15.49
5
c
aaa M C A - B S D S
D S
NOTES
0.014
eA
e
MAX
b

A A
MIN
A
A
L
MILLIMETERS
MAX
M
(b)
D
BASE
PLANE
MIN
b1
SECTION A-A
D S
INCHES
SYMBOL
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
12.70
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
-
eA/2
0.300 BSC
7.62 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

90o
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
N
28
28
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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14
FN7994.1
November 19, 2014
HI-546/883, HI-547/883
Ceramic Leadless Chip Carrier Packages (CLCC)
J28.A
MIL-STD-1835 CQCC1-N28 (C-4)
28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES
D3
SYMBOL
j x 45o
E3
B
E
h x 45o
0.010 S E F S
A
A1
PLANE 2
PLANE 1
-E-
B1
e
L
-H-
L3
MILLIMETERS
MAX
MAX
NOTES
A
0.060
0.100
1.52
2.54
6, 7
0.050
0.088
1.27
2.23
-
B
-
-
-
-
-
B1
0.022
0.028
0.56
0.71
2, 4
B2
0.072 REF
1.83 REF
-
B3
0.006
0.022
0.15
0.56
-
D
0.442
0.460
11.23
11.68
-
D1
0.300 BSC
7.62 BSC
-
D2
0.150 BSC
3.81 BSC
-
D3
-
0.460
E
0.442
0.460
11.23
11.68
2
11.68
-
E1
0.300 BSC
7.62 BSC
-
E2
0.150 BSC
3.81 BSC
-
E3
e
-
0.460
0.050 BSC
0.015
-
-
11.68
1.27 BSC
0.38
2
-
-
2
h
0.040 REF
1.02 REF
5
j
0.020 REF
0.51 REF
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.90
2.41
-
L3
0.003
0.015
0.08
0.038
-
ND
7
7
3
NE
7
7
3
N
28
28
-F-
3
Rev. 0 5/18/94
B3
E1
E2
MIN
A1
e1
0.007 M E F S H S
MIN
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
L2
B2
L1
D2
e1
D1
NOTES:
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
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15
FN7994.1
November 19, 2014
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