DATASHEET

HA-5101/883
®
Data Sheet
August 17, 2005
Low Noise, High Performance Operational
Amplifier
The HA-5101/883 is a dielectrically isolated operational
amplifier featuring low noise and high performance. This
amplifier has an excellent noise voltage density of
4.5nV/√Hz (max) at 1kHz. The unity gain stable
HA-5101/883 yields a 10MHz unity gain bandwidth and a
6V/µs slew rate.
FN3931.1
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Noise Voltage @ 1kHz . . . . . . . . . . . 4.5nV/√Hz Max
• Low Noise Current @ 1kHz . . . . . . . . . . . . . 3pA/√Hz Max
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . 10MHz Min
DC characteristics of the HA-5101/883 assure accurate
performance. The 3mV (max) offset voltage is externally
adjustable and offset voltage drift is just 3µV/°C. Low bias
currents (200nA max) reduce input current errors and the
high open loop voltage gain of 100kV/V, over temperature,
increases the loop gain for low distortion amplification.
• High Gain (Full Temp) . . . . . . . . . . . . . . . . . .100kV/V Min
(Room Temp) . . . . . . . . . . . . . . . . . 1MV/V Typ
The HA-5101/883 is ideal for audio applications, especially
low-level signal amplifiers such as microphone, tape head
and preamplifiers. Additionally, it is well suited for low
distortion oscillators, low noise function generators and high
Q filters.
Applications
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/µs Min
• High CMRR/PSRR (Full Temp) . . . . . . . . . . . . . 80dB Min
• High Output Drive Capability (Full Temp) . . . . . . . . . 25mA
• High Quality Audio Preamplifiers
• High Q Active Filters
• Low Noise Function Generators
• Low Distortion Oscillators
• Low Noise Comparators
Ordering Information
PART NUMBER
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
HA7-5101/883
-55 to 125
8 Ld CerDIP
F8.3A
5962-89636012A
-55 to 125
20 Ld Ceramic LCC J20.A
Pinouts
1
8
NC
-IN
2
7
V+
-
NC
4
-IN
5
NC
BAL
NC
TOP VIEW
NC
TOP VIEW
BAL
5962-896360 (CLCC)
NC
HA7-5101/883 (CERDIP)
3
2
1
20
19
18 NC
17 V+
-
V-
4
5
BAL
1
16 NC
NC
6
+IN
7
15 OUT
NC
8
14 NC
+
9
10
11
12
13
NC
OUT
BAL
6
NC
3
V-
+IN
NC
+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1994, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HA-5101/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . V+ to VInput Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite
Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Thermal Resistance
θJA (°C/W) θJC (°C/W)
Ceramic DIP Package . . . . . . . . . . . . .
120
30
Ceramic LCC Package. . . . . . . . . . . . .
86
26
Package Power Dissipation Limit at +75°C for TJ ≤ +175°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.22W
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.35W
Package Power Dissipation Derating Factor Above +75°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . .12.2mW/°C
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/°C
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C
Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . ±5V to ±15V
VINcm ≤ 1/2 (V+ - V-)
RL ≥ 500Ω
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VS= ±15V, RS = 100Ω, RL = 500kΩ, VOUT = 0V, Unless Otherwise Specified
PARAMETER
SYMBOL
Input Offset Voltage
VIO
Input Bias Current
+IB
-IB
Input Offset Current
IIO
Common Mode Range
+CMR
-CMR
Large Signal Voltage Gain
+AVOL
-AVOL
Common Mode Rejection Ratio
+CMRR
-CMRR
2
TEST CONDITIONS
VCM = 0V
VCM = 0V
+RS = 100kΩ
-RS = 100Ω
VCM = 0V
+RS = 100Ω
-RS = 100kΩ
VCM = 0V
+RS = 100kΩ
-RS = 100kΩ
V+ = 3V
V- = -27V
V+ = 27V
V- = -3V
GROUP A
SUBGROUP TEMP (°C)
LIMITS
MIN
MAX
UNITS
1
+25
-3
3
mV
2, 3
+125, -55
-4
4
mV
1
+25
-200
200
nA
2, 3
+125, -55
-325
325
nA
1
+25
-200
200
nA
2, 3
+125, -55
-325
325
nA
1
+25
-75
75
nA
2, 3
+125, -55
-125
125
nA
1
+25
12
-
V
2, 3
+125, -55
12
-
V
1
+25
-
-12
V
2, 3
+125, -55
-
-12
V
VOUT = 0V and +10V
RL = 2kΩ
4
+25
100
-
kV/V
5, 6
+125, -55
100
-
kV/V
VOUT = 0V and −10V
RL = 2kΩ
4
+25
100
-
kV/V
5, 6
+125, -55
100
-
kV/V
1
+25
80
-
dB
2, 3
+125, -55
80
-
dB
1
+25
80
-
dB
2, 3
+125, -55
80
-
dB
∆VCM = +10V
V+ =+5V
V- = -25V
VOUT = -10V
∆VCM = -10V
V+ = +25V
V- = -5V
VOUT = +10V
FN3931.1
August 17, 2005
HA-5101/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: VS= ±15V, RS = 100Ω, RL = 500kΩ, VOUT = 0V, Unless Otherwise Specified
PARAMETER
SYMBOL
Output Voltage Swing
+VOUT1
-VOUT1
+VOUT2
-VOUT2
Output Current
+IOUT
-IOUT
Quiescent Power Supply Current
+ICC
-ICC
Power Supply Rejection Ratio
+PSRR
-PSRR
Offset Voltage Adjustment
+VIOAdj
TEST CONDITIONS
RL = 2kΩ
RL = 2kΩ
VS = ±18V
RL = 600Ω
VS = ±18V
RL = 600Ω
VOUT = -15V
VS = ±18V
VOUT = +15V
VS = ±18V
VOUT = 0V
IOUT = 0mA
VOUT = 0V
IOUT = 0mA
∆VS = 10V
V+ = +10V, V- = -15V
V+ = +20V, V- = -15V
∆VS = 10V
V+ = +15V, V- = -10V
V+ = +15V, V- = -20V
Note 4
RL = 2kΩ, CL = 50pF
AV = +1V/V
-VIOAdj
GROUP A
SUBGROUP TEMP (°C)
LIMITS
MIN
MAX
UNITS
1
+25
12
-
V
2, 3
+125, -55
12
-
V
1
+25
-
-12
V
2, 3
+125, -55
-
-12
V
1
+25
15
-
V
2, 3
+125, -55
15
-
V
1
+25
-
-15
V
2, 3
+125, -55
-
-15
V
1
+25
25
-
mA
2, 3
+125, -55
25
-
mA
1
+25
-
-25
mA
2, 3
+125, -55
-
-25
mA
1
+25
-
6
mA
2, 3
+125, -55
-
6
mA
1
+25
-6
-
mA
2, 3
+125, -55
-6
-
mA
1
+25
80
-
dB
2, 3
+125, -55
80
-
dB
1
+25
80
-
dB
2, 3
+125, -55
80
-
dB
1
+25
VIO-1
-
mV
2, 3
+125, -55
VIO-1
-
mV
1
+25
VIO+1
-
mV
2, 3
+125, -55
VIO+1
-
mV
MIN
MAX
UNITS
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VS= ±15V, RS = 50Ω, RL = 2kΩ, CL = 50pF, AVCL = +1V/V, Unless Otherwise Specified
PARAMETER
SYMBOL
Slew Rate
Rise and Fall Time
VOUT = -3V to +3V
4
+25
6
-
V/µs
-SR
VOUT = +3V to -3V
4
+25
6
-
V/µs
VOUT = 0V to +200mV
10% ≤ tR ≤ 90%
4
+25
-
200
ns
5, 6
+125, -55
-
400
ns
4
+25
-
200
ns
5, 6
+125, -55
-
400
ns
4
+25
-
35
%
5, 6
+125, -55
-
35
%
4
+25
-
35
%
5, 6
+125, -55
-
35
%
tF
+OS
-OS
3
LIMITS
+SR
tR
Overshoot
TEST CONDITIONS
GROUP A
SUBGROUP TEMP (°C)
VOUT = 0V to -200mV
10% ≤ tF ≤ 90%
VOUT = 0V to +200mV
VOUT = 0V to -200mV
FN3931.1
August 17, 2005
HA-5101/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VS= ±15V, RL = 2kΩ, CL = 50pF, AV = +1, Unless Otherwise Specified
LIMITS
PARAMETER
SYMBOL
Differential Input Resistance
RIN
Low Frequency Peak-to-Peak Noise
EnP-P
TEST CONDITIONS
NOTES
TEMP (°C)
MIN
MAX
UNITS
VCM = 0V
1
+25
250
-
kΩ
0.1Hz to 10Hz
1
+25
-
0.2
µVP-P
Input Noise Voltage Density
En
RS = 20Ω, fo = 1000Hz
1
+25
-
4.5
nV/√Hz
Input Noise Current Density
In
RS = 2MΩ, fo = 1000Hz
1
+25
-
3
pA/√Hz
Unity Gain Bandwidth
UGBW
VO = 100mV
1
+25
10
-
MHz
Full Power Bandwidth
FPBW
VPEAK = 10V
1, 2
+25
95
-
kHz
Minimum Closed Loop Stable Gain
CLSG
1
-55 to +125
+1
-
V/V
Output Resistance
ROUT
1
+25
-
150
Ω
1, 3
-55 to +125
-
180
mW
Quiescent Power Consumption
PC
Open Loop
VOUT = 0V, IOUT = 0mA
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πVPEAK).
3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.)
4. Offset adjustment range is [VIO (Measured) ±1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
SUBGROUPS (SEE TABLES 1 & 2)
Interim Electrical Parameters (Pre Burn-in)
1
Final Electrical Test Parameters
1*, 2, 3, 4, 5, 6
Group A Test Requirements
1, 2, 3, 4, 5, 6
Groups C & D Endpoints
1
*PDA applies to Subgroup 1 only.
4
FN3931.1
August 17, 2005
HA-5101/883
tR
tF
tR
5
tF
FN3931.1
August 17, 2005
HA-5101/883
Burn-in Circuits
CERAMIC MINI-DIP
1
8
2
7
V+
+
V-
D2
C2
3
6
4
5
C1
C3
D1
R1
CERAMIC LCC
NOTES:
R1 = 1MΩ, ±5%, 1/4W (Min)
C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row, (Min)
C3 = 0.01µF/Socket, 10%
D1 = D2 = 1N4002 or Equivalent/Board
(V+) - (V-) = 30V
6
FN3931.1
August 17, 2005
HA-5101/883
Schematic
-IN
D1
+IN
D2
V+
R25
R24
R23
R26
Q23
Q26
R28
R60
Q47
Q28
Q24
Q25
R35
R37
QL41
Q46
Q44
R22
Q1B
Q33
Q1A
Q13
Q32
Q10
Q27
Q9
R3A
3.65K
Q39
R11
R19B
R10
R12
R27
BAL
7
C1
Q6
Q4
Q3
Q12
R19A
R17A
Q17
Q5
Q11
8
Q42
Q31
Q19A
R15
OUTPUT
Q29
Q22
Q19B
R20
Q15
8
Q2A Q2B Q30
Q38
Q41
Q21
Q14
Q43
Q36
Q35
Q16
QL1
R34
Q45
R36
Q37
Q20
QL2
Q7
C2
R58
Q34
R4A
3.65K
R38
R4B
830
830
Q8
Q18
Q49 Q50
Q48
Q51
R18
V-
BAL
FN3931.1
August 17, 2005
HA-5101/883
Die Characteristics
DIE DIMENSIONS
70 X 70 X 19 mils ±1mil
1790 x 1780 x 483µm ±25.4µm
METALLIZATION
Type: AI, 1% Cu
Thickness: 16kÅ ±2kÅ
GLASSIVATION
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.)
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
WORST CASE CURRENT DENSITY:
1.38 x 105A/cm2
SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 54
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5101/883
BAL
-IN
NC
V+
+IN
OUT
V-
BAL
8
FN3931.1
August 17, 2005
HA-5101/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
LEAD FINISH
c1
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
(c)
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
b
ccc M
C A-B S
eA/2
-
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
5
E
0.220
0.310
5.59
7.87
5
c
aaa M C A - B S D S
D S
NOTES
0.014
eA
e
MAX
b
α
A A
b2
MIN
A
A
L
MILLIMETERS
MAX
M
(b)
D
BASE
PLANE
MIN
b1
SECTION A-A
D S
INCHES
SYMBOL
NOTES:
1. Index area: A notch or a pin one identification mark shall be
located adjacent to pin one and shall be located within the
shaded area shown. The manufacturer’s identification shall not
be used as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
8
8
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
9
FN3931.1
August 17, 2005
HA-5101/883
Ceramic Leadless Chip Carrier Packages (CLCC)
J20.A
MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES
D3
j x 45o
E3
B
E
h x 45o
0.010 S E F S
A
PLANE 2
PLANE 1
-E-
MIN
MAX
MIN
MAX
NOTES
A
0.060
0.100
1.52
2.54
6, 7
A1
0.050
0.088
1.27
2.23
-
B
-
-
-
-
-
B1
0.022
0.028
0.56
0.71
2, 4
B2
e
L
-H-
L3
0.022
0.15
0.56
-
0.342
0.358
8.69
9.09
-
D1
0.200 BSC
5.08 BSC
D2
0.100 BSC
2.54 BSC
D3
-
0.358
-
E
0.342
0.358
8.69
0.200 BSC
E2
0.100 BSC
E3
-
e
e1
0.358
0.050 BSC
-
0.015
0.040 REF
0.020 REF
-
9.09
2
9.09
-
5.08 BSC
-
2.54 BSC
-
2
9.09
1.27 BSC
-
0.38
2
1.02 REF
5
0.51 REF
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.91
2.41
-
L3
0.003
0.015
0.08
0.38
-
ND
5
5
NE
5
5
3
N
20
20
3
3
Rev. 0 5/18/94
-FB3
E1
E2
-
0.006
j
B1
1.83 REF
D
h
0.007 M E F S H S
0.072 REF
B3
E1
A1
MILLIMETERS
SYMBOL
L2
B2
L1
D2
e1
D1
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The
maximum “A” dimension is package height before being solder
dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
10
FN3931.1
August 17, 2005
HA-5101
®
D E S I GN I N FO R M ATI O N
Data Sheet
August 17, 2005
FN3931.1
The information contained on the following pages has been developed through characterization by Intersil Semiconductor and is
for use as application and design information only. No guarantee is implied.
Typical Performance Curves
Unless Otherwise Specified: VS = ±15V, TA = +25°C
7
6
5
VOLTAGE
4
3
2
CURRENT
1
0
10
100
1K
FREQUENCY (Hz)
10K
100K
OFFSET VOLTAGE (µV)
1500
INPUT NOISE CURRENT (pA/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
8
1000
500
0
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
FIGURE 1. NOISE SPECTRUM
FIGURE 2. OFFSET VOLTAGE vs TEMPERATURE
AV = 25,000, VS = ±15V (0.09nVP-P RTI)
AV = 25,000, VS = ±15V (12.89mVP-P RTO or 0.52µVP-P RTI)
PEAK-TO-PEAK NOISE 0.1Hz TO 10Hz
PEAK-TO-PEAK TOTAL NOISE 0.1Hz TO 1MHz
11
HA-5101
Typical Performance Curves
Unless Otherwise Specified: VS = ±15V, TA = +25°C (Continued)
250
INPUT OFFSET CURRENT (nA)
20
200
BIAS CURRENT (nA)
0
-20
-40
150
100
50
0
-55
-60
-55
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE
30
5
MAXIMUM
4
SUPPLY CURRENT (mA)
OFFSET CHANGE (µV)
20
10
0
-10
-20
-30
0
50
100
150
200
250
300
350
400
450
MINIMUM
3
2
1
0
500
TYPICAL
0
2
4
6
8
10
12
14
SUPPLY VOLTAGE (±V)
TIME (s)
1.1
D
0.9
0.9
0.8
0.8
0.7
0.7
OUTPUT CURRENT (mA)
1.0
SLEW RATE
50
RISE TIME (NORMALIZED)
SLEW RATE (NORMALIZED)
1.0
B
40
C
30
A
-20
0
20
40
60
80
100
120
0.6
TEMPERATURE (°C)
FIGURE 7. SLEW RATE/RISE TIME vs TEMPERATURE
12
VIN
VOUT
+15mV
-15mV
+15mV
-15mV
±15V
±15V
0V
0V
20
A
B
C
D
10
RL = 2K, CL = 50pF
-40
20
60
RISE TIME
0.6
-60
18
FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 5. INPUT OFFSET WARMUP DRIFT vs TIME
(NORMALIZED TO ZERO FINAL VALUE)
(SIX REPRESENTATIVE UNITS)
1.1
16
0
0
20
40
60
80
100
120
140
160
TIME (s)
FIGURE 8. SHORT CIRCUIT CURRENT vs TIME
FN3931.1
August 17, 2005
HA-5101
Typical Performance Curves
Unless Otherwise Specified: VS = ±15V, TA = +25°C (Continued)
OPEN LOOP VOLTAGE GAIN V/V(dB)
10M
(140)
VERROR
1M
(120)
1mV
100K
(100)
10K
(80)
2.65µs
5
10
15
18
SUPPLY VOLTAGE (±V)
TIME (1.5µs/DIV)
FIGURE 9. DC OPEN-LOOP VOLTAGE GAIN vs SUPPLY
VOLTAGE
FIGURE 10. SETTLING WAVEFORM
3
40
-55°C
GAIN
125°C
GAIN
-3
-6
-9
-12
125°C
PHASE
-55°C
PHASE
0
-45
-90
-135
AV = 1V/V
RL = 2K, CL = 50pF
10K
100K
20
1M
FREQUENCY (Hz)
10M
FIGURE 11. CLOSED LOOP GAIN AND PHASE AT HIGH AND
LOW TEMPERATURES
13
AV = 10
10
0
AV = 1
-10
-20
-180
-225
100M
AV = 100
30
GAIN (dB)
0
PHASE SHIFT (DEGREES)
CLOSED LOOP VOLTAGE GAIN (dB)
6
RL = 2K, CL = 50pF
10K
100K
1M
FREQUENCY (Hz)
10M
100M
FIGURE 12. CLOSED-LOOP VOLTAGE GAIN vs FREQUENCY
AT DIFFERENT CLOSED LOOP GAINS
FN3931.1
August 17, 2005
HA-5101
Typical Performance Curves
Unless Otherwise Specified: VS = ±15V, TA = +25°C (Continued)
-40
140
80
GAIN
60
40
0
20
45
90
0
PHASE
135
REJECTION RATIO (dB)
VOLTAGE GAIN (dB)
100
PHASE SHIFT (DEGREES)
120
-60
-PSRR/CMRR
-80
+PSRR
-100
180
10
100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 13. OPEN-LOOP GAIN/PHASE vs FREQUENCY
VIN = VOUT = ±3V, AV = +1, RL = 2kΩ, CL = 50pF
Timescale = 500ns/Div., Scale: Input = 5V/Div, Output = 2V/Div
FIGURE 15. SLEW RATE WAVEFORM
14
-120
100
1K
10K
FREQUENCY (Hz)
100K
1M
FIGURE 14. REJECTION RATIOS vs FREQUENCY
Rise Time and Overshoot
VIN = VOUT = 0V to +200mV, AV = +1, RL = 2K, CL = 50pF
Timescale = 20ns/Div.
FIGURE 16. SMALL SIGNAL WAVEFORM
FN3931.1
August 17, 2005
HA-5101
Applications Information
Offset Adjustment
The following is the recommended VIO adjust configuration:
Operation At ±5V Supply
+15V
The HA-5101 performs well at VS = ±5V exhibiting typical
characteristics as listed below:
ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBIAS. . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVOL (VO = ±3V) . . . . . . . . . . . . . . . . . .
VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMRR (∆VCM = ±2.5V) . . . . . . . . . . . . .
PSRR (∆VCC = 0.5V). . . . . . . . . . . . . . .
Unity Gain Bandwidth . . . . . . . . . . . . . .
Slew Rate. . . . . . . . . . . . . . . . . . . . . . . .
3.7mA
0.5mV
56nA
106kV/V
3.7V
13mA
90dB
90dB
10MHz
7V/µs
7
3
(NOTE)
+
2
4
(NOTE)
6
1
5
RP
RP = 100kΩ
-15V
NOTE: Proper decoupling is always recommended, 0.1µF high quality
capacitor should be at or very near the device’s supply pins.
Input Protection
The HA-5101 has built-in back-to-back protection diodes
which will limit the differential input voltage to approximately
7V. If the HA-5101 will be used in conditions where that voltage may be exceeded, then current limiting resistors must
be used. No more than 25mA should be allowed to flow in
the HA-5101’s input.
Comparator Circuit
V+
RLIM
∆VIN
Output Saturation
2
RLIM
3
When an op amp is overdriven, output devices can saturate
and sometimes take a long time to recover. Saturation can
be avoided (sometimes) by using circuits such as:
6
+
4
V-
Choose RLIM Such That:
V+
7
( ∆V IN MAX – 7V )
----------------------------------------------- ≤ 2R LIM
25mA
R1
R2
+
R3
IN
VSOURCE
R4
V-
If saturation cannot be avoided the HA-5101 recovers from a
25% overdrive in about 6.5µs (see photo).
OUT
Top: Input
Bottom: Output, 5V/Div., 2µs/Div.
Output is overdriven negative and recovers in 6µs.
15
FN3931.1
August 17, 2005
HA-5101
TABLE 1. TYPICAL PERFORMANCE CHARACTERISTICS
Device Characterized At: VS = ±15V, RL = 2kΩ, CL = 50pF, AVCL = +1V/V, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP (°C)
TYP
DESIGN LIMITS
UNITS
+25
0.8
Table 1
mV
Offset Voltage
VCM = 0V
Offset Voltage Average Drift
Versus Temperature
-55 to +125
3
7
µV/°C
Offset Current Average Drift
Versus Temperature
-55 to +125
100
250
pA/°C
Input Bias Current
VCM = 0V
+25
65
Table 1
nA
Input Offset Current
VCM = 0V
+25
35
Table 1
nA
Differential Input Resistance
VCM = 0V
+25
500
Table 3
kΩ
Input Noise Voltage Density
fo = 10Hz
+25
5.4
9
nV/√Hz
fo = 100Hz
+25
3.4
5.5
nV/√Hz
fo = 1kHz
+25
3.2
Table 3
nV/√Hz
fo = 10Hz
+25
6
20
pA/√Hz
fo = 100Hz
+25
1.5
5
pA/√Hz
fo = 1kHz
+25
0.52
Table 3
pA/√Hz
VOUT = ±10V
-55
400K
Table 1
V/V
+25
1M
Table 1
V/V
+125
1M
Table 1
V/V
Input Noise Current Density
Large Signal Voltage Gain
Slew Rate
VOUT = ±3V
-55 to +125
10
5.4
V/µs
Full Power Bandwidth
VPEAK = 10V, (Note 2)
-55 to +125
159
85
kHz
Rise and Fall Times
VOUT = ±200mV
-55 to +125
50
Table 2
ns
Overshoot
VOUT = ±200mV
-55 to +125
20
35
%
Settling Time
To 0.1% for 10V Step
+25
4.5
6
µs
To 0.01% for 10V Step
+25
6
10
µs
Output Short Circuit Current
t < 10s, VOUT = ±15V
+25
±35
±50
mA
Output Resistance
Open Loop
+25
110
Table 3
Ω
Supply Current
No Load
+25
4.3
Table 1
mA
Minimum Supply Voltage
Functional Operation Only,
Other Parameters Will Vary
+25
±4
±5
V
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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16
FN3931.1
August 17, 2005
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