DATASHEET

Quad SPST CMOS Analog Switch
HI-201/883
Features
The HI-201/883 is a monolithic device comprised of four
independently selectable SPST switchers which feature fast
switching speeds (185ns typical) combined with low power
dissipation (15mW typical at +25°C).
• This Circuit is Processed in Accordance to MIL-STD-883 and
is Fully Conformant Under the Provisions of Paragraph 1.2.1.
Each switch provides low “ON” resistance operation for input
signal voltages up to the supply rails and for signal currents up
to 25mA continuous. Rugged DI construction eliminates latchup and substrate SCR failure modes.
• Low “On” Release . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Ω Max
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• TTL/CMOS Compatible . . . . . . . . . . . . . . . . . . 2.4V (Logic “1”)
• Turn-On Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns
• Analog Current Range (Continuous) . . . . . . . . . . . . . . . 25mA
All devices provide break-before-make switching and are TTL
and CMOS compatible for maximum application versatility.
The HI-201/883 is an ideal component for use in high
frequency analog switching. Typical applications include signal
path switching, sample and hold circuits, digital filters, and
op amp gain switching networks.
• No Latch-Up
HI-201/883 is available in a 16 Ld CerDIP package.
• Sample and Hold Circuits
• Replaces DG201
Applications
• High Frequency Analog Switching
• Digital Filters
• Op Amp Gain Switching Networks
Pin Configuration
V+
VREF
INPUT
HI1-0201/883 (16 LD CERDIP)
TOP VIEW
SOURCE
LOGIC
INPUT
A1
1
16 A2
OUT1
2
15 OUT2
IN1
3
14 IN2
V-
4
13 V+
GND
5
12 VREF
IN4
6
11 IN3
OUT4
7
10 OUT3
A4
8
GATE
REFERENCE,
LEVEL SHIFTER,
AND DRIVER
SWITCH
CELL
GATE
DRAIN
OUTPUT
V-
FIGURE 1. FUNCTIONAL DIAGRAM
9 A3
Ordering Information
PART NUMBER
PART
MARKING
HI1-0201/883 HI1-201/883
April 9, 2012
FN7990.0
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
-55 to +125 16 Ld CerDIP F16.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HI-201/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
±VSUPPLY to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V
Analog Input Voltage, (+VS ). . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +2V
Analog Input Voltage, (-VS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -2V
Digital Input Voltage, (+VA) . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V
Digital Input Voltage, (-VA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V
Peak Current (S or D)
(Pulse at 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Continuous Current Any Terminal (Except S or D) . . . . . . . . . . . . . . . 25mA
Thermal Resistance
θJA (°C/W) θJC (°C/W)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . .
86
22
Package Power Dissipation at +75°C
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.88W
Package Power Dissipation Derating Factor above +75°C
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.76mW/°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . .≤275°C
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage Range (±VSUPPLY) . . . . . . . . . . . . . . . . . . . .±15V
Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V
Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.4V to +VSUPPLY
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified.
D.C. PARAMETERS
Switch “ON” Resistance
SYMBOL
rDS
CONDITIONS
VA = 0.8V, VS = 10V, ID = -1mA,
All Unused Channels VA = 2.4V
VA = 0.8V, VS = -10V, ID = 1mA,
All Unused Channels VA = 2.4V
Source “OFF”
Leakage Current
IS(OFF)
VS = +14V, VD = -14V, VA = 2.4V,
All Unused Channels VA = 2.4V,
VD = +14V, VS = -14V
VS = -14V, VD = +14V, VA = 2.4V,
All Unused Channels VA = 2.4V,
VD = -14V, VS = +14V
Drain “OFF”
Leakage Current
ID(OFF)
VD = -14V, VS = +14V, VA = 2.4V,
All Unused Channels VA = 2.4V,
VD = +14V, VS = -14V
VD = +14V, VS = -14V, VA = 2.4V,
All Unused Channels VA = 2.4V,
VD = -14V, VS = +14V
Channel “ON”
Leakage Current
ID(ON)
VD = VS = +14V, VA = 0.8V,
All Unused Channels VA = 0.8V,
VD = VS = -14V
VD = VS = -14V, VA = 0.8V,
All Unused Channels VA = 0.8V,
VD = VS = +14V
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
1
+25
-
70
Ω
2, 3
-55 to +125
-
100
Ω
1
+25
-
70
Ω
2, 3
-55 to +125
-
100
Ω
1
+25
-2
2
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-2
2
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-2
2
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-2
2
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-2
2
nA
2, 3
-55 to +125
-100
100
nA
1
+25
-2
2
nA
2, 3
-55 to +125
-200
200
nA
1
+25
-0.5
0.5
µA
2, 3
Low Level
Input Current
IAL
VAL = 0.8V
All Unused Channels VA = 2.4V
-55 to +125
-1.0
1.0
µA
High Level
Input Current
IAH
VAH = 2.4V
All Unused Channels VAH = 4.0V
1
+25
-0.5
0.5
µA
2, 3
-55 to +125
-1.0
1.0
µA
Supply Current
+ICC
All Channels VA = 0.8V
1, 2
+25, +125
-
1.5
mA
3
-55
-
2.0
mA
All Channels VA = 2.4V
1, 2
+25, +125
-
1.5
mA
3
-55
-
2.0
mA
2
FN7990.0
April 9, 2012
HI-201/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified.
D.C. PARAMETERS
SYMBOL
Supply Current
-ICC
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
1, 2
+25, +125
-1.5
-
mA
3
-55
-2.0
-
mA
1, 2
+25, +125
-1.5
-
mA
3
-55
-2.0
-
mA
All Channels VA = 0.8V
All Channels VA = 2.4V
TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified.
PARAMETERS
SYMBOL
Turn “ON” Time
tON
Turn “OFF” Time
tOFF
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
CL = 100pF,
RL = 1kΩ
9
+25
-
600
ns
10, 11
-55, +125
-
800
ns
CL = 100pF,
RL = 1kΩ
9
+25
-
500
ns
10, 11
-55, +125
-
650
ns
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1)
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VREF = OPEN, GND = 0V
PARAMETERS
SYMBOL
Address Capacitance
CA
NOTE
TEMPERATURE
(°C)
MIN
MAX
UNITS
f = 1MHz, VAL = 0V
1
+25
-
15
pF
CONDITIONS
Switches Input Capacitance
CS (OFF)
f = 1MHz, VAH = 5V,
Measured Source to GND
1
+25
-
15
pF
Switch Output Capacitance
CD (OFF)
f = 1MHz, VAH = 5V,
Measured Output to Ground
1
+25
-
20
pF
CD (ON)
f = 1MHz, VAL = 0V,
Measured Output to Ground
1
+25
-
30
pF
Drain to Source Capacitance
CDS
f = 1MHz, VAH = 5V
1
+25
-
2.0
pF
Off Isolation
VISO
f = 200kHz, VA = 2.4, RL = 1k,
VGEN = 1VP-P, CL = 10pF
1
+25
55
-
dB
Cross Talk
VCT
f = 200kHz, VA = 2.4, RL = 1k,
VGEN = 1VP-P, CL = 10pF
1
+25
60
-
dB
Charge Transfer Error
VCTE
f = 200kHz, VA = 0 to 4V,
CL = 0.01µF
1
+25
-10
10
mV
NOTE:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab
characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from
multiple production runs which reflect lot to lot and within lot variation.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-in)
Final Electrical Test Parameters
SUBGROUPS (Tables 1 and 2)
1
1 (Note 2), 2, 3, 9, 10, 11
Group A Test Requirements
1, 2, 3, 9, 10, 11
Groups C & D Endpoints
1
NOTE:
2. PDA applies to Subgroup 1 only.
3
FN7990.0
April 9, 2012
HI-201/883
Test Circuits
+VCC
+VCC
S
D
VS
D
S
VD
ID
VIN
IIN
VIN
-VCC
GND
GND
-VCC
FIGURE 3. ID (OFF)
FIGURE 2. INPUT LEAKAGE CURRENT
+VCC
+VCC
S
D
VS
IS
VD
D
ID(ON)
VIN
VIN
V
GND
-VCC
GND
-VCC
FIGURE 5. ID (ON)
FIGURE 4. IS (OFF)
+VCC
I1
STEP
GENERATOR
D
S
TEST
POINT
0.01µF
VIN
15V
IN1 V+ IN3
S1
S3
D1
D3
IN2
IN4
S2
GND
I2
TEST
POINT
0.01µF
D2
V-
STEP
GENERATOR
TEST
POINT
0.01µF
S4
D4
GND
TEST
POINT
0.01µF
-15V GND
-VCC
FIGURE 6. SUPPLY CURRENTS
4
FIGURE 7. CHARGE TRANSFER ERROR
FN7990.0
April 9, 2012
HI-201/883
Test Circuits
(Continued)
15V
+VCC
S
SINE WAVE
GENERATOR
2.4V
D
TEST
POINT
VIN
VD
GND
TEST
POINT
1kΩ
2.4V
1kΩ
-VCC
15V
TEST
POINT
1kΩ
S3
D1
D3
IN2
IN4
S2
D2
V-
S4
D4
GND
1kΩ
2.4V
1kΩ
TEST
POINT
TEST
POINT
FIGURE 9. OFF CHANNEL ISOLATION
2.4V
0.8V
TEST
POINT
S1
-15V GND
FIGURE 8. RDS
1kΩ
SINE WAVE
GENERATOR
IN1 V+ IN3
2.4V
0.8V
1kΩ
IN1 V+ IN3
S1
S3
D1
D3
IN2
IN4
S2
S4
D2
V-
2.4V
0.8V
TEST
POINT
2.4V
0.8V
1kΩ
TEST
POINT
D4
GND
-15V GND
STEP
GENERATOR
1kΩ
FIGURE 10. CROSSTALK BETWEEN CHANNELS
5
FN7990.0
April 9, 2012
HI-201/883
Switching Waveforms
+4V
FIGURE 11.
FIGURE 12.
6
FN7990.0
April 9, 2012
HI-201/883
Burn-In Circuit
FIGURE 13. HI-201/883 CERDIP
NOTE:
R1 = R2 = R3 = R4 = 10kΩ.
C1 = C2 = 0.01µF (per socket) or 0.1µF (per row).
D1 = D2 = IN4002 or equivalent/board.
|(V+) - (V-)| = 30V.
Schematic Diagrams
TTL/CMOS REFERENCE CIRCUIT VREF CELL
V+
R6
600
R2
5k
QP2
QP1
QP3
VREF
QN4
QP4
MP13
QP5
TO P2
QN1
R3
24.2k
D3
QN2
GND
MN14
R4
5.4k
MP14
QP6
MN15
V-
VLL
QN3
R5
7.9k
MN16
MN17
R7
100k
GND
7
FN7990.0
April 9, 2012
HI-201/883
Schematic Diagrams
(Continued)
SWITCH CELL
A’
QN11
V+
INPUT
QN12
QP11
OUTPUT
QN13
V-
QP12
A’
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
V+
QP3
QP1
QP5
QP4
A’
V+
QN1
D1
QP6
QP7
QN6
QN7
QP8
QP10
QP9
TO VLL
TO VREF
R1
200Ω
QN8
D2
QN9
QN10
QP2
A
VA’
QN2
QN4
QN5
QN3
V-
8
FN7990.0
April 9, 2012
HI-201/883
Typical Performance Curves
TA = +25°C, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V and VREF = Open
80
100
VIN = 0V
60
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
70
50
40
30
20
V+ = +10V
V- = -10V
V+ = +15V
V- = -15V
50
V+ = +12.5V
V- = -12.5V
10
0
-50
-25
0
25
50
75
100
0
-15
125
-10
TEMPERATURE (oC)
FIGURE 14. ON RESISTANCE vs TEMPERATURE
-5
0
5
ANALOG SIGNAL LEVEL (V)
10
15
FIGURE 15. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND POWER
SUPPLY VOLTAGE
100
90
80
SWITCH CURRENT (mA)
ID(ON)
1.0
70
60
50
40
30
20
10
0.1
25
50
75
0
100
125
TEMPERATURE (oC)
0
1
2
3
4
5
6
7
VOLTAGE ACROSS SWITCH (±V)
FIGURE 16. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 17A. SWITCH CURRENT vs VOLTAGE
140
120
OFF ISOLATION (dB)
CURRENT (nA)
IS(OFF) / ID(OFF)
10
100
80
RL = 1kΩ
60
40
20
0
100Hz
1kHz
10kHz
100kHz
1MHz
FREQUENCY (Hz)
FIGURE 18. OFF ISOLATION vs FREQUENCY
9
FN7990.0
April 9, 2012
HI-201/883
Die Characteristics
GLASSIVATION:
Type: Nitride over Silox
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1kÅ
DIE DIMENSIONS:
81 X 85 X 19 mils
METALLIZATION:
WORST CASE CURRENT DENSITY:
2 x 105A/cm2 at 25mA
Type: Aluminum
Thickness: 16kÅ ±2kÅ
Metallization Mask Layout
HI-201/883
OUT 1
2
IN 1
3
V-
4
GND
5
IN 4
6
OUT 4
7
10
A1
A2
1
16
8
9
A4
A3
15
OUT 2
14
IN 2
13
V+
12
VREF
11
IN 3
10
OUT 3
FN7990.0
April 9, 2012
HI-201/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
BASE
METAL
E
M
-Bbbb S
C A-B S
(c)
Q
-C-
SEATING
PLANE
S1
b2
b
C A-B S
eA/2
NOTES
-
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
c
aaa M C A - B S D S
D S
MAX
0.014
eA
e
MIN
b
α
A A
MILLIMETERS
MAX
A
A
L
MIN
M
(b)
SECTION A-A
D S
INCHES
SYMBOL
b1
D
BASE
PLANE
ccc M
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
16
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN7990.0
April 9, 2012
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