HM-6514/883 TM 1024 x 4 CMOS RAM March 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HM-6514/883 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. • Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max • Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max • Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min • TTL Compatible Input/Output • Common Data Input/Output On chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminates the need for pull up or pull down resistors. The HM-6514/883 is fully static RAM and may be maintained in any state for an indefinite period of time. • Three-State Output • Standard JEDEC Pinout • Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max • 18 Pin Package for High Density Data retention supply voltage and supply current are guaranteed over temperature. • Gated Inputs - No Pull Up or Pull Down Resistors Required • On-Chip Address Register Ordering Information 120ns HM1-6514S/883 200ns HM1-6514B/883 300ns TEMPERATURE RANGE -55oC to 125oC HM1-6514/883 PACKAGE CERDIP PKG. NO. F18.3 Pinout HM-6514/883 (CERDIP) TOP VIEW A6 1 18 VCC A5 2 17 A7 A4 3 16 A8 A3 4 15 A9 A0 5 14 DQ0 A1 6 13 DQ1 A2 7 12 DQ2 E 8 11 DQ3 GND 9 10 W PIN DESCRIPTION A Address Input E Chip Enable W Write Enable D Data Input Q Data Output CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 151 FN2996.1 HM-6514/883 Functional Diagram LSB A9 A8 A7 A6 A5 A4 A LATCHED ADDRESS REGISTER A 6 64 x 64 MATRIX 64 6 L G L LSB A2 A1 A0 A3 GATED ROW DECODER 16 16 16 16 A LATCHED ADDRESS REGISTER GATED COLUMN I/O SELECT 4 A 4 G 4 1 OF 4 E W DQ 152 HM-6514/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max TABLE 1. HM-6514/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER (NOTE 1) CONDITIONS SYMBOL GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS - 0.4 V Output Low Voltage VOL VCC = 4.5V IOL = 3.2mA 1, 2, 3 -55oC ≤ TA ≤ +125oC Output High Voltage VOH VCC = 4.5V IOH = -1.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC 2.4 - V VCC = 5.5V, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA VCC = 5.5 V, VIO = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA Input Leakage Current II Input/Output Leakage Current IIOZ Data Retention Supply Current ICCDR VCC = 2.0V, E = VCC -0.3V, IO = 0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 25 µA Operating Supply Current ICCOP VCC = 5.5V, (Note 2) E = 1MHz 1, 2, 3 -55oC ≤ TA ≤ +125oC - 7 mA Standby Supply Current ICCSB VCC = 5.5V, E = VCC-0.3V, IO = 0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 50 µA NOTES: 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 153 HM-6514/883 TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER SYMBOL (NOTES 1, 2) CONDITIONS GROUP A SUBGROUPS HM-6514S/883 TEMPERATURE HM-6514B/883 HM-6514/883 MIN MAX MIN MAX MIN MAX UNITS Chip Enable Access Time (1) TELQV VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 120 - 200 - 300 ns Address Access Time (2) TAVQV VCC = 4.5 and 5.5V, Note 3 9, 10, 11 -55oC ≤ TA ≤ +125oC - 120 - 220 - 320 ns Chip Enable Pulse Negative Width (5) TELEH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 120 - 200 - 300 - ns Chip Enable Pulse Positive Width (6) TEHEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 50 - 90 - 120 - ns Address Setup Time (7) TAVEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 20 - 20 - ns Address Hold Time (8) TELAX VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 40 - 50 - 50 - ns Write Enable Pulse Width (9) TWLWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 120 - 200 - 300 - ns Write Enable Pulse Setup Time (10) TWLEH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 120 - 200 - 300 - ns Write Enable Pulse Hold Time (11) TELWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 120 - 200 - 300 - ns Data Setup Time (12) TDVWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 50 - 120 - 200 - ns Data Hold Time (13) TWHDX VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - 0 - ns Write Data Delay Time (14) TWLDV VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 70 - 80 - 100 - ns Early Output High-Z Time (15) TWLEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - 0 - ns Late Output High-Z Time (16) TEHWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - 0 - ns Read or Write Cycle Time (17) TELEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 170 - 290 - 420 - ns NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. 154 HM-6514/883 TABLE 3. HM-6514/883 ELECTRICAL PERFORMANCE SPECIFICATIONS HM-6514/883 LIMITS PARAMETER SYMBOL CONDITIONS NOTE TEMPERATURE MIN MAX UNITS CI VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground 1 TA = +25oC - 8 pF CIO VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground 1 TA = +25oC - 10 pF Input Capacitance Input/Output Capacitance Chip Enable Output Disable Time TELQX VCC = 4.5 and 5.5V 1 -55oC ≤ TA ≤ +125oC 5 - Chip Enable Output Disable Time TEHQZ VCC = 4.5 and 5.5V HM-6514S/883 1 -55oC ≤ TA ≤ +125oC - 50 ns VCC = 4.5 and 5.5V HM-6514B/883 1 -55oC ≤ TA ≤ +125oC - 80 ns VCC = 4.5 and 5.5V HM-6514/883 1 -55oC ≤ TA ≤ +125oC - 100 ns VCC = 4.5V, IO = -100µA 1 -55oC ≤ TA ≤ +125oC VCC -0.4 - V High Level Output Voltage VOH2 NOTES: 1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 1, 7, 9 PDA 100%/5004 1 Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Groups C & D Samples/5005 1, 7, 9 155 HM-6514/883 Timing Waveforms (2) TAVQV (7) TAVEL (17) TELEL (8) TELAX A (7) TAVEL VALID ADD NEXT ADD (2) TAVQY (6) TEHEL (6) TEHEL (5) TELEH E (1) TELQV DQ (4) TEHQZ (3) TELQX HIGH Z HIGH Z VALID DATA OUT W TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 1. READ CYCLE TRUTH TABLE INPUTS TIME REFERENCE E W A DATA I/O DQ -1 H X X Z Memory Disabled H V Z Cycle Begins, Addresses are Latched 0 FUNCTION 1 L H X X Output Enabled 2 L H X V Output Valid H X V Read Accomplished X X Z Prepare for Next Cycle (Same as -1) H V Z Cycle Ends, Next Cycle Begins (Same as 0) 3 4 5 H The address information is latched in the on-chip registers on the falling edge of E (T = 0). Minimum address set up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1) the output becomes enabled but data is not valid until during time (T = 2). W must remain high throughout the read cycle. After the output data has been read, E may return high (T = 3). This will disable the output buffer and all inputs, and ready the RAM for the next memory cycle (T = 4). 156 HM-6514/883 Timing Waveforms (Continued) TELAX TAVEL A TEVEL VALID ADD NEXT ADD TELEL TEHEL TELEH TEHEL E TWLEH TELWL TWHEH TWLWH W TWLDV HIGH Z HIGH Z DQ VALID DATA INPUT TWHDZ TDVWH TELWH TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 2. WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE E W A DQ -1 H X X Z Memory Disabled X V Z Cycle Begins, Addresses are Latched L X Z Write Period Begins X V Data In is Written H X Z Write Completed X X Z Prepare for Next Cycle (Same as -1) X V Z Cycle Ends, Next Cycle Begins (Same as 0) 0 1 L 2 L 3 4 H 5 The write cycle is initiated by the falling edge of E (T = 0), which latches the address information in the on-chip registers. There are two basic types of write cycles, which differ in the control of the common data-in/data-out bus. Case 1: E falls before W falls The output buffers may become enabled (reading) if E falls before W falls. W is used to disable (three-state) the outputs so input data can be applied. TWLDV must be met to allow the W signal time to disable the outputs before applying input data. Also, at the end of the cycle the outputs may become active if W rises before E. The RAM outputs and all inputs will three-state after E rises (TEHQZ). In this type of write cycle TWLEL and TEHWH may be ignored. Case 2: E falls equal to or after W falls, and E rises before or equal to W rising FUNCTION This E and W control timing will guarantee that the data outputs will stay disabled throughout the cycle, thus simplifying the data input timing. TWLEL and TEHWH must be met, but TWLDV becomes meaningless and can be ignored. In this cycle TDVWH and TWHDX become TDVEH and TEHDX. In other words, reference data setup and hold times to the E rising edge. IF OBSERVE IGNORE Case 1 E falls before W TWLDV TWLEL Case 2 E falls after W and E rises before W TWLEL TEHWH TWLDV TWHDX If a series of consecutive write cycles are to be performed, W may be held low until all desired locations have been written (an extension of Case 2). 157 HM-6514/883 Test Load Circuit DUT (NOTE 1) CL + - IOH 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance. Burn-In Circuit HM6514/883 CERDIP VCC C1 F9 1 A6 VCC 18 F8 2 A5 A7 17 F10 F7 3 A4 A8 16 F11 F6 4 A3 A9 15 F12 F3 5 A0 DQ0 14 F4 6 A1 DQ1 13 F5 7 A2 DQ2 12 F0 8 E DQ3 11 9 GND W 10 NOTES: All resistors 47kΩ ±5%. F0 = 100kHz ±10%. F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F12 = F11 ÷ 2. VCC = 5.5V ±0.5V. VIH = 4.5V ±10%. VIL = -0.2V to +0.4V. C1 = 0.01µF Min. 158 F2 F1 HM-6514/883 Die Characteristics DIE DIMENSIONS: 136 x 167 x 19 ±1mils WORST CASE CURRENT DENSITY: 1.79 x 105 A/cm 2 METALLIZATION: Type: Si - Al Thickness: 11kÅ ±2kÅ LEAD TEMPERATURE (10s soldering): 300oC GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ Metallization Mask Layout HM-6514/883 A5 A6 VCC A7 A4 A8 A3 A9 A0 DQ0 DQ1 A1 DQ2 A2 E GND W DQ3 NOTE: 1. Pin numbers correspond to DIP Package only. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 159