82c284 883

82C284/883
®
Clock Generator and
Ready Interface for 80C286 Processors
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt Trigger
Input
- Improved Hysteresis
• Uses Crystal or External Signal for Frequency Source
- Dynamically Switchable Between Two Input
Frequencies
• Provides Local READY and MULTIBUS™ READY
Synchronization
• Static CMOS Technology
• Single +5V Power Supply
• Available in 18 Lead CERDIP Package
The Intersil 82C284/883 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with hysteresis.
Ordering Information
PART NUMBER
MD82C284-12/883
TEMP. RANGE
PACKAGE
-55oC to +125oC CERDIP
PKG. NO.
F18.3
Functional Diagram
Pinout
RESET
82C284/883
(CERDIP)
TOP VIEW
RESET
RES
SYNCHRONIZER
ARDY
1
18 VCC
SRDY
2
17 ARDYEN
SRDYEN
3
16 S1
READY
4
15 S0
EFI
EFI
5
14 NC
F/C
F/C
6
13 PCLK
X1
7
12 RESET
X2
8
11 RES
GND
9
10 CLK
X1
X2
XTAL
OSC
MUX
ARDYEN
ARDY
SRDYEN
SRDY
S1
S0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
CLK
SYNCHRONIZER
READY LOGIC
PCLK GENERATOR
READY
PCLK
FN2968.1
82C284/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied. . . . . GND -0.1V to VCC +1.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance
θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . .
80
20
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Gates
Storage Temperature Range . . . . . . . . . . . . . . . . .-65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
EFI Rise Time (From 0.8V to 3.2V). . . . . . . . . . . . . . . . . . 8ns (Max)
EFI Fall Time (From 3.2V to 0.8V) . . . . . . . . . . . . . . . . . . 8ns (Max)
TABLE 1. 82C284/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested.
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
Input LOW Voltage
VIL
VCC = 4.5V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
0.8
V
Input HIGH Voltage
VIH
VCC = 5.5V
1, 2, 3
-55oC ≤ TA ≤ +125oC
2.2
-
V
EFI, F/C Input High Voltage
VIHC
VCC = 5.5V
1, 2, 3
-55oC ≤ TA ≤ +125oC
3.2
-
V
RES HIGH Voltage
VIHR
VCC = 5.5V
1, 2, 3
-55oC ≤ TA ≤ +125oC
VCC -0.8
-
V
RES Input Hysteresis
VHYS
VCC = 5.5V
1, 2, 3
-55oC ≤ TA ≤ +125oC
0.5
-
V
RESET, PCLK Output LOW
Voltage
VOL
IOL = 5mA,
VCC = 4.5V, Note 2
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
0.4
V
RESET, PCLK Output
Voltage
VOH
IOH = -1mA,
VCC = 4.5V, Note 2
1, 2, 3
-55oC ≤ TA ≤ +125oC
VCC -0.4
-
V
READY Output LOW
Voltage
VOLR
IOH = 10mA,
VCC = 4.55V, Note 2
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
0.4
V
CLK Output LOW Voltage
VOLC
IOL = 5mA,
VCC = 4.5V, Note 2
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
0.4
V
CLK Output HIGH Voltage
VOHC
IOH = -5mA,
VCC = 4.5V, Note 2
1, 2, 3
-55oC ≤ TA ≤ +125oC
VCC -0.4
-
V
II
VIN = GND or VCC,
VCC = 5.5V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-10
10
µA
82C284-10/883, Note 1
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
48
mA
82C284-12/883, Note 1
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
60
mA
Input Leakage Current
Active Power Supply
Current
ICCOP
NOTES:
1. ICCOP measured at 10MHz for the 82C284-10/883 and at 12.5MHz for the 82C284-12/883. VIN = GND or VCC, VCC = 5.5V, outputs
unloaded.
2. Interchanging of force and sense conditions is permitted.
TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet waveforms, unless otherwise specified.
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
10MHz
12MHz
GROUP A
SUBGROUP
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
EFI LOW Time
t1
At VCC/2, Note 8
9, 10, 11
-55oC ≤ TA ≤ +125oC
20
-
16
-
ns
EFI HIGH Time
t2
At VCC/2, Note 8
9, 10, 11
-55oC ≤ TA ≤ +125oC
20
-
20
-
ns
2
82C284/883
TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet waveforms, unless otherwise specified. (Continued)
(NOTE 1)
CONDITIONS
10MHz
12MHz
GROUP A
SUBGROUP
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
PARAMETER
SYMBOL
Status Setup Time
for Status Going
Active
t5A
9, 10, 11
-55oC ≤ TA ≤ +125oC
20
-
18
-
ns
Status Setup Time
for Going Inactive
t5B
9, 10, 11
-55oC ≤ TA ≤ +125oC
20
-
16
-
ns
Status Hold Time
t6
9, 10, 11
-55oC ≤ TA ≤ +125oC
1
-
1
-
ns
9, 10, 11
-55oC ≤ TA ≤ +125oC
15
-
15
-
ns
9, 10, 11
-55oC ≤ TA ≤ +125oC
15
-
15
-
ns
15
-
15
-
ns
F/C Setup Time
F/C Hold Time
t7
t8
SRDY or SRDYEN
Setup Time
t9
9, 10, 11
-55oC ≤ TA ≤ +125oC
SRDY or SRDYEN
Hold Time
t10
9, 10, 11
-55oC ≤ TA ≤ +125oC
2
-
2
-
ns
ARDY or ARDYEN
Setup Time
t11
Note 3
9, 10, 11
-55oC ≤ TA ≤ +125oC
5
-
5
-
ns
ARDY or ARDYEN
Hold Time
t12
Note 3
9, 10, 11
-55oC ≤ TA ≤ +125oC
30
-
25
-
ns
RES Setup Time
t13
Notes 3, 7
9, 10, 11
-55oC ≤ TA ≤ +125oC
20
-
18
-
ns
9, 10, 11
≤ +125oC
10
-
8
-
ns
≤ +125oC
50
-
40
-
ns
≤ +125oC
12
-
11
-
ns
≤ +125oC
16
-
13
-
ns
≤ +125oC
5
-
5
-
ns
READY Inactive
Delay
t21
At 0.8V, Note 4,
Test Condition 2
9, 10, 11
-55oC ≤ TA
-55oC ≤ TA
-55oC ≤ TA
-55oC ≤ TA
-55oC ≤ TA
READY Active Delay
t22
At 0.8V, Note 4
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
24
-
18
ns
PCLK Delay
t23
CL = 75pF,
Test Condition 1
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
20
-
16
ns
RESET Delay
t24
CL = 75pF,
Test Condition 3
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
27
-
26
ns
PCLK LOW Time
t25
CL = 75pF, Note 5
9, 10, 11
-55oC ≤ TA ≤ +125oC
t1610
-
t1610
-
ns
PCLK HIGH Time
t26
CL = 75pF, Note 5
9, 10, 11
-55oC ≤ TA ≤ +125oC
t1610
-
t1610
-
ns
RES Hold Time
CLK Period
CLK LOW Period
CLK HIGH Time
t14
Notes 3, 7
t16
t17
t18
9, 10, 11
Notes 2, 6
Notes 2, 6
9, 10, 11
9, 10, 11
3
82C284/883
TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet waveforms, unless otherwise specified. (Continued)
PARAMETER
(NOTE 1)
CONDITIONS
SYMBOL
GROUP A
SUBGROUP
10MHz
TEMPERATURE
MIN
12MHz
MAX
MIN
MAX
UNITS
NOTES:
1. VCC = 4.5V and 5.5V unless otherwise specified. CLK loading: CL = 100pF.
2. With the internal crystal oscillator using recommended crystal and capacitive loading; or with the EFI input meeting specifications t1 and t2.
The recommended crystal loading for CLK frequencies of 8MHz to 20MHz are 25pF from pin X1 to GND, and 15pF from pin X2 to GND; for
CLK frequencies from 20MHz to 25MHz the recommended loading is 15pF from pin X1 to GND, and 15pF from X2 to GND. These recommended values are ±5pF and include all stray capacitance. Decouple VCC and GND as close to the 80C284/883 as possible.
3. This is an asychronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK edge.
4. The pull-up resistor value for the READY pin is 620Ω with the rated 150pF load.
5. t16 refers to any allowable CLK period.
6. When using a crystal with the recommended capacitive loading, CLK output HIGH and LOW times are guaranteed to meet 80C286 requirements.
7. Measured from 1.0V on the CLK to 0.8V on the RES waveform for RES active, and to 4.2V on the RES waveform for RES inactive.
8. Input test waveform characteristics: VIL= 0.0V, VIH = 4.5V.
TABLE 3. 82C284/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
10MHz
12MHz
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
Input Capacitance
CIN
FREQ = 1MHz, All
measurements are
referenced to device GND
1
TA = +25oC
-
10
-
10
pF
EFI HIGH to CLK
LOW Delay
t15A
1, 2
-55oC ≤ TA ≤ +125oC
-
30
-
25
ns
EFI LOW to CLK
HIGH Delay
t15B
1, 3
-55oC ≤ TA ≤ +125oC
-
35
-
30
ns
CLK Rise Time
t19
1.0V to 3.6V,
CL = 100pF
1
-55oC ≤ TA ≤ +125oC
-
8
-
8
ns
CLK Fall Time
t20
3.6V to 1.0V,
CL = 100pF
1
-55oC ≤ TA ≤ +125oC
-
8
-
8
ns
X1 HIGH to CLK
t27
1, 4
-55oC ≤ TA ≤ +125oC
-
35
-
30
ns
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes.
2. Measured from 3.2V on the EFI waveform to 1.0V on the CLK.
3. Measured from 0.8V on the EFI waveform to 3.6V on the CLK.
4. Measured from 3.6V on the X1 input to 3.6V on the CLK.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
4
82C284/883
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
PDA
100%
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
-
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Samples/5005
1, 7, 9
Group A
Groups C & D
A.C. Test Conditions
TEST CONDITION
RL
CL
1
750Ω
75pF
2
620Ω
150pF
3
∞
75pF
VCC
RL
DEVICE
OUTPUT
CL
A.C. Specifications
3.8V
3.2V
EFI INPUT
0.8V
0.4V
tDELAY (MAX)
VCC - 0.4V
3.6V
CLK
OUTPUT
1.0V
3.6V
1.0V
0.4V
tSETUP
tHOLD
3.8V
3.2V 3.2V
F/C
INPUT
0.8V
0.8V
0.4V
VCC - 0.4V
VCC - 0.8V
RES
INPUT
0.8V 0.8V
0.4V
2.6V
OTHER
DEVICE
INPUT
2.0V
0.8V
2.0V
0.8V
0.4V
tDELAY (MAX)
tDELAY (MIN)
2.0V
DEVICE
OUTPUT
0.8V
FIGURE 1. A.C. DRIVE, SETUP, HOLD AND DELAY TIME MEASUREMENT POINTS
5
82C284/883
Timing Waveforms
t2
t1
t16
EFI
t15B
t19
t18
CLK
t20
t17
t15A
FIGURE 2. CLK AS A FUNCTION OF EFI
NOTE: The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown.
t16
CLK
t14
(SEE
NOTE) t13
t13
t14
RES
t24
t24
RESET DEPENDS ON
STATE OF
PREVIOUS
RES
t22
t21
READY
NOTE:
This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
FIGURE 3. RESET AND READY TIMING AS A FUNCTION OF RES WITH S1, S0, ARDY + ARDYEN AND SRDY + SRDYEN HIGH
TS
φ1
φ2
TC
φ1
φ2
CLK
t6
t5B
t6
S1 • S0
t23
t23
t5A
PCLK
UNDEFINED
FIRST BUS
IF THIS IS
CYCLE
t26
t25
t9
t10
SRDY + SRDYEN
NOTE 1
t12
t11
t11
t12
ARDY + ARDYEN
t21
READY
t21
t22
NOTE 2
NOTES:
1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
2. If SRDY + SRDYEN or ARDY + ARDYEN are active before and/or during the first bus cycle after RESET, READY may not be deasserted
until the falling edge of φ2 of TS.
FIGURE 4. READY AND PCLK TIMING WITH RES HIGH
6
82C284/883
Timing Waveforms
(Continued)
φ1
φ2
φ1
φ2
φ1
φ2
CLK
PCLK
t7
t8
F/C
t27
X1
CLK
φ1
φ2
φ1
φ2
φ1
φ2
PCLK
F/C
t7
t8
t15B
EFI
FIGURE 5. CLK AS A FUNCTION OF F/C, PCLK, X1, AND EFI DURING DYNAMIC FREQUENCY SWITCHING
NOTE: This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
7
82C284/883
Burn-In Circuit
18 LEAD CERDIP
R1
F7
F5
F6
VCC/2
R1
R1
1
18
2
17
3
16
R1
VCC
F8
R1
R1
F9
R1
R1
4
15
5
14
F10
R1
F1
R1
NC
R1
F12
6
13
7
12
R1
VCC/2
R1
F0
R1
VCC/2
R1
VCC/2
8
11
GND
9
10
F11
R1
VCC/2
C1
VCC
NOTES:
1. Supply Voltage: VCC = 5.5V, ±0.5V, GND = 0V. Driver Voltage: VIH = 4.5V ± 10%, VIL = 0V
2. Input Voltage Limits: VIL (Max) = 0.4V, VIH (Min) = 2.6V
3. Component Values: R1 = 47kΩ, C1 = 0.1µF (Min)
4. Oven type and frequency requirements microtest, F0 through F12.
5. Approximate current per unit. ICC = 0.3mA.
6. Special requirements:
(a) Electrostatic Discharge Sensitive. Proper precautions must be used when handling units.
(b) All power supplies must be at zero volts when the boards are inserted into the ovens. After insertion, apply VCC first, then activate
the driver power supplies.
7. Oscilloscope measurements: To be on loaded boards before insertion into the oven.
8
Die Characteristics
DIE DIMENSIONS:
63 mils x 69 mils x 19 mils ± 1 mil
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 8kÅ
WORST CASE CURRENT DENSITY:
2 x 105 A/cm2
Metallization Mask Layout
82C284/883
SRDY
ARDY
VCC
ARDYEN
S1
SRDYEN
S0
READY
NC
EFI
PCLK
F/C
RESET
X1
X2
GND
CLK
RES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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