DATASHEET

80C88/883
®
Data Sheet
February 22, 2008
FN6589.0
CMOS 8-/16-Bit Microprocessor
Features
The Intersil 80C88/883 high performance 8-/16-bit CMOS
CPU is manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). Two modes of operation,
MINimum for small systems and MAXimum for larger
applications such as multiprocessing, allow user
configuration to achieve the highest performance level.
• This Circuit is Processed in Accordance to Mil-Std-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1
Full TTL compatibility (with the exception of CLOCK) and
industry-standard operation allow use of existing NMOS
8088 hardware and Intersil CMOS peripherals.
• 8-Bit Data Bus Interface; 16-Bit Internal Architecture
Complete software compatibility with the 80C86, 8086, and
8088 microprocessors allows use of existing software in new
designs.
• Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum
• Compatible with NMOS 8088
• Direct Software Compatibility with 80C86, 8086, 8088
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88/883)
• 1 Megabyte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
• Bus-Hold Circuitry Eliminates Pull-up Resistors
• Wide Operating Temperature Range
- M80C88/883 . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Ordering Information
PART NUMBER
MD80C88-2/883
PART MARKING
MD80C88-2/883
1
TEMPERATURE RANGE (°C)
-55 to +125
PACKAGE
40 LD CERDIP
PKG. DWG. #
F40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1989, Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
80C88/883
Pinouts
80C88/883
(40 LD CERDIP)
TOP VIEW
2
GND
1
MIN
MODE
40 VCC
MAX
MODE
A14
2
39 A15
A13
3
38 A16/S3
A12
4
37 A17/S4
A11
5
36 A18/S5
A10
6
35 A19/S6
A9
7
34 SS0
A8
8
33 MN/MX
AD7
9
32 RD
AD6
10
31 HOLD
(RQ/GT0)
AD5
11
30 HLDA
(RQ/GT1)
AD4
12
29 WR
(LOCK)
AD3
13
28 IO/M
(S2)
AD2
14
27 DT/R
(S1)
AD1
15
26 DEN
(S0)
AD0
16
25 ALE
(QS0)
NMI
17
24 INTA
(QS1)
INTR
18
23 TEST
CLK
19
22 READY
GND
20
21 RESET
(HIGH)
FN6589.0
February 22, 2008
80C88/883
Functional Diagram
EXECUTION UNIT
REGISTER FILE
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
DATA POINTER
AND
INDEX REGS
(8 WORDS)
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
SSO/HIGH
16-BIT ALU
4
A19/S6. . . A16/S3
8
AD7-AD0
8
A8-A15
3
INTA, RD, WR
4
DT/R, DEN, ALE, IO/M
FLAGS
BUS
INTERFACE
UNIT
4-BYTE
INSTRUCTION
QUEUE
TEST
INTR
NMI
LOCK
RQ/GT0, 1
CONTROL AND TIMING
2
HOLD
HLDA
CLK
2
QS0, QS1
3
S2, S1, S0
3
RESET READY MN/MX GND
VCC
MEMORY INTERFACE
C-BUS
B-BUS
INSTRUCTION
STREAM BYTE
QUEUE
ES
CS
BUS
INTERFACE
UNIT
SS
DS
IP
EXECUTION UNIT
CONTROL SYSTEM
A-BUS
AH
BH
AL
BL
CL
DL
CH
EXECUTION
UNIT
DH
ARITHMETIC/
LOGIC UNIT
SP
BP
SI
DI
3
FLAGS
FN6589.0
February 22, 2008
80C88/883
Pin Descriptions
The following pin function descriptions are for 80C88/883 systems in either minimum or maximum mode. The “local bus” in these descriptions is the
direct multiplexed bus interface connection to the 80C88/883 (without regard to additional bus buffers).
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
MAXIMUM OR MINIMUM MODE. THE “LOCAL BUS” IN THESE DESCRIPTIONS IS THE DIRECT MULTIPLEXEDBUS INTERFACE
CONNECTION TO THE 80C88/883 (WITHOUT REGARD TO ADDITIONAL BUS BUFFERS).
AD7-AD0
9-16
I/O
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data
(T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last valid level
during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”
A15, A14-A8
39, 2-8
O
ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4). These
lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high
impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or
“grant sequence”.
A19/S6,
A18/S5,
A17/S4,
A16/S3
35
36
37
38
O
O
O
O
ADDRESS/STATUS: During T1, these are the four most
significant address lines for memory operations. During I/O
operations, these lines are LOW. During memory and I/O
operations, status information is available on these lines during
T2, T3, TW and T4. S6 is always LOW. The status of the
interrupt enable flag bit (S5) is updated at the beginning of each
clock cycle. S4 and S3 are encoded as shown.
This information indicates which segment register is presently
being used for data accessing.
These lines are held at high impedance to the last valid logic
level during local bus “hold acknowledge” or “grant Sequence”.
S4
S3
CHARACTERISTICS
0
0
Alternate Data
0
1
Stack
1
0
Code or None
1
1
Data
RD
32
O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on
the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88/883 local
bus. RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH in T2 until
the 80C88/883 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.
READY
22
I
READY: is the acknowledgment from the address memory or I/O device that it will complete the data
transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from
READY. This signal is active HIGH. The 80C88/883 READY input is not synchronized. Correct operation
is not guaranteed if the set up and hold times are not met.
INTR
18
I
INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine
is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by
software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.
TEST
23
I
TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution continues,
otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle
on the leading edge of CLK.
NMI
17
I
NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutine is
vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally
by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction.
This input is internally synchronized.
RESET
21
I
RESET: cases the processor to immediately terminate its present activity. The signal must transition LOW
to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the
instruction set description, when RESET returns LOW. RESET is internally synchronized.
CLK
19
I
CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty
cycle to provide optimized internal timing.
VCC
40
GND
1, 20
MN/MX
33
VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for
decoupling.
GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor between
pins 1 and 20 is recommended for decoupling.
I
4
MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are
discussed in the following sections.
FN6589.0
February 22, 2008
80C88/883
Pin Descriptions
The following pin function descriptions are for 80C88/883 system in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique
to the minimum mode are described; all other pin functions are as described on page 4.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
MINIMUM MODE SYSTEM (i.e., MN/MX = VCC)
IO/M
28
O
STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O
access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle
(I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus “hold acknowledge”.
WR
29
O
Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depending on
the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active LOW, and is held
to high impedance logic one during local bus “hold acknowledge”.
INTA
24
O
INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and Tw of
each interrupt acknowledge cycle. Note that INTA is never floated.
ALE
25
O
ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82/82C83
address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note that ALE is never
floated.
DT/R
27
O
DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87 data
bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R is
equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH, R = LOW). This
signal is held to a high impedance logic one during local bus “hold acknowledge”.
DEN
26
O
DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which uses
the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles. For a read
or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from
the beginning of T2 until the middle of T4. DEN is held to high impedance logic one during local bus “hold
acknowledge”.
HOLD,
HLDA
31
30
I
O
HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD must be
active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an acknowledgment,
in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the
local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when
the processor needs to run another cycle, it will again drive the local bus and control lines.
Hold is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the set up time.
SS0
34
O
STATUS LINE: is logically equivalent to S0 in
the maximum mode. The combination of SS0,
IO/M and DT/R allows the system to completely
decode the current bus cycle status. SS0 is held
to high impedance logic one during local bus
“hold acknowledge”.
5
IO/M
DT/R
SS0
CHARACTERISTICS
1
0
0
Interrupt Acknowledge
1
0
1
Read I/O Port
1
1
0
Write I/O Port
1
1
1
Halt
0
0
0
Code Access
0
0
1
Read Memory
0
1
0
Write Memory
0
1
1
Passive
FN6589.0
February 22, 2008
80C88/883
Pin Descriptions
The following pin function descriptions are for 80C88/883 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique
to the maximum mode are described; all other pin functions are as described above.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
MAXIMUM MODE SYSTEM (i.e., MN/MX = GND)
S0
S1
S2
RQ/GT0,
RQ/GT1
26
27
28
31
30
O
O
O
I/O
STATUS: is active during clock high of T4, T1 and T2,
and is returned to the passive state (1, 1, 1) during T3 or
during Tw when READY is HIGH. This status is used by
the 82C88 bus controller to generate all memory and I/O
access control signals. Any change by S2, S1 or S0
during T4 is used to indicate the beginning of a bus
cycle, and the return to the passive state in T3 or Tw is
used to indicate the end of a bus cycle.
These signals are held at a high impedance logic one
state during “grant sequence”.
S2
S1
S0
CHARACTERISTICS
0
0
0
Interrupt Acknowledge
0
0
1
Read I/O Port
0
1
0
Write I/O Port
0
1
1
Halt
1
0
0
Code Access
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
Passive
REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local
bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 having higher
priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may be left unconnected.
The request/grant sequence is as follows (see RQ/GT Timing Sequence):
1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to the
80C88/883 (pulse 1).
2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88/883 to the requesting master
(pulse 2), indicates that the 80C88/883 has allowed the local bus to float and that it will enter the “grant
sequence” state at the next CLK. The CPUs bus interface unit is disconnected logically from the local
bus during “grant sequence”.
3. A pulse one CLK wide from the requesting master indicates to the 80C88/883 (pulse 3) that the “hold”
request is about to end and that the 80C88/883 can reclaim the local bus at the next CLK. The CPU
then enters T4 (or T1 if no bus cycles pending).
Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK
cycle after bus exchange. Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4
of the cycle when all the following conjugations are met:
1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply
with condition number 1 already satisfied.
LOCK
29
O
6
LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is
active (LOW). The LOCK signal is activated by the “LOCK” prefix instruction and remains active until the
completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one
state during “grant sequence”. In Max Mode, LOCK is automatically generated during T2 of the first INTA
cycle and removed during T2 of the second INTA cycle.
FN6589.0
February 22, 2008
80C88/883
Pin Descriptions
The following pin function descriptions are for 80C88/883 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique
to the maximum mode are described; all other pin functions are as described above. (Continued)
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
MAXIMUM MODE SYSTEM (i.e., MN/MX = GND)
QS1, QS0
24, 25
34
O
O
QUEUE STATUS: provide status to allow external
tracking of the internal 80C88/883 instruction queue.
The queue status is valid during the CLK cycle after
which the queue operation is performed. Note that the
queue status never goes to a high impedance statue
(floated).
QS1
QS0
0
0
No Operation
CHARACTERISTICS
0
1
First Byte of Opcode from
Queue
1
0
Empty the Queue
1
1
Subsequent Byte from
Queue
Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during a “grant
sequence”.
Functional Description
Static Operation
All 80C88/883 circuitry is static in design. Internal registers,
counters and latches are static and require not refresh as
with dynamic circuit design. This eliminates the minimum
operating frequency restriction placed on other
microprocessors. The CMOS 80C88/883 can operate from
DC to the specified upper frequency limit. The processor
clock may be stopped in either state (high/low) and held
there indefinitely. This type of operation is especially useful
for system debug or power critical applications.
The 80C88/883 can be single stepped using only the CPU
clock. This state can be maintained as long as is necessary.
Single step clock operation allows simple interface circuitry
to provide critical information for start-up.
Static design also allows very low frequency operation (as
low as DC). In a power critical situation, this can provide
extremely low power operation since 80C88/883 power
dissipation is directly related to operation frequency. As the
system frequency is reduced, so is the operating power until,
at a DC input frequency, the power requirement is the
80C88/883 standby current.
Internal Architecture
The internal functions of the 80C88/883 processor are
partitioned logically into two processing units. The first is the
Bus Interface Unit (BIU) and the second is the Execution
Unit (EU) as shown in the CPU block diagram.
this unit serves to increase processor performance through
improved bus bandwidth utilization. Up to 4-bytes of the
instruction stream can be queued while waiting for decoding
and execution.
The instruction stream queuing mechanism allows the BIU to
keep the memory utilized very efficiently. Whenever there is
space for at least 1-byte in the queue, the BIU will attempt a
byte fetch memory cycle. This greatly reduces “dead time”:
on the memory bus. The queue acts as a First-In-First-Out
(FIFO) buffer, from which the EU extracts instruction bytes
as required. If the queue is empty (following a branch
instruction, for example), the first byte into the queue
immediately becomes available to the EU.
The execution unit receives pre-fetched instructions from the
BIU queue and provides unrelocated operand addresses to
the BIU. Memory operands are passed through the BIU for
processing by the EU, which passes results to the BIU for
storage.
Memory Organization
The processor provides a 20-bit address to memory which
locates the byte being referenced. The memory is organized
as a linear array of up to 1 million bytes, addressed as
00000(H) to FFFFF(H). The memory is logically divided into
code, data, extra, and stack segments of up to 64-bytes
each, with each segment falling on 16-byte boundaries. (See
Figure 1).
These units can interact directly but for the most part
perform as separate asynchronous operational processors.
The bus interface unit provides the functions related to
instruction fetching and queuing, operand fetch and store,
and address relocation. This unit also provides the basic bus
control. The overlap of instruction pre-fetching provided by
7
FN6589.0
February 22, 2008
80C88/883
.
7
0
FFFFFH
64K-BIT
CODE SEGMENT
XXXXOH
STACK SEGMENT
+ OFFSET
SEGMENT
REGISTER FILE
CS
LSB
BYTE
WORD
SS
DATA SEGMENT
MSB
DS
ES
EXTRA SEGMENT
00000H
FIGURE 1. MEMORY ORGANIZATION
All memory references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of
programs. The segment register to be selected is
automatically chosen according to specific rules as shown in
Table 1. All information in one segment type share the same
logical attributes (e.g., code or data). By structuring memory
into relocatable areas of similar characteristics and by
automatically selecting segment registers, programs are
shorter, faster, and more structured.
TABLE 1.
MEMORY
REFERENCE
NEED
SEGMENT
REGISTER
USED
Instructions
CODE (CS)
Automatic with all instruction
prefetch.
Stack
STACK (SS)
All stack pushes and pops.
Memory references relative to
BP base register except data
references.
DATA (DS)
Data references when: relative
to stack, destination of string
operation, or explicitly
overridden.
EXTRA (ES)
Destination of string
operations: Explicitly selected
using a segment override.
Local Data
External Data
(Global)
SEGMENT
SELECTION RULE
Word (16-bit) operands can be located on even or odd
address boundaries. For address and data operands, the
least significant byte of the word is stored in the lower valued
address location and the most significant byte in the next
higher address location.
8
The BIU will automatically execute two fetch or write cycles
for 16-bit operands.
Certain locations in memory are reserved for specific CPU
operations. (See Figure 2). Locations from addresses
FFFF0H through FFFFFH are reserved for operations
including a jump to initial system initialization routine.
Following RESET, the CPU will always begin execution at
location FFFF0H where the jump must be located. Locations
00000H through 003FFH are reserved for interrupt
operations. Each of the 256 possible interrupt service
routines is accessed through its own pair of 16-bit pointers segment address pointer and offset address pointer. The
first pointer, used as the offset address, is loaded into the IP,
and the second pointer, which designates the base address,
is loaded into the CS. At this point program control is
transferred to the interrupt routine. The pointer elements are
assumed to have been stored at their respective places in
reserved memory prior to the occurrence of interrupts.
Minimum and Maximum Modes
The requirements for supporting minimum and maximum
80C88/883 systems are sufficiently different that they cannot
be done efficiently with 40 uniquely defined pins.
Consequently, the 80C88/883 is equipped with a strap pin
(MN/MX) which defines the system configuration. The
definition of a certain subset of the pins changes, dependent
on the condition of the strap pin. When the MN/MX pin is
strapped to GND, the 80C88/883 defines pins 24 through 31
and 34 in maximum mode. When the MN/MX pins is
strapped to VCC, the 80C88/883 generates bus control
signals itself on pins 24 through 31 and 34.
The minimum mode 80C88/883 can be used with either a
muliplexed or demultiplexed bus. This architecture provides
the 80C88/883 processing power in a highly integrated form.
The demultiplexed mode requires one latch (for 64k address
ability) or two latches (for a full megabyte of addressing). An
82C86 or 82C87 transceiver can also be used if data bus
buffering is required. (See Figure 3). The 80C88/883
provides DEN and DT/R to control the transceiver, and ALE
to latch the addresses. This configuration of the minimum
mode provides the standard demultiplexed bus structure
with heavy bus buffering and relaxed bus timing
requirements.
The maximum mode employs the 82C88 bus controller (See
Figure 4). The 82C88 decode status lines S0, S1 and S2,
and provides the system with all bus control signals. Moving
the bus control to the 82C88 provides better source and sink
current capability to the control lines, and frees the
80C88/883 pins for extended large system features.
Hardware lock, queue status, and two request/grant
interfaces are provided by the 80C88/883 in maximum
mode. These features allow coprocessors in local bus and
remote bus configurations.
FN6589.0
February 22, 2008
80C88/883
FFFFFH
FFFF0H
3FCH
TYPE 255 POINTER
(AVAILABLE)
084H
TYPE 33 POINTER
(AVAILABLE)
080H
TYPE 32 POINTER
(AVAILABLE)
07FH
TYPE 31 POINTER
(AVAILABLE)
014H
TYPE 5 POINTER
(RESERVED)
010H
TYPE 4 POINTER
OVERFLOW
00CH
TYPE 3 POINTER
1 BYTE INT INSTRUCTION
008H
TYPE 2 POINTER
NON MASKABLE
004H
TYPE 1 POINTER
SINGLE STEP
000H
TYPE 0 POINTER
DIVIDE ERROR
3FFH
AVAILABLE
INTERRUPT
POINTERS
(224)
RESERVED
INTERRUPT
POINTERS
(27)
DEDICATED
INTERRUPT
POINTERS
(5)
RESET BOOTSTRAP
PROGRAM JUMP
CS BASE ADDRESS
IP OFFSET
16-BITS
FIGURE 2. RESERVED MEMORY LOCATIONS
Bus Operation
The 80C88/883 address/data bus is broken into three parts:
the lower eight address/data bits (AD0-AD7), the middle
eight address bits (A8-A15), and the upper four address bits
(A16-A19). The address/data bits and the highest four
address bits are time multiplexed. This technique provides
the most efficient use of pins on the processor, permitting the
use of standard 40 Ld package. The middle eight address
bits are not multiplexed, i.e., they remain valid throughout
each bus cycle. In addition, the bus can be demultiplexed at
the processor with a single address latch if a standard, non
multiplexed bus is desired for the system.
Each processor bus cycle consists of at least four CLK
cycles. These are referred to as T1, T2, T3 and T4. (See
Figure 5). The address is emitted from the processor during
T1 and data transfer occurs on the bus during T3 and T4. T2
is used primarily for changing the direction of the bus during
read operations. In the event that a “Not Ready” indication is
given by the addressed device, “wait” states (TW) are
inserted between T3 and T4. Each inserted “wait” state is of
the same duration as a CLK cycle. Periods can occur
between 80C88/883 driven bus cycles. These are referred to
as “idle” states (TI), or inactive CLK cycles. The processor
uses these cycles for internal housekeeping.
9
During T1 of any bus cycle, the ALE (Address latch enable)
signal is emitted (by either the processor or the 82C88 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status
information for the cycle may be latched.
Status bits S0, S1, and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to Table 2.
Status bits S3 through S6 are multiplexed with high order
address bits and are therefore valid during T2 through T4.
S3 and S4 indicate which segment register was used to this
bus cycle in forming the address according to Table 3.
S5 is a reflection of the PSW interrupt enable bit. S6 is
always equal to 0.
FN6589.0
February 22, 2008
80C88/883
VCC
CLK
RES
RESET WR
RDY
GND
VCC
MN/MX
IO/M
READY RD
82C84A/85
80C88/883
CPU
INTA
CLOCK
GENERATOR
DT/R
DEN
GND
C1
VCC
20
STB
ALE
1
GND
AD0-AD7
A8-A19
GND
OE
ADDR/DATA
ADDRESS
82C82
LATCH
(1, 2 OR 3)
C2
40
C1 = C2 = 0.1µF
VCC
T
INTR
OE
82C86
TRANSCEIVER
DATA
EN
82C59A
INTERRUPT
CONTROL
INT
OE
HM-65162
CMOS PROM
HS-6616
CMOS PROM
CS
RDWR
82CXX
PERIPHERALS
IR0-7
FIGURE 3. DEMULTIPLEXED BUS CONFIGURATION
VCC
GND
MN/MX
S0
READY S1
82C84A/85
CLK
RES
RESET
RDY
CLK
MRDC
MWTC
82C88 AMWC
S1
IORC
S2
IOWC
DEN
DT/R
AIOWC
ALE
INTA
S0
S2
GND
NC
NC
80C88/883
CPU
STB
1
GND
VCC
C1
20
GND
AD0-AD7
A8-A19
GND
ADDR/DATA
OE
ADDRESS
82C82
LATCH
(1, 2 OR 3)
C2
40
C1 = C2 = 0.1µF
VCC
T
INT
OE
82C86
TRANSCEIVER
DATA
OE
82C59A
INTERRUPT
CONTROL
HM-65162
CMOS PROM
HS-6616
CMOS PROM
CS
RDWR
82CXX
PERIPHERALS
IR0-7
FIGURE 4. FULLY BUFFERED SYSTEM USING BUS CONTROLLER
10
FN6589.0
February 22, 2008
80C88/883
(4 + NWAIT) = TCY
T1
T2
T3
(4 + NWAIT) = TCY
TWAIT
T4
T1
T2
T3
TWAIT
T4
CLK
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
ALE
S2-S0
ADDR
STATUS
A19-A16
A19-A16
S6-S3
S6-S3
A15-A8
ADDR
ADDR DATA
BUS RESERVED
FOR DATA IN
A7-A0
A15-A8
D15-D0
VALID
A7-A0
DATA OUT (D7-D0)
RD, INTA
READY
READY
READY
WAIT
WAIT
DT/R
DEN
MEMORY ACCESS TIME
WP
FIGURE 5. BASIC SYSTEM TIMING
TABLE 2.
S2
S1
S0
0
0
0
0
0
0
TABLE 3.
S4
S3
Interrupt Acknowledge
0
0
Alternate Data (Extra Segment)
1
Read I/O
0
1
Stack
1
0
Write I/O
1
0
Code or None
0
1
1
Halt
1
1
Data
1
0
0
Instruction Fetch
1
0
1
Read Data from Memory
1
1
0
Write Data to Memory
1
1
1
Passive (No Bus Cycle)
CHARACTERISTICS
11
CHARACTERISTICS
I/O Addressing
In the 80C88/883, I/O operations can address up to a
maximum of 64k I/O registers. The I/O address appears in
the same format as the memory address on bus lines A15A0. The address lines A19-A16 are zero in I/O operations.
The variable I/O instructions, which use register DX as a
pointer, have full address capability, while the direct I/O
instructions directly address one or two of the 256 I/O byte
locations in page 0 of the I/O address space. I/O ports are
addressed in the same manner as memory locations.
FN6589.0
February 22, 2008
80C88/883
Designers familiar with the 8085 or upgrading an 8085
design should note that the 8085 addresses I/O with an 8-bit
address on both halves of the 16-bit address bus. The
80C88/883 uses a full 16-bit address on its lower 16 address
lines.
appropriate element to the new interrupt service program
location.
BOND
PAD
EXTERNAL
PIN
OUTPUT
DRIVER
External Interface
Processor Reset and Initialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 80C88/883 RESET
is required to be HIGH for greater than four clock cycles. The
80C88/883 will terminate operations on the high-going edge
of RESET and will remain dormant as long as RESET is
HIGH. The low-going transition of RESET triggers an
internal reset sequence for approximately 7 clock cycles.
After this interval the 80C88/883 operates normally,
beginning with the instruction in absolute location FFFFOH
(see Figure 2). The RESET input is internally synchronized
to the processor clock. At initialization, the HIGH to LOW
transition of RESET must occur no sooner than 50µs after
power up, to allow complete initialization of the 80C88/883.
NMI will not be recognized if asserted prior to the second
CLK cycle following the end of RESET.
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
FIGURE 6. BUS HOLD CIRCUITRY PINS 2-16 AND 35-39
BOND
PAD
OUTPUT
DRIVER
INPUT
BUFFER
VCC
EXTERNAL
PIN
P
INPUT
PROTECTION
CIRCUITRY
FIGURE 7. BUS HOLD CIRCUITRY PINS 26-32 AND 34
Non-Maskable Interrupt (NMI)
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate the need for pull-up/down
resistors, “bus-hold” circuitry has been used on 80C88/883
pins 2-16, 26-32 and 34-39 (see Figure 6A and 6B). These
circuits maintain a valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which
goes to a high impedance state).
To override the “bus hold” circuits, an external driver must be
capable of supplying 400µA minimum sink or source current
at valid input voltage levels. Since this “bus hold” circuitry is
active and not a “resistive” type element, the associated
power supply current is negligible. Power dissipation is
significantly reduced when compared to the use of passive
pull-up resistors.
Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in the
instruction set description. Hardware interrupts can be
classified as nonmusical or maskable.
Interrupts result in a transfer of control to a new program
location. A 256 element table containing address pointers to
the interrupt service program locations resides in absolute
locations 0 through 3FFH (see Figure 2), which are reserved
for this purpose. Each element in the table is 4-bytes in size
and corresponds to an interrupt “type”. An interrupting
device supplies an 8-bit type number, during the interrupt
acknowledge sequence, which is used to vector through the
12
The processor provides a single non-maskable interrupt
(NMI) pin which has higher priority than the maskable
interrupt request (INTR) pin. A typical use would be to
activate a power failure routine. The NMI is edge-triggered
on a LOW to High transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two clock cycles, but is not required to be
synchronized to the clock. An high going transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves (2-bytes in the case of
word moves) of a block type instruction. Worst case
response to NMI would be for multiply, divide, and variable
shift instructions. There is no specification on the occurrence
of the low-going edge; it may occur before, during, or after
the servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the NMI
procedure.
The signal must be free of logical spikes in general and be
free of bounces on the low-going edge to avoid triggering
extraneous responses.
Maskable Interrupt (INTR)
The 80C88/883 provides a singe interrupt request input
(INTR) which can be masked internally by software with the
resetting of the interrupt enable (IF) flag bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK.
FN6589.0
February 22, 2008
80C88/883
To be responded to, INTR must be present (HIGH) during
the clock period preceding the end of the current instruction
or the end of a whole move for a block type instruction. INTR
may be removed anytime after the falling edge of the first
INTA signal. During interrupt response sequence, further
interrupts are disabled. The enable bit is reset as part of the
response to any interrupt (INTR, NMI, software interrupt, or
single step). The FLAGS register, which is automatically
pushed onto the stack, reflects the state of the processor
prior to the interrupt. The enable bit will be zero until the old
FLAGS register is restored, unless specifically set by an
instruction.
During the response sequence (see Figure 7), the processor
executes two successive (back-to-back) interrupt
acknowledge cycles. The 80C88/883 emits to LOCK signal
(maximum mode only) from T2 of the first bus cycle until T2
of the second. A local bus “hold” request will not be honored
until the end of the second bus cycle. In the second bus
cycle, a byte is fetched from the external interrupt system
(e.g., 82C59A PIC) which identifies the source (type) of the
interrupt. This byte is multiplied by four and used as a
pointer into the interrupt vector lookup table.
An INTR signal left HIGH will be continually responded to
within the limitations of the enable bit and sample period.
INTR may be removed anytime after the falling edge of the
first INTA signal. The interrupt return instruction includes a
flags pop which returns the status of the original interrupt
enable bit when it restores the flags.
T1
T2
T3
T4
T1
T2
T3
T4
ALE
An interrupt request or RESET will force the 80C88/883 out
of the HALT state.
Read/Modify/Write (Semaphore) Operations Via
LOCK
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the
execution of an instruction. This allows the processor to
perform read/modify/write operations on memory (via the
“exchange register with memory” instruction), without
another system bus master receiving intervening memory
cycles. This is useful in multiprocessor system
configurations to accomplish “test and set lock” operations.
The LOCK signal is activated (LOW) in the clock cycle
following decoding of the LOCK prefix instruction. It is
deactivated at the end of the last bus cycle of the instruction
following the LOCK prefix. While LOCK is active, a request
on a RQ/GT pin will be recorded, and then honored at the
end of the LOCK.
External Synchronization Via TEST
As an alternative to interrupts, the 80C88/883 provides a
single software-testable input pin (TEST). This input is
utilized by executing a WAIT instruction. The single WAIT
instruction is repeatedly executed until the TEST input goes
active (LOW). The execution of WAIT does not consume bus
cycles once the queue is full.
If a local bus request occurs during WAIT execution, the
80C88/883 three-states all output drivers while inputs and
I/O pins are held at valid logic levels by internal bus-hold
circuits. If interrupts are enabled, the 80C88/883 will
recognize interrupts and process them when it regains
control of the bus.
Basic System Timing
LOCK
INTA
AD0AD7
TYPE
VECTOR
FIGURE 8. INTERRUPT ACKNOWLEDGE SEQUENCE
Halt
When a software HALT instruction is executed, the
processor indicates that it is entering the HALT state in one
of two ways, depending upon which mode is strapped. In
minimum mode, the processor issues ALE, delayed by one
clock cycle, to allow the system to latch the halt status. Halt
status is available on IO/M, DT/R, and SS0. In maximum
mode, the processor issues appropriate HALT status on S2,
S1 and S0, and the 82C88 bus controller issues one ALE.
The 80C88/883 will not leave the HALT state when a local
bus hold is entered while in HALT. In this case, the processor
reissues the HALT indicator at the end of the local bus hold.
13
In minimum mode, the MN/MX pin is strapped to VCC and
the processor emits bus control signals (RD, WR, IO/M, etc.)
directly. In maximum mode, the MN/MX pin is strapped to
GND and the processor emits coded status information
which the 82C88 bus controller uses to generate
MULTIBUS™ compatible bus control signals.
System Timing - Minimum System
The read cycle begins in T1 with the assertion of the address
latch enable (ALE) signal (see Figure 5). The trailing (low
going) edge of this signal is used to latch the address
information, which is valid on the address data bus
(ADO-AD7) at this time, into the 82C82/82C83 latch.
Address lines A8 through A15 do not need to be latched
because they remain valid throughout the bus cycle. From
T1 to T4 the IO/M signal indicates a memory or I/O
operation. At T2 the address is removed from the address
data bus and the bus is held at the last valid logic state by
internal bus-hold devices. The read control signal is also
asserted at T2. The read (RD) signal causes the addressed
device to enable its data bus drivers to the local bus. Some
FN6589.0
February 22, 2008
80C88/883
time later, valid data will be available on the bus and the
addressed device will drive the READY line HIGH. When the
processor returns the read signal to a HIGH level, the
addressed device will again three-state its bus drivers. If a
transceiver (82C86/82C87) is required to buffer the local
bus, signals DT/R and DEN are provided by the 80C88/883.
A write cycle also begins with the assertion of ALE and the
emission of the address. The IO/M signal is again asserted
to indicate a memory or I/O write operation. In T2,
immediately following the address emission, the processor
emits the data to be written into the addressed location. This
data remains valid until at least the middle of T4. During T2,
T3, and Tw, the processor asserts the write control signal.
The write (WR) signal becomes active at the beginning of
T2, as opposed to the read, which is delayed somewhat into
T2 to provide time for output drivers to become inactive.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge
(INTA) signal is asserted in place of the read (RD) signal and
the address bus is held at the last valid logic state by internal
bus-hold devices (see Figure 6). In the second of two
successive INTA cycles, a byte of information is read from
the data bus, as supplied by the interrupt system logic (i.e.,
82C59A priority interrupt controller). This byte identifies the
source (type) of the interrupt. It is multiplied by four and used
as a pointer into the interrupt vector lookup table, as
described earlier.
Bus Timing - Medium Complexity Systems
For medium complexity systems, the MN/MX pin is
connected to GND and the 82C88 bus controller is added to
the system, as well as an 82C82/82C83 latch for latching the
system address, and an 82C86/82C87 transceiver to allow
for bus loading greater than the 80C88/883 is capable of
handling (see Figure 8). Signals ALE, DEN, and DT/R are
generated by the 82C88 instead of the processor in this
configuration, although their timing remains relatively the
same. The 80C88/883 status outputs (S2, S1 and S0)
provide type of cycle information and become 82C88 inputs.
This bus cycle information specifies read (code, data or I/O),
write (data or I/O), interrupt acknowledge, or software halt.
The 82C88 thus issues control signals specifying memory
read or write, I/O read or write, or interrupt acknowledge.
The 82C88 provides two types of write strobes, normal and
advanced, to be applied as required. The normal write
strobes have data valid at the leading edge of write. The
advanced write strobes have the same timing as read
strobes, and hence, data is not valid at the leading edge of
write. The 82C86/82C87 transceiver receives the usual T
and OE inputs from the 82C88 DT/R and DEN outputs.
The pointer into the interrupt vector table, which is passed
during the second INTA cycle, can derive from an 82C59A
located on either the local bus or the system bus. If the
master 82C59A priority interrupt controller is positioned on
the local bus, the 82C86/82C87 transceiver must be
14
disabled when reading from the master 82C59A during the
interrupt acknowledge sequence and software “poll”.
The 80C88/883 Compared to the 80C86
The 80C88/883 CPU is a 8-bit processor designed around
the 8086 internal structure. Most internal functions of the
80C88/883 are identical to the equivalent 80C86 functions.
The 80C88/883 handles the external bus the same way the
80C86 does with the distinction of handling only 8-bits at a
time. Sixteen-bit operands are fetched or written in two
consecutive bus cycles. Both processors will appear
identical to the software engineer, with the exception of
execution time. The internal register structure is identical
and all instructions have the same end result. Internally,
there are three differences between the 80C88/883 and the
80C86. All changes are related to the 8-bit bus interface.
• The queue length is 4-bytes in the 80C88/883, whereas
the 80C86 queue contains 6-bytes, or three words. The
queue was shortened to prevent overuse of the bus by the
BIU when prefetching instructions. This was required
because of the additional time necessary to fetch
instructions 8-bits at a time.
• To further optimize the queue, the prefetching algorithm
was changed. The 80C88/883 BIU will fetch a new
instruction to load into the queue each time there is a
1-byte space available in the queue. The 80C86 waits until
a 2-byte space is available.
The internal execution time of the instruction set is affected
by the 8-bit interface. All 16-bit fetches and writes from/to
memory take an additional four clock cycles. The CPU is
also limited by the speed of instruction fetches. This latter
problem only occurs when a series of simple operations
occur. When the more sophisticated instructions of the
80C88/883 are being used, the queue has time to fill the
execution proceeds as fast as the execution unit will allow.
The 80C88/883 and 80C86 are completely software
compatible by virtue of their identical execution units.
Software that is system dependent may not be completely
transferable, but software that is not system dependent will
operate equally as well on an 80C88/883 or an 80C86.
The hardware interface of the 80C88/883 contains the major
differences between the two CPUs. The pin assignments are
nearly identical, however, with the following functional
changes:
• A8-A15: These pins are only address outputs on the
80C88/883. These address lines are latched internally and
remain valid throughout a bus cycle in a manner similar to
the 8085 upper address lines.
• BHE has no meaning on the 80C88/883 and has been
eliminated.
• SS0 provides the S0 status information in the minimum
mode. This output occurs on pin 34 in minimum mode
FN6589.0
February 22, 2008
80C88/883
only. DT/R, IO/M and SS0 provide the complete bus status
in minimum mode.
• IO/M has been inverted to be compatible with the 8085
bus structure.
• ALE is delayed by one clock cycle in the minimum mode
when entering HALT, to allow the status to be latched with
ALE.
T1
T2
T3
T4
CLK
QS1, QS0
80C88/883
S2, S1, S0
A19/S6 - A16/S3
A19 - A16
S6 - S3
ALE
RDY
80C88/883
82C84
READY 80C88/883
AD7 - AD0
80C88/883
A15 - A8
DATA OUT
A7-A0
DATA IN
A15 - A8
RD
DT/R
80C88/883
MRDC
DEN
FIGURE 9. MEDIUM COMPLEXITY SYSTEM TIMING
15
FN6589.0
February 22, 2008
80C88/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND - 0.5V to VCC + 0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
θJA (°C/W)
CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . -65°C to +150°C
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range
M80C88/883 . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications
SYMBOL
VCC = 5.0V, ±10%;TA = -55°C to +125°C (M80C88/883)
PARAMETER
VIH
Logical One Input Voltage
VIL
Logical Zero Input Voltage
TEST CONDITION
M80C88/883 (Note 4)
MIN
MAX
2.2
UNITS
V
-
0.8
V
VIHC
CLK Logical One Input Voltage
VCC - 0.8
-
V
VILC
CLK Logical Zero Input Voltage
-
0.8
V
VOH
Output High Voltage
lOH = -2.5mA
3.0
-
V
lOH = -100µA
VCC - 0.4
Output Low Voltage
lOL = +2.5mA
-
0.4
V
Input Leakage Current
VIN = 0V or VCC
Pins 17-19, 21-23 and 33
-1.0
1.0
µA
lBHH
Input Current-Bus Hold High
VIN = - 3.0V (Note 1)
-40
-400
µA
lBHL
Input Current-Bus Hold Low
VIN = - 0.8V (Note 2)
40
400
µA
Output Leakage Current
VOUT = 0V (Note 5)
-
-10.0
µA
ICCSB
Standby Power Supply Current
VCC = 5.5V (Note 3)
-
500
µA
ICCOP
Operating Power Supply Current
FREQ = Max, VIN = VCC or GND,
Outputs Open
-
10
mA/MHz
VOL
II
IO
V
NOTES:
1. lBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins 2-16, 26-32, 34-39.
2. IBHL should be measured after lowering VIN to GND and then raising to 0.8V on the following pins: 2-16, 35-39.
3. lCCSB tested during clock high time after HALT instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded.
4. MN/MX is a strap option and should be held to VCC or GND.
5. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32.
Capacitance TA = +25°C
SYMBOL
CIN
COUT
CI/O
PARAMETER
TEST CONDITIONS
TYPICAL
UNITS
Input Capacitance
FREQ = 1MHz. All measurements are referenced to device GND
25
pF
Output Capacitance
FREQ = 1MHz. All measurements are referenced to device GND
25
pF
I/O Capacitance
FREQ = 1MHz. All measurements are referenced to device GND
25
pF
16
FN6589.0
February 22, 2008
80C88/883
AC Electrical Specifications
VCC = 5.0V, ±10%;TA = -55°C to +125°C (M80C88/883)
SYMBOL
PARAMETER
TEST
CONDITIONS
80C88/883
MIN
MAX
UNITS
MINIMUM COMPLEXITY SYSTEM
TIMING REQUIREMENTS
(1)
TCLCL
CLK Cycle Period
125
-
ns
(2)
TCLCH
CLK Low Time
68
-
ns
(3)
TCHCL
CLK High Time
44
-
ns
(4)
TCH1CH2
CLK Rise Time
From 1.0V to 3.5V
-
10
ns
(5)
TCL2CL1
CLK FaIl Time
From 3.5V to 1.0V
-
10
ns
(6)
TDVCL
Data In Setup Time
20
-
ns
(7)
TCLDX1
Data In Hold Time
10
-
ns
(8)
TR1VCL
RDY Setup Time into 82C84A
(Notes 6, 7)
35
-
ns
(9)
TCLR1X
RDY Hold Time into 82C84A
(Notes 6, 7)
0
-
ns
(10)
TRYHCH
READY Setup Time into 80C88/883
68
-
ns
(11)
TCHRYX
READY Hold Time into 80C88/883
20
-
ns
(12)
TRYLCL
READY Inactive to CLK (Note 8)
-8
-
ns
(13)
THVCH
HOLD Setup Time
20
-
ns
(14)
TINVCH
lNTR, NMI, TEST Setup Time
(Note 7)
15
-
ns
(15)
TILIH
Input Rise Time (Except CLK)
From 0.8V to 2.0V
-
15
ns
(16)
TIHIL
Input FaIl Time (Except CLK)
From 2.0V to 0.8V
-
15
ns
TIMING RESPONSES
(17)
TCLAV
Address Valid Delay
CL = 100pF
10
60
ns
(18)
TCLAX
Address Hold Time
CL = 100pF
10
-
ns
(19)
TCLAZ
Address Float Delay
CL = 100pF
TCLAX
50
ns
(20)
TCHSZ
Status Float Delay
CL = 100pF
-
50
ns
(21)
TCHSV
Status Active Delay
CL = 100pF
10
60
ns
(22)
TLHLL
ALE Width
CL = 100pF
TCLCH - 10
-
ns
(23)
TCLLH
ALE Active Delay
CL = 100pF
-
50
ns
(24)
TCHLL
ALE Inactive Delay
CL = 100pF
-
55
ns
(25)
TLLAX
Address Hold Time to ALE Inactive
CL = 100pF
TCHCL - 10
-
ns
(26)
TCLDV
Data Valid Delay
CL = 100pF
10
60
ns
(27)
TCLDX2
Data Hold Time
CL = 100pF
10
-
ns
(28)
TWHDX
Data Hold Time After WR
CL = 100pF
TCLCL - 30
-
ns
(29)
TCVCTV
Control Active Delay 1
CL = 100pF
10
70
ns
(30)
TCHCTV
Control Active Delay 2
CL = 100pF
10
60
ns
(31)
TCVCTX
Control Inactive Delay
CL = 100pF
10
70
ns
(32)
TAZRL
Address Float to READ Active
CL = 100pF
0
-
ns
(33)
TCLRL
RD Active Delay
CL = 100pF
10
100
ns
(34)
TCLRH
RD Inactive Delay
CL = 100pF
10
80
ns
17
FN6589.0
February 22, 2008
80C88/883
AC Electrical Specifications
VCC = 5.0V, ±10%;TA = -55°C to +125°C (M80C88/883) (Continued)
SYMBOL
PARAMETER
TEST
CONDITIONS
80C88/883
MIN
MAX
UNITS
(35)
TRHAV
RD Inactive to Next Address Active
CL = 100pF
TCLCL - 40
-
ns
(36)
TCLHAV
HLDA Valid Delay
CL = 100pF
10
100
ns
(37)
TRLRH
RD Width
CL = 100pF
2TCLCL - 50
-
ns
(38)
TWLWH
WR Width
CL = 100pF
2TCLCL - 40
-
ns
(39)
TAVAL
Address Valid to ALE Low
CL = 100pF
TCLCH - 40
-
ns
(40)
TOLOH
Output Rise Time
From 0.8V to 2.0V
-
15
ns
(41)
TOHOL
Output Fall Time
From 2.0V to 0.8V
-
15
ns
NOTES:
6. Signal at 82C84A shown for reference only.
7. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
8. Applies only to T2 state (8ns into T3).
18
FN6589.0
February 22, 2008
80C88/883
Waveforms
T1
T2
T3
TW
(5)
TCL2CL1
(1)
TCLCL
T4
TCH1CH2
(4)
CLK (82C84A OUTPUT)
(3)
(2)
TCLCH
TCHCL
(30) TCHCTV
TCHCTV
(30)
IO/M, SSO
(17)
TCLAV
A15-A8
A15-A8 (FLOAT DURING INTA)
(17)
TCLAV
(17)
TCLAV
(26) TCLDV
(18) TCLAX
S6-S3
A19-A16
A19/S6-A16/S3
TLHLL
(22)
(23) TCLLH
TLLAX
(25)
ALE
(24)
TR1VCL (8)
TCHLL
RDY (82C84A INPUT)
SEE NOTES 9, 10
TAVAL
(39)
VIH
VIL
TCLR1X (9)
(12)
TRYLCL
(11)
TCHRYX
READY (80C88/883 INPUT)
(19)
TCLAZ
(10)
TRYHCH
(16)
TDVCL
AD7-AD0
AD7-AD0
(32) TAZRL
(7)
TCLDX1
DATA IN
(34) TCLRH
TRHAV
(35)
RD
(30)
TCHCTV
READ CYCLE
(WR, INTA = VOH)
TCLRL
(33)
TRLRH
(37)
(30)
TCHCTV
DT/R
(29) TCVCTV
TCVCTX
(31)
DEN
FIGURE 10. BUS TIMING - MINIMUM MODE SYSTEM
NOTES:
9. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
10. Signals at 82C84A are shown for reference only.
19
FN6589.0
February 22, 2008
80C88/883
Waveforms
(Continued)
T1
T2
T3
(5)
TCH1CH2
TCL2CL1
TW
CLK (82C84A OUTPUT)
(26)
TCLDV
TCLAX
(17)
TCLAV
TCVCTV
(27)
TCLDX2
(18)
AD7-AD0
AD7-AD0
WRITE CYCLE
DATA OUT
TWHDX
(29)
(28)
(31) TCVCTX
DEN
(29) TCVCTV
(38)
TWLWH
WR
TCVCTX
TDVCL
(19)
TCLAZ
(31)
(6)
TCLDX1 (7)
POINTER
AD7-AD0
TCHCTV (30)
TCHCTV
(30)
INTA CYCLE
(NOTE 11)
RD, WR = VOH
T4
TW
(4)
DT/R
(29) TCVCTV
INTA
TCVCTX
(31)
(29) TCVCTV
DEN
SOFTWARE
HALT DEN, RD,
WR, INTA = VOH
INVALID ADDRESS
AD7-AD0
TCLAV
(17)
SOFTWARE HALT
TCHLL
(24)
ALE
TCHCTV
(30)
TCLLH
(23)
TCVCTX
(31)
IO/M
DT/R
SSO
FIGURE 11. BUS TIMING - MINIMUM MODE SYSTEM (Continued)
NOTES:
11. Two INTA cycles run back-to-back. The 80C88/883 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the
second INTA cycle.
12. Signals at 82C84A are shown for reference only.
20
FN6589.0
February 22, 2008
80C88/883
AC Electrical Specifications
VCC = 5.0V ±10%;TA = -55°C to +125°C (M80C88/883)
80C88/883
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS
(1)
TCLCL
CLK Cycle Period
125
-
ns
(2)
TCLCH
CLK Low Time
68
-
ns
(3)
TCHCL
CLK High Time
44
-
ns
(4)
TCH1CH2
CLK Rise Time
From 1.0V to 3.5V
-
10
ns
(5)
TCL2CL1
CLK Fall Time
From 3.5V to 1.0V
-
10
ns
(6)
TDVCL
Data in Setup Time
20
-
ns
(7)
TCLDX1
Data In Hold Time
10
-
ns
(8)
TR1VCL
RDY Setup Time into 82C84
(Notes 13, 14)
35
-
ns
(9)
TCLR1X
RDY Hold Time into 82C84
(Notes 13, 14)
0
-
ns
(10)
TRYHCH
READY Setup Time into 80C88/883
68
-
ns
(11)
TCHRYX
READY Hold Time into 80C88/883
20
-
ns
(12)
TRYLCL
READY Inactive to CLK (Note 15)
-8
-
ns
(13)
TlNVCH
Setup Time for Recognition
(lNTR, NMl, TEST) (Note 14)
15
-
ns
(14)
TGVCH
RQ/GT Setup Time
15
-
ns
(15)
TCHGX
RQ Hold Time into 80C88/883 (Note 16)
30
TCHCL + 10
ns
(16)
TILlH
Input Rise Time (Except CLK)
From 0.8V to 2.0V
-
15
ns
(17)
TIHIL
Input Fall Time (Except CLK)
From 2.0V to 0.8V
-
15
ns
CL = 100pF
for all 80C88/883 outputs in
addition to internal loads.
5
35
ns
5
35
ns
-
65
ns
TIMING RESPONSES
(18)
TCLML
Command Active Delay (Note 13)
(19)
TCLMH
Command Inactive (Note 13)
(20)
TRYHSH
(21)
TCHSV
Status Active Delay
10
60
ns
(22)
TCLSH
Status Inactive Delay (Note 17)
10
70
ns
(23)
TCLAV
Address Valid Delay
10
60
ns
(24)
TCLAX
Address Hold Time
10
-
ns
(25)
TCLAZ
Address Float Delay
TCLAX
50
ns
(26)
TCHSZ
Status Float Delay
-
50
ns
(27)
TSVLH
Status Valid to ALE High (Note 13)
-
20
ns
(28)
TSVMCH
Status Valid to MCE High (Note 13)
-
30
ns
(29)
TCLLH
CLK Low to ALE Valid (Note 13)
-
20
ns
(30)
TCLMCH
CLK Low to MCE High (Note 13)
-
25
ns
(31)
TCHLL
ALE Inactive Delay (Note 13)
4
18
ns
READY Active to Status Passive (Notes 15, 17)
21
FN6589.0
February 22, 2008
80C88/883
AC Electrical Specifications
VCC = 5.0V ±10%;TA = -55°C to +125°C (M80C88/883) (Continued)
80C88/883
SYMBOL
PARAMETER
MCE Inactive Delay (Note 13)
TEST CONDITIONS
MIN
MAX
UNITS
CL = 100pF
for all 80C88/883 outputs in
addition to internal loads.
-
15
ns
10
60
ns
(32)
TCLMCL
(33)
TCLDV
Data Valid Delay
(34)
TCLDX2
Data Hold Time
10
-
ns
(35)
TCVNV
Control Active Delay (Note 13)
5
45
ns
(36)
TCVNX
Control Inactive Delay (Note 13)
10
45
ns
(37)
TAZRL
Address Float to Read Active
0
-
ns
(38)
TCLRL
RD Active Delay
10
100
ns
(39)
TCLRH
RD Inactive Delay
10
80
ns
(40)
TRHAV
RD Inactive to Next Address Active
TCLCL
- 40
-
ns
(41)
TCHDTL
Direction Control Active Delay
(Note 13)
-
50
ns
(42)
TCHDTH
Direction Control Inactive Delay
(Note 13)
-
30
ns
(43)
TCLGL
GT Active Delay
0
50
ns
(44)
TCLGH
GT Inactive Delay
0
50
ns
(45)
TRLRH
RD Width
2TCLCL 50
-
ns
(46)
TOLOH
Output Rise Time
From 0.8V to 2.0V
-
15
ns
(47)
TOHOL
Output Fall Time
From 2.0V to 0.8V
-
15
ns
NOTES:
13. Signal at 82C84A or 82C88 shown for reference only.
14. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
15. Applies only to T2 state (8ns into T3).
16. The 80C88/883 actively pulls the RQ/GT pin to a logic one on the following clock low time.
17. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
22
FN6589.0
February 22, 2008
80C88/883
Waveforms
T1
T2
(4)
TCH1CH2
(1)
TCLCL
T3
T4
(5)
TCL2CL1
TW
CLK
(23)
TCLAV
TCLCH
(2)
TCHCL (3)
QS0, QS1
(21) TCHSV
TCLSH
(22)
S2, S1, S0 (EXCEPT HALT)
(SEE NOTE 20)
A15-A8
A15-A8
(33)
(24)
TCLDV
TCLAX
(23) TCLAV
A19/S6-A16/S3
TCLAV
A19-A16
TSVLH
(27)
(23)
S6-S3
TCHLL (31)
TCLLH
(29)
ALE (82C88 OUTPUT)
NOTES 18, 19
(8)
TR1VCL
RDY (82C84 INPUT)
TCLR1X
(9)
(12) TRYLCL
READY 80C86 INPUT)
(11)
TCHRYX
TRYHSH
(20)
(24)
TCLAX
(10)
TRYHCH
READ CYCLE
TCLAV
(25)
TCLAZ
(23)
(6)
TDVCL
AD7-AD0
AD7-AD0
(7)
TCLDX1
DATA IN
(37) TAZRL
(39) TCLRH
TRHAV
RD
(42)
TCHDTH
(41) TCHDTL
TCLRL
(38)
DT/R
TCLML
82C88
OUTPUTS
SEE NOTES 19, 21
(18)
(40)
TRLRH
(45)
TCLMH
(19)
TCVNX
(36)
MRDC OR IORC
(35) TCVNV
DEN
FIGURE 12. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
18. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
19. Signals at 82C84A or 82C88 are shown for reference only.
20. Status inactive in state just prior to T4.
21. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high
82C88 CEN.
23
FN6589.0
February 22, 2008
80C88/883
Waveforms
(Continued)
T1
T2
T3
T4
TW
CLK
TCHSV (21)
(SEE NOTE 24)
S2, S1, S0 (EXCEPT HALT)
WRITE CYCLE
TCLDV
TCLAX
TCLAV (23)
(33)
(24)
TCLSH
(22)
AD7-AD0
TCLDX2
DATA
TCVNV
(35)
TCVNX (36)
DEN
82C88
OUTPUTS
SEE NOTES 22, 23
(34)
TCLMH
(19)
(18) TCLML
AMWC OR AIOWC
TCLMH (19)
(18)TCLML
MWTC OR IOWC
INTA CYCLE
A15-A8
(SEE NOTES 25, 26)
RESERVED FOR
CASCADE ADDR
(25) TCLAZ
(6)
AD7-AD0
TDVCL
TCLDX1 (7)
POINTER
TCLMCL
(32)
(28) TSVMCH
(41)
TCHDTL
MCE/PDEN
(30) TCLMCH
DT/R
82C88 OUTPUTS
SEE NOTES 22, 23, 25
(42)
TCHDTH
(18) TCLML
INTA
TCVNV
(35)
(19) TCLMH
DEN
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
AD7-AD0
A15-A8
TCVNX
(36)
INVALID ADDRESS
TCLAV
(23)
S2, S1, S0
TCHSV
(21)
TCLSH
(22)
FIGURE 13. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)
NOTES:
22. Signals at 82C84A or 82C86 are shown for reference only.
23. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high
82C88 CEN.
24. Status inactive in state just prior to T4.
25. Cascade address is valid between first and second INTA cycles.
26. Two INTA cycles run back-to-back. The 80C88/883 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is
shown for second INTA cycle.
24
FN6589.0
February 22, 2008
80C88/883
Waveforms
(Continued)
> 0-CLK
CYCLES
ANY
CLK
CYCLE
CLK
TCLGH
(44)
TGVCH (14)
(1)
TCLCL
TCHGX (15)
RQ/GT
PULSE 1
COPROCESSOR
RQ
PREVIOUS GRANT
AD7-AD0
TCLGL
(43) PULSE 2
80C88/883 GT
TCLGH (44)
PULSE 3
COPROCESSOR
RELEASE
TCLAZ (25)
80C88/883
COPROCESSOR
TCHSV (21)
(SEE NOTE)
TCHSZ (26)
RD, LOCK
A19/S6-A16/S3
S2, S1, S0
NOTE:
FIGURE 14. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
The coprocessor may not drive the busses outside the region shown without risking contention.
≥ 1CL
CYCLE
1 OR 2
CYCLES
CLK
THVCH (13)
THVCH (13)
(SEE NOTE)
HOLD
TCLHAV (36)
TCLHAV (36)
HLDA
TCLAZ (19)
A15-A8
80C88/883
80C88/883
COPROCESSOR
AD7-AD0
TCHSZ (20)
TCHSV (21)
A19/S6-A16/S3
RD, WR, I/O/M, DT/R, DEN, SSO
NOTE:
FIGURE 15. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
CLK
ANY CLK CYCLE
(13)
TINVCH (SEE NOTE)
NMI
INTR
ANY CLK CYCLE
CLK
TCLAV
(23)
TCLAV
(23)
SIGNAL
LOCK
TEST
FIGURE 16. ASYNCHRONOUS SIGNAL RECOGNITION
NOTE: Setup requirements for asynchronous signals only to
guarantee recognition at next CLK.
25
FIGURE 17. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
FN6589.0
February 22, 2008
80C88/883
Waveforms
(Continued)
≥ 50µs
VCC
CLK
(7) TCLDX1
(6) TDVCL
RESET
≥ 4 CLK CYCLE
FIGURE 18. RESET TIMING
AC Test Circuit
AC Testing Input, Output Waveform
INPUT
VIH + 20% VIH
TEST
POINT
OUTPUT FROM
DEVICE UNDER TEST
CL (NOTE)
OUTPUT
1.5V
1.5V
VOH
VOL
VIL - 50% VIL
AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch
between 0.4V and VCC -0.4V. Input rise and fall times are
driven at 1ns/V.
NOTE: Includes stay and jig capacitance.
Burn-In Circuits
MD80C88/883 (CERDIP)
C
1 GND
VCC 40
2 A14
A15 39
3 A13
A16 38
4 A12
A17 37
5 A11
A18 36
6 A10
A19 35
7 A9
BHE 34
8 A8
MX 33
9 AD7
RD 32
10 AD6
RQ0 31
11 AD5
RQ1 30
12 AD4
LOCK 29
OPEN
13 AD3
S2 28
OPEN
14 AD2
S1 27
OPEN
15 AD1
S0 26
RO
OPEN
16 AD0
QS0 25
RO
GND
17 NMI
QS2 24
GND
18 INTR
TEST 23
19 CLK
READY 22
RI
20 GND
RESET 21
RI
GND
GND
VCL
GND
GND
VCL
GND
GND
GND
VCL
VCL
VCL
F0
GND
26
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RC
RIO
RO
RO
RO
RO
RO
GND
VCC
VCL
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
GND
RO
RI
VIL
VCL
RO
RO
RO
RO
RO
VCL
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
GND
VCL
NODE A
FROM
PROGRAM
CARD
FN6589.0
February 22, 2008
80C88/883
Burn-In Circuits
(Continued)
COMPONENTS:
NOTES:
1. VCC = 5.5V ±0.5V, GND = 0V.
1. RI = 10kΩ ±5%, 1/4W
2. Input voltage limits (except clock):
VIL (Maximum) = 0.4V
VIH (Minimum) = 2.6V, VIH (Clock) = VCC - 0.4V) minimum.
2. RO = 1.2kΩ ±5%, 1/4W
3. VCC/2 is external supply set to 2.7V ±10%.
4. RC = 1kΩ ±5%, 1/4W
4. VCL is generated on program card (VCC - 0.65V).
5. C = 0.01µF (Minimum)
3. RIO = 2.7kΩ ±5%, 1/4W
5. Pins 13 through 16 input sequenced instructions from internal
hold devices, (DIP Only).
6. F0 = 100kHz ±10%.
7. Node A = a 40µs pulse every 2.56ms.
27
FN6589.0
February 22, 2008
80C88/883
Die Characteristics
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11KÅ ±2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm2
Metallization Mask Layout
80C88/883
A11
A12
A13
A14
GND
VCC
A15 A16/S3
A17/S4 A18/S5
A19/S6
A10
A9
SSO
MN/MX
A8
RD
AD7
HOLD
AD6
AD5
HLDA
AD4
AD3
WR
AD2
IO/M
AD1
DT/R
AD0
NMI
28
INTR CLK
GND
RESET READY TEST INTA
ALE
DEN
FN6589.0
February 22, 2008
80C88/883
Instruction Set Summary
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
76543210
76543210
76543210
76543210
Register/Memory to/from Register
100010dw
mod reg r/m
Immediate to Register/Memory
1100011w
mod 0 0 0 r/m
data
data if w 1
DATA TRANSFER
MOV = MOVE:
Immediate to Register
1 0 1 1 w reg
data
data if w 1
Memory to Accumulator
1010000w
addr-low
addr-high
Accumulator to Memory
1010001w
addr-low
addr-high
Register/Memory to Segment Register ††
10001110
mod 0 reg r/m
Segment Register to Register/Memory
10001100
mod 0 reg r/m
11111111
mod 1 1 0 r/m
PUSH = Push:
Register/Memory
0 1 0 1 0 reg
Register
0 0 0 reg 1 1 0
Segment Register
POP = Pop:
10001111
Register/Memory
mod 0 0 0 r/m
0 1 0 1 1 reg
Register
0 0 0 reg 1 1 1
Segment Register
XCHG = Exchange:
Register/Memory with Register
1000011w
mod reg r/m
1 0 0 1 0 reg
Register with Accumulator
IN = Input from:
Fixed Port
1110010w
Variable Port
1110110w
port
OUT = Output to:
Fixed Port
1110011w
Variable Port
1110111w
port
XLAT = Translate Byte to AL
11010111
LEA = Load EA to Register2
10001101
mod reg r/m
LDS = Load Pointer to DS
11000101
mod reg r/m
LES = Load Pointer to ES
11000100
mod reg r/m
LAHF = Load AH with Flags
10011111
SAHF = Store AH into Flags
10011110
PUSHF = Push Flags
10011100
POPF = Pop Flags
10011101
ARITHMETIC
ADD = Add:
Register/Memory with Register to Either
000000dw
mod reg r/m
Immediate to Register/Memory
100000sw
mod 0 0 0 r/m
data
Immediate to Accumulator
0000010w
data
data if w = 1
000100dw
mod reg r/m
data if s:w = 01
ADC = Add with Carry:
Register/Memory with Register to Either
29
FN6589.0
February 22, 2008
80C88/883
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
76543210
76543210
76543210
76543210
Immediate to Register/Memory
100000sw
mod 0 1 0 r/m
data
data if s:w = 01
Immediate to Accumulator
0001010w
data
data if w = 1
1111111w
mod 0 0 0 r/m
INC = Increment
Register/Memory
Register
0 1 0 0 0 reg
AAA = ASCll Adjust for Add
00110111
DAA = Decimal Adjust for Add
00100111
SUB = Subtract:
Register/Memory and Register to Either
001010dw
mod reg r/m
Immediate from Register/Memory
100000sw
mod 1 0 1 r/m
data
Immediate from Accumulator
0010110w
data
data if w = 1
000110dw
mod reg r/m
Immediate from Register/Memory
100000sw
mod 0 1 1 r/m
data
Immediate from Accumulator
0001110w
data
data if w = 1
1111111w
mod 0 0 1 r/m
data if s:w = 01
SBB = SUBTRACT WITH BORROW
Register/Memory and Register to Either
data if s:w = 01
DEC = DECREMENT
Register/Memory
Register
0 1 0 0 1 reg
NEG = Change Sign
1111011w
mod 0 1 1 r/m
001110dw
mod reg r/m
Immediate with Register/Memory
100000sw
mod 1 1 1 r/m
data
Immediate with Accumulator
0011110w
data
data if w = 1
AAS = ASCll Adjust for Subtract
00111111
DAS = Decimal Adjust for Subtract
00101111
MUL = Multiply (Unsigned)
1111011w
mod 1 0 0 r/m
IMUL = Integer Multiply (Signed)
1111011w
mod 1 0 1 r/m
AAM = ASCll Adjust for Multiply
11010100
00001010
DlV = Divide (Unsigned)
1111011w
mod 1 1 0 r/m
IDlV = Integer Divide (Signed)
1111011w
mod 1 1 1 r/m
AAD = ASClI Adjust for Divide
11010101
00001010
CBW = Convert Byte to Word
10011000
CWD = Convert Word to Double Word
10011001
CMP = COMPARE
Register/Memory and Register
data if s:w = 01
LOGIC
NOT = Invert
1111011w
mod 0 1 0 r/m
SHL/SAL = Shift Logical/Arithmetic Left
110100vw
mod 1 0 0 r/m
SHR = Shift Logical Right
110100vw
mod 1 0 1 r/m
SAR = Shift Arithmetic Right
110100vw
mod 1 1 1 r/m
ROL = Rotate Left
110100vw
mod 0 0 0 r/m
ROR = Rotate Right
110100vw
mod 0 0 1 r/m
RCL = Rotate Through Carry Flag Left
110100vw
mod 0 1 0 r/m
30
FN6589.0
February 22, 2008
80C88/883
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
76543210
76543210
76543210
76543210
110100vw
mod 0 1 1 r/m
0010000dw
mod reg r/m
Immediate to Register/Memory
1000000w
mod 1 0 0 r/m
data
data if w = 1
Immediate to Accumulator
0010010w
data
data if w = 1
Register/Memory and Register
1000010w
mod reg r/m
Immediate Data and Register/Memory
1111011w
mod 0 0 0 r/m
data
Immediate Data and Accumulator
1010100w
data
data if w = 1
Register/Memory and Register to Either
000010dw
mod reg r/m
Immediate to Register/Memory
1000000w
mod 1 0 1 r/m
data
Immediate to Accumulator
0000110w
data
data if w = 1
Register/Memory and Register to Either
001100dw
mod reg r/m
Immediate to Register/Memory
1000000w
mod 1 1 0 r/m
data
Immediate to Accumulator
0011010w
data
data if w = 1
disp-high
RCR = Rotate Through Carry Right
AND = And:
Reg./Memory and Register to Either
TEST = And Function to Flags, No Result:
data if w = 1
OR = Or:
data if w = 1
XOR = Exclusive or:
data if w = 1
STRING MANIPULATION
REP = Repeat
1111001z
MOVS = Move Byte/Word
1010010w
CMPS = Compare Byte/Word
1010011w
SCAS = Scan Byte/Word
1010111w
LODS = Load Byte/Word to AL/AX
1010110w
STOS = Stor Byte/Word from AL/A
1010101w
CONTROL TRANSFER
CALL = Call
Direct Within Segment
11101000
disp-low
Indirect Within Segment
11111111
mod 0 1 0 r/m
Direct Intersegment
10011010
offset-low
offset-high
seg-low
seg-high
Indirect Intersegment
11111111
mod 0 1 1 r/m
Direct Within Segment
11101001
disp-low
Direct Within Segment-Short
11101011
disp
Indirect Within Segment
11111111
mod 1 0 0 r/m
Direct Intersegment
11101010
offset-low
offset-high
seg-low
seg-high
JMP = UNCONDITIONAL JUMP
Indirect Intersegment
11111111
disp-high
mod 1 0 1 r/m
RET = Return from CALL
Within Segment
11000011
Within Seg Adding lmmed to SP
11000010
31
data-low
data-high
FN6589.0
February 22, 2008
80C88/883
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
76543210
76543210
76543210
data-high
Intersegment
11001011
Intersegment Adding Immediate to SP
11001010
data-low
JE/JZ = Jump on Equal/Zero
01110100
disp
JL/JNGE = Jump on Less/Not Greater or Equal
01111100
disp
JLE/JNG = Jump on Less or Equal/ Not Greater
01111110
disp
JB/JNAE = Jump on Below/Not Above or Equal
01110010
disp
JBE/JNA = Jump on Below or Equal/Not Above
01110110
disp
JP/JPE = Jump on Parity/Parity Even
01111010
disp
JO = Jump on Overflow
01110000
disp
JS = Jump on Sign
01111000
disp
JNE/JNZ = Jump on Not Equal/Not Zero
01110101
disp
JNL/JGE = Jump on Not Less/Greater or Equal
01111101
disp
JNLE/JG = Jump on Not Less or Equal/Greater
01111111
disp
JNB/JAE = Jump on Not Below/Above or Equal
01110011
disp
JNBE/JA = Jump on Not Below or Equal/Above
01110111
disp
JNP/JPO = Jump on Not Par/Par Odd
01111011
disp
JNO = Jump on Not Overflow
01110001
disp
JNS = Jump on Not Sign
01111001
disp
LOOP = Loop CX Times
11100010
disp
LOOPZ/LOOPE = Loop While Zero/Equal
11100001
disp
LOOPNZ/LOOPNE = Loop While Not Zero/Equal
11100000
disp
JCXZ = Jump on CX Zero
11100011
disp
Type Specified
11001101
type
Type 3
11001100
INTO = Interrupt on Overflow
11001110
IRET = Interrupt Return
11001111
76543210
INT = Interrupt
PROCESSOR CONTROL
CLC = Clear Carry
11111000
CMC = Complement Carry
11110101
STC = Set Carry
11111001
CLD = Clear Direction
11111100
STD = Set Direction
11111101
CLl = Clear Interrupt
11111010
ST = Set Interrupt
11111011
HLT = Halt
11110100
WAIT = Wait
10011011
ESC = Escape (to External Device)
11011xxx
LOCK = Bus Lock Prefix
11110000
32
mod x x x r/m
FN6589.0
February 22, 2008
80C88/883
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
76543210
NOTES:
AL = 8-bit accumulator
AX = 16-bit accumulator
CX = Count register
DS= Data segment
ES = Extra segment
Above/below refers to unsigned value.
Greater = more positive;
Less = less positive (more negative) signed values
if d = 1 then “to” reg; if d = 0 then “from” reg
if w = 1 then word instruction; if w = 0 then byte
instruction
if mod = 11 then r/m is treated as a REG field
if mod = 00 then DISP = 0†, disp-low and disp-high
are absent
if mod = 01 then DISP = disp-low sign-extended
16-bits, disp-high is absent
if mod = 10 then DISP = disp-high:disp-low
if r/m = 000 then EA = (BX) + (SI) + DISP
if r/m = 001 then EA = (BX) + (DI) + DISP
if r/m = 010 then EA = (BP) + (SI) + DISP
if r/m = 011 then EA = (BP) + (DI) + DISP
if r/m = 100 then EA = (SI) + DISP
if r/m = 101 then EA = (DI) + DISP
if r/m = 110 then EA = (BP) + DISP †
if r/m = 111 then EA = (BX) + DISP
DISP follows 2nd byte of instruction (before data
if required)
† except if mod = 00 and r/m = 110 then
EA = disp-high: disp-low.
†† MOV CS, REG/MEMORY not allowed.
33
76543210
76543210
76543210
if s:w = 01 then 16-bits of immediate data form the operand.
if s:w = 11 then an immediate data byte is sign extended
to form the 16-bit operand.
if v = 0 then “count” = 1; if v = 1 then “count” in (CL)
x = don't care
z is used for string primitives for comparison with ZF FLAG.
SEGMENT OVERRIDE PREFIX
001 reg 11 0
REG is assigned according to the following table:
16-BIT (w = 1)
8-BIT (w = 0)
SEGMENT
000 AX
000 AL
00 ES
001 CX
001 CL
01 CS
010 DX
010 DL
10 SS
011 BX
011 BL
11 DS
100 SP
100 AH
101 BP
101 CH
110 SI
110 DH
111 DI
111 BH
Instructions which reference the flag register file as a 16-bit
object use the symbol FLAGS to represent the file:
FLAGS =
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
Mnemonics © Intel, 1978
FN6589.0
February 22, 2008
80C88/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
BASE
METAL
E
M
-Bbbb S
C A-B S
(c)
Q
-C-
SEATING
PLANE
S1
b2
C A-B S
eA/2
NOTES
-
0.225
-
5.72
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
2.096
-
53.24
5
E
0.510
0.620
15.75
5
c
aaa M C A - B S D S
D S
MAX
0.014
eA
e
b
MIN
b
α
A A
MILLIMETERS
MAX
A
A
L
MIN
M
(b)
SECTION A-A
D S
INCHES
SYMBOL
b1
D
BASE
PLANE
ccc M
F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)
40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
12.95
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
-
eA/2
0.300 BSC
7.62 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.070
0.38
1.78
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
40
40
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
34
FN6589.0
February 22, 2008
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