REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Technical changes to table I. Editorial changes throughout. 91-12-23 M. L. Poelking B Update boilerplate to MIL-PRF-38535 requirements. - CFS 03-08-04 Thomas M. Hess C Update boilerplate to current MIL-PRF-38535 requirements. - CFS 08-07-16 Thomas M. Hess REV SHEET REV C C SHEET 15 16 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Tim H. Noh STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY Tim H. Noh APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE William K. Heckman DRAWING APPROVAL DATE MICROCIRCUIT, DIGITAL, CMOS, UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER MONOLITHIC SILICON 91-02-05 AMSC N/A REVISION LEVEL C SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 1 OF 5962-90525 16 5962-E382-08 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example. 5962 - 90525 Federal stock class designator \ RHA designator (see 1.2.1) 01 M Q X Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 02 HD-6402R HD-6402B Circuit function Clock frequency (fclk) Universal asynchronous receiver transmitter (UART) Universal asynchronous receiver transmitter (UART) 2.0 MHz 8.0 MHz 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class M Q or V Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Q Descriptive designator GDIP1-T40 or CDIP2-T40 Terminals Package style 40 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 2 1.3 Absolute maximum ratings. 1/ Supply voltage............................................................................................................ Input, output, or I/O voltage applied ........................................................................... Junction temperature (TJ)........................................................................................... Storage temperature range ........................................................................................ Lead temperature (soldering, 10 seconds)................................................................. Power dissipation (PD)................................................................................................ Thermal resistance, junction-to-case (θJC) ................................................................. Thermal resistance, junction-to-ambient (θJA) ............................................................ +8.0 V GND – 0.5 V dc to VCC +0.5 V dc +175°C -65°C to +150°C +300°C 1.03 W See MIL-STD-1835 48.3°C/W 1.4 Recommended operating conditions. Supply voltage (VCC) .................................................................................................. +4.5 V dc to +5.5 V dc Case operating temperature range (TC) ..................................................................... -55°C to +125°C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _______ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 3 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Control definition. The control definition shall be as specified on figure 2. 3.2.4 Block diagram. The block diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device type Limits Min Input high voltage VIH VCC = 5.5 V 1, 2, 3 All Input low voltage VIL VCC = 4.5 V 1, 2, 3 All Input leakage current II VO = 0 V or 5.5 V, VCC = 5.5 V 1, 2, 3 All -1.0 Output high voltage VOH IOH = -2.5 mA, VCC = 4.5 V 2/ 1, 2, 3 All 3.0 IOH = -100 μA, VCC = 4.5 V 2/ Max 2.3 V 0.8 V 1.0 μA V VCC – 0.4 Output low voltage VOL IOL = +2.5 mA, VCC = 4.5 V 2/ 1, 2, 3 All Output leakage current IO VO = 0 V or 5.5 V, VCC = 5.5 V 1, 2, 3 All Operating supply current ICC VO = 0 V or 5.5 V, VCC = 5.5 V, fclk = 2.0 MHz, Outputs open 1, 2, 3 3/ Unit 0.4 V 1.0 μA All 2.0 mA 1, 2, 3 All 100 μA -1.0 Standby supply current ISB VO = 0 V or 5.5 V, VCC = 5.5 V, Outputs open Input capacitance CIN All measurements are referenced to device GND, 4 All 25 pF Output capacitance COUT f = 1.0 MHz, TA = +125°C, See 4.4.1c 4 All 25 pF 7, 8 All Functional tests See 4.4.1b See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 9, 10, 11 01 2.0 02 8.0 Min Clock frequency CRL, DRR, and TBRL pulse width fCLK See figure 4. CL = 50 pF, VCC = 4.5 V tr = tf = 1.0 ns/V tPW 9, 10, 11 01 150 02 75 Unit Max MHz ns Pulse width MR tMR 9, 10, 11 All 150 ns Input data setup time tSET 9, 10, 11 01 50 ns 02 20 01 60 02 20 Input data hold time Output enable time tHOLD 9, 10, 11 9, 10, 11 tEN ns 01 160 02 35 ns 1/ All tests shall be performed using the worst case conditions, unless otherwise specified. 2/ Interchanging of force and sense conditions is permitted. Relaxed input levels for VOL and VOH may be used if separate VIL and VIH tests that guarantee threshold voltage transition are performed. 3/ If not tested, shall be guaranteed to the limits specified in table I. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 6 Device types: 01 and 02 Case outline Q Terminal number Terminal symbol Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC NC GND RRD RBR8 RBR7 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 PE FE OE SFD RRC DRR DR RRI 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MR TBRE TBRL TRE TRO TBR1 TBR2 TBR3 TBR4 TBR5 TBR6 TBR7 TBR8 CRL PI SBS CLS2 CLS1 EPE TRC NC = No connection FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 7 Control word Character format CLS2 CLS1 PI EPE SBS START BIT DATA BITS PARITY BIT STOP BITS 0 0 0 0 0 1 5 ODD 1 0 0 0 0 1 1 5 ODD 1.5 0 0 0 1 0 1 5 EVEN 1 0 0 0 1 1 1 5 EVEN 1.5 0 0 1 X 0 1 5 NONE 1 0 0 1 X 1 1 5 NONE 1.5 0 1 0 0 0 1 6 ODD 1 0 1 0 0 1 1 6 ODD 2 0 1 0 1 0 1 6 EVEN 1 0 1 0 1 1 1 6 EVEN 2 0 1 1 X 0 1 6 NONE 1 0 1 1 X 1 1 6 NONE 2 1 0 0 0 0 1 7 ODD 1 1 0 0 0 1 1 7 ODD 2 1 0 0 1 0 1 7 EVEN 1 1 0 0 1 1 1 7 EVEN 2 1 0 1 X 0 1 7 NONE 1 1 0 1 X 1 1 7 NONE 2 1 1 0 0 0 1 8 ODD 1 1 1 0 0 1 1 8 ODD 2 1 1 0 1 0 1 8 EVEN 1 1 1 0 1 1 1 8 EVEN 2 1 1 1 X 0 1 8 NONE 1 1 1 1 X 1 1 8 NONE 2 X = Irrelevant 0 = Low level voltage 1 = High level voltage FIGURE 2. Control definition. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 8 Note: These outputs are three-state. FIGURE 3. Block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 9 Note: CL includes stray and jig capacitance. FIGURE 4. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 10 FIGURE 4. Switching waveforms and test circuit - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 11 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. b. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125°C, minimum. Interim and final electrical test parameters shall be as specified in table II herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. c. Subgroup 4 (CIN and COUT measurements) shall be measured only for the initial test and after process or design changes which may affect capacitance. Sample size is 15 devices with no failures, and all input and output terminals tested. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 12 TABLE II. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-PRF-38535, table III) Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class M Device class Q Device class V Interim electrical parameters (see 4.2) --- --- 1, 7, 9 Final electrical parameters (see 4.2) 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1/ 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1/ 1, 2, 3, 7, 8A, 8B, 9, 10, 11 2/ 1, 2, 3, 4, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4, 7, 8A, 8B, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 Group D end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 Group A test requirements (see 4.4) 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C, D, or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. b. TA = +125°C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 13 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone (614) 692-00547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535, MIL-HDBK-1331, and as follows: Symbol Definition Functional description VCC Positive supply current. A .01μF decoupling capacitor from the VCC pin to the GND pin is recommended. NC No connection. GND Ground. RRD Receiver register disable A high level on receiver register disable forces the receiver holding outputs RBR1 – RBR8 to high impedance state. RBR1 through RBR8 Receiver buffer register The contents of the receiver buffer register appear on these three-state outputs. Word formats less than 8 characters are right justified to RBR1. PE Parity error A high level on parity error indicates received parity does not match parity programmed by control bits. When parity is inhibited this output is low. FE Framing error A high level on framing error indicates the first stop bit was invalid. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 14 Symbol Definition Functional description OE Overrun error A high level on overrun error indicates the data received flag was not cleared before the last character was transferred to the receiver buffer register. SFD Status flags disable A high level on status flags disable forces the outputs PE, FE, OE, DR, and TBRE to a high impedance state. RRC Receiver register clock The receiver register clock is 16X the receiver data rate. DRR Data received reset A low level on data received reset clears the data received output DR to a low level. DR Data received A high level on data received indicates a character has been received and transferred to the receiver buffer register. RRI Receiver register input Serial data on receiver register input is clocked into the receiver register. MR Master reset A high level on master reset clears PE, FE, OE, and DR to a low level and sets the transmitter register empty (TRE) to a high level 18 clock cycles after MR falling edge. MR does not clear the receiver buffer register. This input must be pulsed at least once after power-up. The reset pulse should meet VIH and tMR. Wait 18 clock cycles after the falling edge of MR before beginning operation. TBRE Transmitter buffer register empty A high level on transmitter buffer register empty indicates the transmitter buffer register has transferred its data to the transmitter register and is ready for new data. TBRL Transmitter buffer register load A low level on transmitter buffer register load transfers data from inputs TBR1 – TBR8 into the transmitter buffer register. A low-to-high transition on TBRL initiates data transfer to the transmitter register. If busy, transfer is automatically delayed so that the two characters are transmitted end-to-end. TRE Transmitter register empty A high level on transmitter register empty indicates completed transmission of a character including stop bits. TRO Transmitter register output Character data, start data and stop bits appear serially at the transmitter register output. TBR1 through TBR8 Transmitter buffer register Character data is loaded into the transmitter buffer register via inputs TBR1 – TBR8. For character formats less than 8 bits the TBR8, 7, and 6 inputs are ignored corresponding to their programmed word length. CRL Control register load A high level on control register load loads the control register with the control word. The control word is latched on the falling edge of CRL. PI Parity inhibit A high level on parity inhibit inhibits parity generation, parity checking, and forces PE output low. SBS Stop bit select A high level on stop bit select selects 1.5 stop bits for 5 character format and 2 stop bits for other lengths. CLS1, CLS2 Character length selected These inputs program the character length selected (CLS1 low, CLS2 low, 5 bits) (CLS1 high, CLS2 low, 6 bits) (CLS1 low, CLS2 high, 7 bits) ( CLS1 high, CLS2 high, 8 bits). EPE Even parity enable When PI is low, a high level on even parity enable generates and checks even parity. A low level selects odd parity. TRC Transmitter register clock The transmitter register clock is 16X the transmit data rate. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 15 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90525 A REVISION LEVEL C SHEET 16 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 08-07-16 Approved sources of supply for SMD 5962-90525 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/ . Vendor similar PIN 2/ Standard microcircuit drawing PIN 1/ Vendor CAGE number 5962-9052501MQA 34371 HD1-6402R/883 5962-9052502MQA 34371 HD1-6402B/883 1/ 2/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 34371 Vendor name and address Intersil Corporation 1001 Murphy Ranch Road Milpitas, CA 95035-6803 Point of contact: 1650 Robert J. Conlan Blvd. Palm Bay, FL 32905 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.