DATASHEET

HD-15530
TM
CMOS Manchester Encoder-Decoder
March 1997
Features
Description
• Support of MlL-STD-1553
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for
the Master Reset functions.
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
TEMP. RANGE
CERDIP
-40oC to +85oC
-55oC to +125oC
SMD#
1.25 MEGABIT/s
HD1-15530-9
PKG. NO.
F24.6
HD1-15530-8
7802901JA
CLCC
-40oC to +85oC
HD4-15530-9
-55oC to +125oC
HD4-15530-8
SMD#
J28.A
78029013A
-40oC to +85oC
PDIP
HD3-15530-9
This circuit meets many of the requirements of MIL-STD1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmental control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
E24.6
Pinouts
UNIPOLAR DATA IN 8
ENCODER
SHIFT CLK
VALID
WORD
VCC
2
1
28
ENCODER
CLK
SEND
CLK IN
TAKE DATA
3
27
26
5
25
SEND
DATA
NC
6
24
NC
NC
7
23
NC
8
22
9
21
10
20
11
19
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
DECODER SHIFT CLK 9
COMMAND/
DATA SYNC 10
DECODER RESET 11
16 OUTPUT INHIBIT
BIPOLAR
15 ZERO OUT
14 ÷ 6 OUT
GND 12
13 MASTER RESET
BIPOLAR
ZERO IN
BIPOLAR
ONE IN
UNIPOLAR
DATA IN
DECODER
SHIFT CLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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142
12
13
14
15
16
17
18
OUTPUT
INHIBIT
7
4
DECODER
CLK
BIPOLAR
ZERO OUT
BIPOLAR ONE IN
20 SYNC SELECT
÷ 6 OUT
BIPOLAR ZERO IN 6
21 SEND DATA
MASTER
RESET
5
22 SEND CLK IN
GND
DECODER CLK
23 ENCODER CLK
DECODER
RESET
SERIAL DATA OUT 4
24 VCC
COMMAND/
DATA SYNC
VALID WORD 1
ENCODER
SHIFT CLK 2
TAKE DATA 3
HD-15530 (CLCC)
TOP VIEW
SERIAL
DATA OUT
HD-15530 (CERDIP, PDIP)
TOP VIEW
SYNC
SELECT
ENCODER
ENABLE
SERIAL
DATA IN
BIPOLAR
ONE OUT
FN2960.1
HD-15530
Block Diagrams
ENCODER
12
13
22
14
VCC
MASTER RESET
SEND CLK IN
÷ 6 OUT
UNIPOLAR 8
DATA IN
BIPOLAR 7
ONE IN
BIPOLAR 6
ZERO IN
24
OUTPUT
INHIBIT
17
÷2
CHARACTER
FORMER
÷6
23
DECODER
GND
15
16
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
ENCODER
CLK
DECODER
CLK
BIT
COUNTER
21
2
SEND
DATA
18
19
SERIAL
DATA IN
MASTER
RESET
20
SYNC
SELECT
5
3
TRANSITION
FINDER
BIT
RATE
CLK
SYNCHRONIZER
10 COMMAND/
DATA SYNC
4 SERIAL
DATA OUT
9
11
TAKE
DATA
PARITY 1 VALID
CHECK
WORD
13
DECODER
RESET
ENCODER
ENABLE
ENCODER
SHIFT CLK
CHARACTER
IDENTIFIER
DECODER
SHIFT
CLK
BIT
COUNTER
Pin Description
PIN
NUMBER
TYPE
1
O
2
NAME
SECTION
DESCRIPTION
VALID WORD
Decoder
Output high indicates receipt of a valid word, (valid parity and no Manchester errors).
O
ENCODER SHIFT
CLOCK
Encoder
Output for shifting data into the Encoder. The Encoder samples SDI on the
low-to-high transition of Encoder Shift Clock.
3
O
TAKE DATA
Decoder
Output is high during receipt of data after identification of a sync pulse and
two valid Manchester data bits.
4
O
SERIAL DATA OUT
Decoder
Delivers received data in correct NRZ format.
5
I
DECODER CLOCK
Decoder
Input drives the transition finder, and the synchronizer which in turn
supplies the clock to the balance of the decoder, input a frequency equal to
12X the data rate.
6
I
BIPOLAR ZERO IN
Decoder
A high input should be applied when the bus is in its negative state. This pin
must be held high when the Unipolar input is used.
7
I
BIPOLAR ONE IN
Decoder
A high input should be applied when the bus is in its positive state. This pin
must be held low when the Unipolar input is used.
8
I
UNLPOLAR DATA IN
Decoder
With pin 6 high and pin 7 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
9
O
DECODER SHIFT
CLOCK
Decoder
Output which delivers a frequency (DECODER CLOCK ÷ 12), synchronized by the recovered serial data stream.
10
O
COMMAND SYNC
Decoder
Output of a high from this pin occurs during output of decoded data which
was preceded by a Command (or Status) synchronizing character. A low
output indicates a Data synchronizing character.
11
I
DECODER RESET
Decoder
A high input to this pin during a rising edge of DECODER SHIFT CLOCK
resets the decoder bit counting logic to a condition ready for a new word.
12
I
GROUND
Both
Ground Supply pin.
13
I
MASTER RESET
Both
A high on this pin clears 2:1 counters in both Encoder and Decoder, and
resets the ÷ 6 circuit.
14
O
÷ 6 OUT
Encoder
Output from 6:1 divider which is driven by the ENCODER CLOCK.
15
O
BIPOLAR ZERO OUT
Encoder
An active low output designed to drive the zero or negative sense of a
bipolar line driver.
16
I
OUTPUT INHIBIT
Encoder
A low on this pin forces pin 15 and 17 high, the inactive states.
17
O
BIPOLAR ONE OUT
Encoder
An active low output designed to drive the one or positive sense of a bipolar
line driver.
143
HD-15530
Pin Description
PIN
NUMBER
TYPE
18
I
19
(Continued)
SECTION
DESCRIPTION
SERIAL DATA IN
Encoder
Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
I
ENCODER ENABLE
Encoder
A high on this pin initiates the encode cycle. (Subject to the preceeding
cycle being complete.)
20
I
SYNC SELECT
Encoder
Actuates a Command sync for an input high and Data sync for an input low.
21
O
SEND DATA
Encoder
An active high output which enables the external source of serial data.
22
I
SEND CLOCK IN
Encoder
Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6
output.
23
I
ENCODER CLOCK
Encoder
Input to the 6:1 divider, a frequency equal to the data rate X12 is usually
input here.
24
I
VCC
Both
VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC
(pin 24) to GROUND (pin 12) is recommended.
I = Input
NAME
O = Output
Encoder Operation
ENCODER SHIFT CLOCK so it can be sampled on the lowto-high transition 3 - 4 . After the sync and Manchester II
coded data are transmitted through the BIPOLAR ONE and
BIPOLAR ZERO outputs, the Encoder adds on an additional
bit which is the parity for that word 5 . If ENCODER
ENABLE is held high continuously, consecutive words will
be encoded without an interframe gap. ENCODER ENABLE
must go low by time 5 as shown to prevent a consecutive
word from being encoded. At any time a low on OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by dividing the DECODER CLOCK.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK 1 .
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word 2 . When the Encoder is ready to accept data,
the SEND DATA output will go high and remain high for sixteen ENCODER SHIFT CLOCK periods 3 . During these
sixteen periods the data should be clocked into the SERIAL
DATA input with every high-to-low transition of the
TIMING
0
1
2
3
4
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
5
6
7
15
16
17
18
19
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
SYNC SELECT
DON’T CARE
VALID
DON’T CARE
SEND DATA
SERIAL
DATA IN
15
BIPOLAR
ONE OUT
1ST HALF 2ND HALF
BIPOLAR
ZERO OUT
SYNC
1 2
SYNC
14
13
12
11
10
3
2
1
0
15
14
13
12
11
3
2
1
0
P
15
14
13
12
11
3
2
1
0
P
3
4
FIGURE 1.
144
5
HD-15530
Decoder Operation
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The BIPOLAR
ONE and BIPOLAR ZERO inputs will accept data from a
comparator sensed transformer coupled bus as specified in
Military Spec 1553. The UNIPOLAR DATA input can only
accept non-inverted Manchester II coded data. (e.g. from
BIPOLAR ONE OUT of an Encoder through an inverter to
Unipolar Data Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized 1 , the type of sync is indicated on
COMMAND/DATA SYNC output. If the sync character was a
command sync, this output will go high 2 and remain high
for sixteen DECODER SHIFT CLOCK periods 3 , otherwise
it will remain low. The TAKE DATA output will go high and
remain high 2 - 3 while the Decoder is transmitting the
decoded data through SERIAL DATA OUT. The decoded
TIMING
0
1
2
data available at SERIAL DATA OUT is in NRZ format. The
DECODER SHIFT CLOCK is provided so that the decoded
bits can be shifted into an external register on every low-tohigh transition of this clock 2 - 3 . Note that DECODER
SHIFT CLOCK may adjust its phase up until the time that
TAKE DATA goes high.
After all sixteen decoded bits have been transmitted 3 the
data is checked for odd parity. A high on VALID WORD
output 4 indicates a successful reception of a word without
any Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown 1 .
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and initialize the Decoder to start looking for a new sync character.
3
4
5
6
7
8
16
17
18
19
15
14
13
12
11
10
2
1
0
P
15
14
13
12
11
10
2
1
0
P
DECODER
SHIFT CLK
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
1ST HALF 2ND HALF
SYNC
SYNC
TAKE DATA
COMMAND/
DATA SYNC
SERIAL
DATA OUT
VALID WORD
15
UNDEFINED
14
13
12
4
3
2
1
0
(FROM PREVIOUS RECEPTION)
1
3
2
FIGURE 2.
145
4
HD-15530
How to Make Our MTU Look Like a Manchester Encoded UART
VCC
VALID WORD
DECODER
ENCODER CLK
SYNC
SELECT
BIPOLAR
ZERO IN
1
24
2
23
3
22
BIPOLAR
ONE IN
4
21
5
20
UNIPOLAR
DATA IN
6
19
7
18
COMMAND
SYNC
8
17
9
16
10
15
11
14
12
13
DECODER
RESET
A
B
CK H
74LS164
A
B
ENCODER
ENABLE
BIPOLAR
ONE OUT
INHIBIT
OUTPUT
BIPOLAR
ZERO OUT
MASTER
RESET
CK
OH SH/LD CK SI OH SH/LD CK
74165
74165
74LS164
PARALLEL OUT
PARALLEL IN
FIGURE 3.
Typical Timing Diagrams for a Manchester Encoded UART
VALID
VALID
ENCODER ENABLE
SYNC SELECT
PARALLEL IN
BIPOLAR ONE OUT
P
BIPOLAR ZERO OUT
P
SYNC
MSB
LSB
PARITY
FIGURE 4. ENCODER TIMING
SYNC
MSB
LSB
BIPOLAR ONE IN
PARITY
P
BIPOLAR ZERO IN
P
COMMAND SYNC
PARALLEL OUT
VALID WORD
VALID
VALID
FROM
PREVIOUS
RECEPTION
FIGURE 5. DECODER TIMING
146
HD-15530
MIL-STD-1553
The 1553 standard defines a time division multiplexed data
bus for application within aircraft. The bus is defined to be
bipolar, and encoded in a Manchester II format, so no DC
component appears on the bus. This allows transformer
coupling and excellent isolation among systems and their
environment.
Words. Terminals respond with Status Words. Each word is
preceded by a synchronizing pulse, and followed by parity
bit, occupying a total of 20µs. The word formats are shown in
Figure 4. The special abbreviations are as follows:
P
Parity, which is defined to be odd, taken across all 17
bits.
R/T
Receive on logical zero, transmit on ONE.
The HD-15530 supports the full bipolar configuration,
assuming a bus driver configuration similar to that in Figure
1. Bipolar inputs from the bus, like Figure 2, are also accommodated.
ME
Message Error if logical 1.
TF
Terminal Flat, if set, calls for controller to request
self-test data.
The signaling format in MlL-STD-1553 is specified on the
assumption that the network of 32 or fewer terminals are
controlled by a central control unit by means of Command
The paragraphs above are intended only to suggest the
content of MlL-STD-1553, and do not completely describe its
bus requirements, timing or protocols.
BUS
+
-
“1”
“1”
“1” REF
“0” REF
+
“0”
“0”
BUS
FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIVER
FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER
0
COMMAND
SYNC
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
COMMAND WORD (FROM CONTROLLER TO TERMINAL)
5
DATA
SYNC
SYNC
1
TERMINAL
ADDRESS
5
5
1
SUB ADDRESS
/MODE
DATA WORD
COUNT
P
R/T
BIT
PERIOD
BIT
PERIOD
BIT
PERIOD
DATA WORD (SENT EITHER DIRECTION)
LOGICAL ONE DATA
SYNC
16
1
CONTROL WORD
P
STATUS WORD (FROM TERMINAL TO CONTROLLER)
5
LOGICAL ZERO DATA
SYNC
1
TERMINAL
ADDRESS
9
FIGURE 9. MIL-STD-1553 WORD FORMATS
NOTE: This page is a summary of MIL-STD-1553 and is not intended to describe the operation of the HD-15530.
147
1
CODE FOR FAILURE MODES TF P
ME
FIGURE 8. MIL-STD-1553 CHARACTER FORMATS
1
HD-15530
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . .
55
12
CLCC Package . . . . . . . . . . . . . . . . . .
65
14
Plastic DIP Package . . . . . . . . . . . . . .
60
N/A
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Temperature Range (TA)
HD-15530-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
HD-15530-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Encoder/Decoder Clock Rise Time . . . . . . . . . . . . . . . . . . .8ns Max
Encoder/Decoder Clock Fall Time . . . . . . . . . . . . . . . . . . . . 8ns Max
Sync Transition Span (TD2) . . . . . . . . . . . . . . . 18 TDC Typ (Note 1)
Short Data Transition Span (TD4) . . . . . . . . . . . 6 TDC Typ (Note 1)
Long Data Transition Span (TD5). . . . . . . . . . . 12 TDC Typ (Note 1)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-15530-9)
TA = -55oC to +125oC (HD-15530-8)
LIMITS
PARAMETER
SYMBOL
MIN
MAX
Input LOW Voltage
V IL
-
0.2 VCC
VCC = 4.5V and 5.5V
V
Input HIGH Voltage
VlH
0.7 VCC
-
VCC = 4.5V and 5.5V
V
Input LOW Clock Voltage
VILC
-
GND +0.5
VCC = 4.5V and 5.5V
V
Input HIGH Clock Voltage
VIHC
VCC -0.5
-
VCC = 4.5V and 5.5V
V
Output LOW Voltage
VOL
-
0.4
IOL = 1.8mA (Note 2), VCC = 4.5V
V
Output HIGH Voltage
VOH
2.4
-
IOH = -3mA (Note 2), VCC = 4.5V
V
Input Leakage Current
II
-1.0
+1.0
VI = GND or V CC, VCC = 5.5V
µA
Standby Supply Current
ICCSB
-
2
VIN = VCC = 5.5V Output Open
mA
Operating Power Supply Current
ICCOP
-
10
VCC = 5.5V, VIN = VCC, f =15MHz, Outputs Open
mA
FT
-
-
Function Test
TEST CONDITIONS
(Note 3)
UNITS
-
NOTES:
1. TDC = Decoder clock period = 1/FDC
2. Interchanging of force and sense conditions is permitted.
3. Tested as follows: = f = 15MHz, VIH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH ≥ 1.5V and VOL ≤ 1.5V.
Capacitance TA = +25oC; Frequency = 1MHz
SYMBOL
PARAMETER
TYPICAL
UNITS
CIN
Input Capacitance
15
pF
CO
Output Capacitance
15
pF
148
CONDITIONS
All measurements are referenced to device GND
HD-15530
AC Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-15530-9)
TA = -55oC to +125oC (HD-15530-8)
PARAMETER
SYMBOL
(NOTE 2)
TEST CONDITIONS
LIMITS
MIN
MAX
UNITS
ENCODER TIMING
Encoder Clock Frequency
FEC
VCC = 4.5V and 5.5V, CL = 50pF
-
15
MHz
FESC
VCC = 4.5V and 5.5V, CL = 50pF
-
2.5
MHz
Encoder Data Rate
FED
VCC = 4.5V and 5.5V, CL = 50pF
-
1.25
MHz
Master Reset Pulse Width
TMR
VCC = 4.5V and 5.5V, CL = 50pF
150
-
ns
Shift Clock Delay
TE1
VCC = 4.5V and 5.5V, CL = 50pF
-
125
ns
Serial Data Setup
TE2
VCC = 4.5V and 5.5V, CL = 50pF
75
-
ns
Serial Data Hold
TE3
VCC = 4.5V and 5.5V, CL = 50pF
75
-
ns
Enable Setup
TE4
VCC = 4.5V and 5.5V, CL = 50pF
90
-
ns
Enable Pulse Width
TE5
VCC = 4.5V and 5.5V, CL = 50pF
100
-
ns
Sync Setup
TE6
VCC = 4.5V and 5.5V, CL = 50pF
55
-
ns
Sync Pulse Width
TE7
VCC = 4.5V and 5.5V, CL = 50pF
150
-
ns
Send Data Delay
TE8
VCC = 4.5V and 5.5V, CL = 50pF
0
50
ns
Bipolar Output Delay
TE9
VCC = 4.5V and 5.5V, CL = 50pF
-
130
ns
Enable Hold
TE10
VCC = 4.5V and 5.5V, CL = 50pF
10
-
ns
Sync Hold
TE11
VCC = 4.5V and 5.5V, CL = 50pF
95
-
ns
Decoder Clock Frequency
FDC
VCC = 4.5V and 5.5V, CL = 50pF
-
15
MHz
Decoder Data Rate
FDD
VCC = 4.5V and 5.5V, CL = 50pF
-
1.25
MHz
Decoder Reset Pulse Width
TDR
VCC = 4.5V and 5.5V, CL = 50pF
150
-
ns
Decoder Reset Setup Time
TDRS
VCC = 4.5V and 5.5V, CL = 50pF
75
-
ns
Decoder Reset Hold Time
TDRH
VCC = 4.5V and 5.5V, CL = 50pF
10
-
ns
Master Reset Pulse
TMR
VCC = 4.5V and 5.5V, CL = 50pF
150
-
ns
Bipolar Data Pulse Width
TD1
VCC = 4.5V and 5.5V, CL = 50pF
TDC + 10
(Note 1)
-
ns
One Zero Overlap
TD3
VCC = 4.5V and 5.5V, CL = 50pF
-
TDC - 10
(Note 1)
ns
Sync Delay (ON)
TD6
VCC = 4.5V and 5.5V, CL = 50pF
-20
110
ns
Take Data Delay (ON)
TD7
VCC = 4.5V and 5.5V, CL = 50pF
0
110
ns
Serial Data Out Delay
TD8
VCC = 4.5V and 5.5V, CL = 50pF
-
80
ns
Sync Delay (OFF)
TD9
VCC = 4.5V and 5.5V, CL = 50pF
0
110
ns
Take Data Delay (OFF)
TD10
VCC = 4.5V and 5.5V, CL = 50pF
0
110
ns
Valid Word Delay
TD11
VCC = 4.5V and 5.5V, CL = 50pF
0
110
ns
Send Clock Frequency
DECODER TIMING
NOTES:
1. TDC = Decoder clock period = 1/FDC
2. AC Testing as follows: Input levels: V IH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing Reference levels: 1.5V;
Output load: CL = 50pF.
149
HD-15530
Timing Waveforms
SEND CLOCK
TE1
ENCODER SHIFT CLOCK
TE2
SERIAL DATA IN
TE3
VALID
VALID
SEND CLOCK
TE1
ENCODER SHIFT CLOCK
TE4
ENCODER ENABLE
TE5
TE6
VALID
SYNC SELECT
TE7
ENCODER SHIFT CLOCK
TE8
SEND DATA
SEND CLOCK
TE9
BIPOLAR ONE OUT OR
BIPOLAR ZERO OUT
FIGURE 10. ENCODER TIMING
150
HD-15530
Timing Waveforms
(Continued)
DECODER SHIFT CLOCK
TD6
COMMAND/DATA SYNC
TAKE DATA
TD7
DECODER SHIFT CLOCK
TD8
SERIAL DATA OUT
DATA BIT
DECODER SHIFT CLOCK
TD9
COMMAND/DATA SYNC
TD10
TAKE DATA
VALID WORD
TD11
DECODER SHIFT CLOCK
TDRS
DECODER RESET
TDR
TDRH
FIGURE 11. DECODER TIMING
151
HD-15530
Timing Waveforms
(Continued)
NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS.
BIT PERIOD
BIT PERIOD
BIPOLAR ONE IN
BIT PERIOD
TD3
TD1
BIPOLAR ZERO IN
TD2
TD1
TD2
COMMAND SYNC
TD3
BIPOLAR ONE IN
TD1
BIPOLAR ZERO IN
TD1
TD3
TD3
TD2
TD2
DATA SYNC
TD1
TD1
BIPOLAR ONE IN
TD3
TD3
TD3
BIPOLAR ZERO IN
TD3
TD1
TD3
TD1
TD4
TD5
ONE
TD5
TD4
ZERO
ONE
NOTE: BIPOLAR ONE IN = 0; BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS.
UNIPOLAR IN
TD2
TD2
COMMAND SYNC
TD2
UNIPOLAR IN
TD2
DATA SYNC
UNIPOLAR IN
TD5
TD4
ONE
TD4
TD5
ZERO
ONE
TD4
ONE
FIGURE 12. DECODER TIMING
Test Load Circuit
AC Testing Input, Output Waveform
INPUT
VIH
DUT
50%
CL9
(NOTE)
NOTE: Includes stray and jig capacitance.
OUTPUT
VOH
VIL
50%
VOL
AC Testing: All input signals must switch between V IL and VIH.
Input rise and fall times are driven at 1ns per volt.
152
HD-15530
Burn-In Circuits
HD1-15530 CERDIP
VCC
C1
GND
A
1
24
A
2
23
A
3
22
4
21
5
20
6
19
A
R1
F0
7
18
GND
8
17
A
9
16
10
15
GND
11
14
GND
12
13
R1
A
R1
R1
VCC
F0
A
R1
R1
R1
GND
VCC
VCC
GND
R1
R1
VCC
A
R1
R1
GND
GND
R1
R1
HD4-15530 CLCC
VCC
C1
GND GND GND GND
R2
4
R2
3
2
F0
R2
R2
1
28
27
26
5
25
GND
NC
6
24
NC
NC
7
23
NC
8
22
GND
9
21
VCC
10
20
GND
11
19
GND
GND
R2
12
13
14
15
16
17
18
R2
VCC
R2
R2
GND GND GND GND
NOTES:
1. VCC = 5.5V ± 0.5V
2. VIH = 4.5V ± 10%
3. V IL = -0.2V +0.4V
4. R1 = 47KΩ ± 5%
5. R2 = 1.8KΩ ± 5%
6. F0 = 100KHz ± 10%
7. C1 = 0.01µF Min.
R2
F0
Die Characteristics
DIE DIMENSIONS:
155 x 195 x 19mils
GLASSIVATION:
Type: SiO2
Thickness: 8kA ±1kÅ
METALLIZATION:
Type: Si-Al
Thickness: 11kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
1.8 x 105 A/cm2
Metallization Mask Layout
HD-15530
ENCODER
SHIFT CLK
VCC
VALID
WORD
ENCODER CLK
TAKE DATA
SEND CLK IN
SERIAL DATA OUT
SEND DATA
DECODER CLK
SYNC SELECT
BIPOLAR ZERO IN
ENCODER ENABLE
BIPOLAR ONE IN
SERIAL DATA IN
UNIPOLAR DATA IN
BIPOLAR ONE OUT
DECODER SHIFT CLK
OUTPUT INHIBIT
BIPOLAR ZERO OUT
COMMAND/DATA SYNC
DECODER
RESET
GND
MASTER
RESET
÷ 6 OUT
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