DATASHEET

HS-3282
TM
REFERENCE AN400
CMOS ARINC Bus Interface Circuit
March 1997
Features
Description
• ARlNC Specification 429 Compatible
The HS-3282 is a high performance CMOS bus interface
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
serial data protocols. This device is intended to be used with
the HS-3182, a monolithic Dl bipolar differential line driver
designed to meet the specifications of ARINC 429. The
ARINC 429 bus interface circuit consists of two (2) receivers
and a transmitter operating independently as shown in
Figure 1. The two receivers operate at a frequency that is
ten (10) times the receiver data rate, which can be the same
or different from the transmitter data rate. Although the two
receivers operate at the same frequency, they are
functionally independent and each receives serial data asynchronously. The transmitter section of the ARINC bus
interface circuit consists mainly of a First-In First-Out (FIFO)
memory and timing circuit. The FIFO memory is used to hold
up to eight (8) ARINC data words for transmission serially.
The timing circuit is used to correctly separate each ARINC
word as required by ARINC Specification 429. Even though
ARINC Specification 429 specifies a 32-bit word, including
parity, the HS-3282 can be programmed to also operate with
a word length of 25 bits. The incoming receiver data word
parity is checked, and a parity status is stored in the receiver
latch and output on Pin BD08 during the 1st word. [A logic
“0” indicates that an odd number of logic “1” s were received
and stored; a logic “1” indicates that an even number of logic
“1”s were received and stored]. In the transmitter the parity
generator will generate either odd or even parity depending
upon the status of PARCK control signal. A logic “0” on
BD12 will cause odd parity to be used in the output data
stream.
• Data Rates of 100 Kilobits or 12.5 Kilobits
• Separate Receiver and Transmitter Section
• Dual and Independent Receivers, Connecting Directly
to ARINC Bus
• Serial to Parallel Receiver Data Conversion
• Parallel to Serial Transmitter Data Conversion
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
• Generate Parity of Transmitter Data
• Automatic Word Gap Timer
• Single 5V Supply
• Low Power Dissipation
• Full Military Temperature Range
Ordering Information
PACKAGE
CERDIP
TEMP. RANGE
-55oC to +125oC
SMD#
CLCC
-40oC to +85oC
-55oC to +125oC
SMD#
PART NUMBER
PKG.
NO.
HS1-3282-8
F40.6
5962-8688001QA
F40.6
HS4-3282-9+
J44.A
HS4-3282-8
J44.A
5962-8688001XA
J44.A
Versatility is provided in both the transmitter and receiver by
the external clock input which allows the bus interface circuit
to operate at data rates from 0 to 100 kilobits. The external
clock must be ten (10) times the data rate to insure no data
ambiguity.
The ARINC bus interface circuit is fully guaranteed to
support the data rates of ARINC specification 429 over both
the voltage (±5%) and full military temperature range. It
interfaces with UL, CMOS or NMOS support circuitry, and
uses the standard 5-volt VCC supply.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
183
FN2964.2
HS-3282
Pinouts
HS-3282 (CERDIP)
TOP VIEW
VDD
1
40 NC
429DI1(A)
2
39 MR
429DI1(B)
3
38 TX CLK
429DI2(A)
4
37 CLK
429DI2(B)
5
36 NC
D/R1
6
35 NC
D/R2
7
34 CWSTR
SEL
8
33 ENTX
EN1
9
32 429D0
EN2
10
31 429D0
BD15
11
30 TX/R
BD14
12
29 PL2
BD13
13
28 PL1
BD12
14
27 BD00
BD11
15
26 BD01
BD10
16
25 BD02
BD09
17
24 BD03
BD08
18
23 BD04
BD07
19
22 BD05
BD06
20
21 GND
NC
2
CLK
429DI1(A)
3
MR
429DI1(B)
4
TXCLK
429DI2(A)
5
NC
429DI2(B)
6
VDD
NC
HS-3282 (CLCC)
TOP VIEW
1 44 43 42 41 40
NC 7
39 NC
D/R1 8
38 NC
D/R2 9
37 CWSTR
SEL 10
36 ENTX
EN1 11
35 429D0
EN2 12
34 429D0
BD15 13
33 TX/R
BD14 14
32 PL2
BD13 15
31 PL1
BD12 16
30 BD00
BD11 17
29 BD01
184
BD02
BD03
BD04
BD05
GND
BD06
BD07
BD08
BD09
NC
BD10
18 19 20 21 22 23 24 25 26 27 28
HS-3282
Pin Description
PIN
SYMBOL
SECTION
DESCRIPTION
1
VCC
Recs/Trans
2
429 DI1 (A)
Receiver
ARlNC 429 data input to Receiver 1.
3
429 DI1 (B)
Receiver
ARlNC 429 data input to Receiver 1.
4
429 Dl2 (A)
Receiver
ARINC 429 data input to Receiver 2.
5
429 DI2 (B)
Receiver
ARINC 429 data input to Receiver 2.
6
D/R1
Receiver
Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched.
7
D/R2
Receiver
Device ready flag output from Receiver 2 indicating a valid data word is ready to be fetched.
8
SEL
Receiver
Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2.
9
EN1
Receiver
Input signal to enable data from Receiver 1 onto the data bus.
10
EN2
Receiver
Input signal to enable data from Receiver 2 onto the data bus.
11
BD15
Recs/Trans
Bi-directional data bus for fetching data from either of the Receivers, or for loading data into
the Transmitter memory or control word register. See Control Word Table for description of
Control Word bits.
12
BD14
Recs/Trans
See Pin 11.
13
BD13
Recs/Trans
See Pin 11.
14
BD12
Recs/Trans
See Pin 11.
15
BD11
Recs/Trans
See Pin 11.
16
BD10
Recs/Trans
See Pin 11.
17
BD09
Recs/Trans
See Pin 11.
18
BD08
Recs/Trans
See Pin 11.
19
BD07
Recs/Trans
See Pin 11.
20
BD06
Recs/Trans
See Pin 11.
21
GND
Recs/Trans
Circuit Ground.
22
BD05
Recs/Trans
See Pin 11.
23
BD04
Recs/Trans
See Pin 11. Control Word function not applicable.
24
BD03
Recs/Trans
See Pin 11. Control Word function not applicable.
25
BD02
Recs/Trans
See Pin 11. Control Word function not applicable.
26
BD01
Recs/Trans
See Pin 11. Control Word function not applicable.
27
BD00
Recs/Trans
See Pin 11. Control Word function not applicable.
28
PL1
Transmitter
Parallel load input signal loading the first 16-bit word into the Transmitter memory.
29
PL2
Transmitter
Parallel load input signal loading the first 16-bit word into the Transmitter memory and initiates data transfer into the memory stack.
30
TX/R
Transmitter
Transmitter flag output to indicate the memory is empty.
Supply pin 5 volts ±5%.
185
HS-3282
Pin Description
(Continued)
PIN
SYMBOL
SECTION
DESCRIPTION
31
429D0
Transmitter
Data output from Transmitter
32
429D0
Transmitter
Data output from Transmitter.
33
ENTX
Transmitter
Transmitter Enable input signal to initiate data transmission from FIFO memory.
34
CWSTR
Recs/Trans
Control word input strobe signal to latch the control word from the databus into the control
word register.
35
-
-
No connection. Must be left open.
36
-
-
No connection. Must be left open or tied low but never tied high.
37
CLK
Recs/Trans
External clock input. May be either ten (10) or eighty (80) times the data rate. If using both
ARINC data rates it must be ten (10) times the highest data rate, (typically 1MHz).
38
TXCLK
Transmitter
Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate.
39
MR
Recs/Trans
Master Reset. Active low pulse used to reset FIFO, bit counters, gap timer, word count signal,
TX/R and various other flags and controls. Master reset does not reset the control word
register. Usually only used on Power-Up or System Reset.
40
-
-
No Connection.
Pinout
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC NC
186
NC
HS-3282
Operational Description
The HS-3282 is designed to support ARINC Specification
429 and other serial data protocols that use a similar format
by collecting the receiving, transmitting, synchronizing,
timing and parity functions on a single, low power LSl circuit.
It goes beyond the ARlNC requirements by providing for
either odd or even parity, and giving the user a choice of
either 25 or 32-bit word lengths. The receiver and transmitter
sections operate independently of each other. The serial-toparallel conversion required of the receiver and the parallelto-serial conversion requirements of the transmitter have
been incorporated into the bus interface circuit.
Provisions have been made through the external clock input
to provide data rate flexibility. This requires an external clock
that is 10 times the data rate.
To obtain the flexibility discussed above, a number of
external control signals are required, To reduce the pin
count requirements, an internal control word register is used.
The control word is latched from the data bus into the register by the Control Word Strobe (CWSTR) signal going to a
logic “1”. Eleven (11) control functions are used, and along
with the Bus Data (BD) line are listed below:
Control Word
PIN NAME
SYMBOL
FUNCTION
BD05
SLFTST
Connects the self test signal from the transmitter directly to the receiver shift registers, bypassing the input
receivers. Receiver 1 receives Data True and Receiver 2 receives Data Not. Note that the transmitter output
remains active. (Logic “0” on SLFTST Enables Self Test).
BD06
SDENB1
Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder).
BD07
X1
If SDENB1 = “1” then this bit is compared with ARlNC Data Bit #9. If Y1 also matches (see Y1), the word will be
accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
BD08
Y1
If SDENBI = “1” then this bit is compared with ARINC Data Bit #10. If X1 also matches (see X1), the word will
be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
BD09
SDENB2
BD10
X2
If SDENB2 = “1” then this bit is compared with ARlNC Data Bit #9. If Y2 also matches (see Y2), the word will be
accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
BD11
Y2
If SDENB2 = “1” then this bit is compared with ARINC Data Bit #10. If X2 also matches (see X2), the word will
be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
BD12
PARCK
Signal used to invert the transmitter parity bit for test of parity circuits. Logic “0” selects normal odd parity. Logic
“I” selects even parity.
BD13
TXSEL
Selects high or low Transmitter data rate. If TXSEL = “0” then transmitter data rate is equal to the clock rate
divided by ten (10). If TXSEL = “1” then transmitter data rate is equal to the clock rate divided by eighty (80).
BD14
RCVSEL
Selects high or low Receiver data rate. If RCVSEL = “0” then the received data rate should be equal to the clock
rate divided by ten (10), if RCVSEL = “1 “then the received data rate should be equal to the clock rate divided
by eighty (80).
BD15
WLSEL
Selects word length. If WLSEL = “0” a 32-bit word format will be selected. If WLSEL = “1” a 25-Bit word format
will be selected.
Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder).
ARlNC 429 DATA FORMAT as input to the Receiver and
output from the Transmitter is as follows:
TABLE 1. ARINC 429 32-BIT DATA FORMAT
This format is shuffled when seen on the sixteen bidirectional input/outputs. The format shown below is used from
the receivers and input to the transmitter:
TABLE 2A. WORD 1 FORMAT
ARINC BIT #
FUNCTION
1-8
Label
9 - 10
SDl or Data
BI-DIRECTIONAL
BIT #
FUNCTION
ARINC BlT #
11
LSB
15, 14
Data
13, 12
12 - 27
Data
13
LSB
11
28
MSB
12, 11
SDl or Data
10, 9
29
Sign
10, 9
SSM Status
31, 30
30, 31
SSM
8
Parity Status
32
Parity Status
7 - 00
Label
1-8
32
187
HS-3282
• The Line Receiver functions as a voltage level translator.
It transforms the 10 volt differential line voltage, ARINC
429 format, into 5 volt internal logic level.
TABLE 2B. WORD 2 FORMAT
BI-DIRECTIONAL
BlT#
FUNCTION
ARINC BIT#
15
Sign
29
14
MSB
28
13 - 00
Data
27 - 14
• The output of the Line Receiver is one of two inputs to the
Self-Test Data Selector (SEL). The other input to the
Data Selector is the Self-Test Signal from the Transmitter
section.
Receiver Parity Status:
0 = Odd Parity
1 = Even Parity
If the receiver input data word string is broken before the
entire data word is received, the receiver will reset and
ignore the partially received data word.
If the transmitter is used to transmit consecutive data words,
each word will be separated by a four (4) bit “null” state (both
positive and negative outputs will maintain a zero (0) volt
level.)
FUNCTION
1-8
Label
9
LSB
11 - 23
Data
24
MSB
25
Parity Status
• After the receiver data has been shifted down the shift
register, it is placed in a holding register. The device ready
flag will then be set indicating that data is ready to be
fetched. If the data is ignored and left in the holding register, it will be written over when the next data word is
received.
TABLE 4A. WORD 1 FORMAT
BI-DIRECTIONAL
BIT#
FUNCTION
ARINC BIT#
15 - 9
Don’t Care
XXX
8
Parity Status
25
7-0
Label
1-8
• The received data in the 32-bit holding register is placed
on the bus in the form of two (2)16-bit words regardless of
whether the format is for 32 or 25-bit data words. Either
word can be accessed first or repeatedly until the next
received data word falls into the holding register.
TABLE 4B. WORD 2 FORMAT
BI-DIRECTIONAL
BIT#
FUNCTION
• The parity of the incoming word is checked and the status
(i.e., logic “0” for odd parity and logic “1” for even parity)
stored in the receiver latch and output on BD08 during the
Word No. 1.
ARINC BlT#
15
MSB
24
14 - 1
Data
23 -10
0
LSB
9
• The derived data clock then shifts the data down a 32-Bit
long Data Shift Register (Data S/RI). The Data Word
Length is selectable for either 25 Bits or 32 Bits long by
the Control Signal (WLSEL). As soon as the data word is
completely received, an internal signal (WDCNT1) is generated by the Word Gap Timer Circuit.
• The Source/Destination (S/D) Decoder compares the user
set code (X and Y) with Bits 9 and 10 of the Data Word. If
the two codes are matched, a positive signal is generated
to enable the WDCNT1 signal to latch in the received
data. Otherwise, the data word is ignored and no latching
action takes place. The S/D Decoder can be Enabled and
Disabled by the control signal S/D ENB. If the data word is
latched, an indicator flag (D/R1) is set. This indicates a
valid data word is ready to be fetched by the user.
TABLE 3. ARINC 25-BIT DATA FORMAT
ARINC BIT #
• The incoming data, either Self-Test or ARlNC 429, is
double sampled by the Word Gap Timer to generate a
Data Clock. The Receiver sample frequency (RCVCLK),
1MHz, or 125kHz, is generated by the Receiver/Transmitter Timing Circuit. This sampling frequency is ten times the
Data Rate to ensure no data ambiguity.
Receiver Parity Status:
0 = Odd Parity
1 = Even Parity
No Source/Destination (S/D) in 25-Bit format.
Receiver Operation
Since the two receivers are functionally identical, only one
will be discussed in detail, and the block diagram will be
used for reference in this discussion. The receiver consists
of the following circuits:
• Assuming the user desires to access the data, he first sets
the Data Select Line (SEL) to a Logic “0” level and pulses
the Enable (EN1) line. This action causes the Data
Selector (SELl) to select the first-data word, which contains the label field and Enable it onto the Data Bus. To
obtain the second data word, the user sets the SEL line to
a Logic “1” level and pulse the Enable (EN1) line again.
The Enable pulse duration is matched to the user circuit
requirement needed to read the Data Word from the Data
Bus. The second Enable pulse is also used to reset the
Device Ready (D/R1) flip-flop. This completes a receiving
cycle.
188
HS-3282
Transmitter Operation
Sample Interface Technique
The Transmitter section consists of an 8-word deep by 31Bit long FIFO Memory, Parity Generator, Transmitter Word
Gap Timing Circuit and Driver Circuit.
From Figure 1, one can see that the Data Bus is time shared
between the Receiver and Transmitter. Therefore, bus
controlling must be synchronously shared between the
Receiver and the Transmitter.
• The FlFO Memory is organized in such a way that data
loaded in the input register is automatically transferred to
the output register for Serial Data Transmission. This
eliminates a large amount of data managing time since the
data need not be clocked from the input register to the
output register. The FIFO input register is made up of two
sets of 16 D-type flip-flops, which are clocked by the two
parallel load signals (PL1 and PL2). PL1 must always
precede PL2. Multiple PL1’s may occur and data will be
written over. As soon as PL2 is received, data is
transferred to the FIFO. The data from the Data Bus is
clocked into the D-type flip-flop on the positive going edge
of the PL signals. If the FIFO memory is initially empty, or
the stack is not full, the data will be automatically
transferred down the Memory Stack and into the output
register or to the last empty FIFO storage register. If the
Transmitter Enable signal (ENTX) is not active, a Logic
“0”, the data remains at the output register. The FIFO
Memory has storage locations to hold eight 31-bit words. If
the memory is full and the new data is again strobed with
PL, the old data at the input register is written over by the
new data. Data will remain in the Memory until ENTX goes
to a Logic “1”. This activates the FIFO Clock and data is
shifted out serially to the Transmitter Driver. Data may be
loaded into the FIFO only while ENTX is inactive (low). It is
not possible to write data into the FIFO while transmitting.
WARNING: If PL1 or PL2 is applied while ENTX is high,
i.e., while transmitting, the FlFO may be disrupted such
that it would require a MR (Master Reset) signal to
recover.
• The Output Register of the FIFO is designed such that it
can shift out a word of 24 Bits long or 31 Bits long. This
word length is again controlled by the WLSEL bit. The TX
word Gap Timer Circuit also automatically inserts a gap
equivalent to 4-Bit Times between each word. This gives a
minimum requirement of 29-Bit time or 36-Bit time for each
word transmission. Assuming the signal, ENTX, remains
at a Logic “1”, a transfer to stack signal is generated to
transfer the data down the Memory Stack one position.
This action is continued until the last word is shifted out of
the FIFO memory. At this time a Transmitter Ready (TX/R)
flag is generated to signal the user that the Transmitter is
ready to receive eight more data words. During transmission, if ENTX is taken low then high again, transmission
will cease leaving a portion of the word untransmitted, and
the data integrity of the FIFO will be destroyed.
• A Bit Counter is used to detect the last Bit shifted out of
the FIFO memory and appends the Parity Bit generated
by the Parity Generator. The Parity Generator has a
control signal, Parity Check (PARCK), which establishes
whether odd or even parity is used in the output data
word. PARCK set to a logic “0” will result in odd parity and
when set to a logic “1” will result in even parity.
Figure 2 shows the typical interface timing control of the
ARlNC Chip for Receiving function and for Transmitting
function. Timing sequence for loading the Transmitter FIFO
Memory is shown in Timing Interval A. A transmitter Ready
(TX/R) Flag signals the user that the Transmitter Memory is
empty. The user then Enables the Transmitter Data, a 16-Bit
word, on the Data Bus and strobes the Transmitter with a
Parallel Load (PL1) Signal. The second part of the 32-Bit
word is similarly loaded into the Transmitter with PL2, which
also initiates data transfer to stack. This is continuous until
the Memory is full, which is eight 31-Bit words. The user
must keep track of the number of words loaded into the
Memory to ensure no data is written over by other data.
During the time the user is loading the Transmitter, he does
not have to service the Receiver, even if the Receiver flags
the user with the signal D/R1 that a valid received word is
ready to be fetched. This is shown by the Timing interval B. If
the user decides to obtain the received data before the
Transmitter is completely loaded, he sets the two parallel
load signals (PL1 and PL2) at a Logic “1” state, and strobes
EN1 while the signal SEL is at a Logic “0” state. After the
negative edge of EN1, the first 16-Bit segment of the
received word becomes valid on the Data Bus. At the
positive edge of EN1, the user should toggle the signal SEL
to ready the Receiver for the second 16-Bit word. Strobing
the Receiver with EN1, the second time, enables the second
16-Bit word and resets the Receiver Ready Flag D/R1. The
user should now reset the signal SEL to a Logic “0” state to
ready the Receiver for another Read Cycle. During the time
period that the user is fetching the received words, he can
load the transmitter. This is done by interlacing the PL
signals with the EN signals as shown in the Timing Interval
B. Servicing the Receiver 2 is similar and is illustrated by
Timing interval C. Timing interval D shows the rest of the
Transmitter loading sequence and the beginning of the
transmission by switching the signal TX Enable to a Logic “1”
state. Timing interval E is the time it takes to transmit all data
from the FlFO Memory, either 288 Bit times or 232 Bit times.
Repeater Operation
This mode of operation allows a data word that has been
received to be placed directly in the FIFO for transmission. A
timing diagram is shown in Figure 7. A 32-bit word is used in
this example. The data word is shifted into the shift register
and the D/R flag goes low. A logic “0” is placed on the SEL
line and EN1 is strobed. This is the same as the normal
receiver operation and places half the data word (16 bits) on
the data bus. By strobing PL1 at the same time as EN1,
these 16 bits will be taken off the bus and placed in the
FIFO. SEL is brought back high and EN1 is strobed again for
the second 16 bits of the data word. Again by strobing PL2 at
the same time the second 16 bits will be placed in the FIFO.
The parity bit will have been stripped away leaving the 31-bit
data word in the FIFO ready for transmission as shown in
Figure 6.
189
HS-3282
CLK
TX CLK
37
WLSEL
SELF
TEST
429D11 (A)
429D11 (B)
RCV CLK
RCVSEL
WDCNT 1
WORD GAP
TXSEL
DATA CLOCK
SEL
LINE
RECEIV.
ER 1
3
DATA S/R 1
TX
TIMING
RCV
CLK
CONTROL
WORD
REGISTER
TX
CLK
32
LATCH 1
S/DENB
SEL EN1
11
16
SEL 1
16
S/D
DECODER
16
GND
21
SLF TST
(BD05)
S/D ENB1
(BD06)
S/D ENB2
(BD09)
X1 (BD07)
Y1 (BD06)
X2 (BD10)
Y2 (BD11)
PARCK
(BD12)
TXSEL
(BD13)
RCVSEL
(BD14)
WLSEL
(BD15)
WDCNT 1
34
WDCNT 2
16
SEL 2
16
TX CLK
16
D
F/F
S/D CODER
429D12 (B)
VCC
1
2
SLF
TEST
429D12 (A)
RCV
38
D
F/F
SEL EN2
LATCH 2
CWSTR
WLSEL
TX WORD
GAP
33
ENTX
4
5
16
32
LINE
RECEIV.
ER 2
SEL
16
DATA S/R 2
DATA CLOCK
SELF
TEST
WLSEL
WORD GAP
16
FIFO
8 x 31
TXC
DRVR
PARITY
11 - 20
32
429D0
WDCNT 2
22 - 27
RCV CLK
39
MR
6
7
D/R1 D/R2
8
9
10
28
SEL EN1 EN2
BD15BD00
DATA
BUS
29
PL1 PL2
30
PARCK
TX/R
FIGURE 1. SINGLE CHIP ARINC 429 INTERFACE FUNCTIONAL BLOCK DIAGRAM
190
429D0
31
SELF
TEST
HS-3282
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage Applied
(Except Pins 2 - 5) . . . . . . . . . . . . . . . . GND -0.3V to VDD +0.3V
Input Voltage Applied (Pins 2 - 5). . . . . . . . . . . . . . . . . -29V to +29V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA (oC/W) θJC (oC/W)
CDIP Package . . . . . . . . . . . . . . . . . . .
35
8
CLCC Package . . . . . . . . . . . . . . . . . .
55
12
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range
HS-3282-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
HS-3282-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2632 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
ARlNC INPUTS Pins 2-3,4-5
Logic “1” Input Voltage
V lH
VDD = 5.25V
6.7
13.0
V
Logic “0” Input Voltage
VIL
VDD = 5.25V
-13.0
-6.7
V
Null Input Voltage
VNUL
VDD = 4.75V, 5.25V
-2.5
+2.5
V
Common Mode Voltage
VCH
VDD = 4.75V, 5.25V
-5.0
+5.0
V
Input Leakage
IlH
VDD = 5.25V, VIN = ±6.5V
-
200
µA
Input Leakage
IlL
VDD = 5.25V, VIN = 0.0V
-450
-
µA
Differential Input Impedance
RI
VDD = 5.25V, VIN = +5V, -5V
12
-
kΩ
Input lmpedance to VDD
RH
VDD = 5.25V, VlN = 0V
12
-
kΩ
Input lmpedance to GND
RG
VDD = Open, VlN = 5.0V
12
-
kΩ
BIDIRECTIONAL INPUTS Pins 11-20, 22-27
Logic “1” Input Voltage
VIH
VDD = 5.25V
2.1
-
V
Logic “0” Input Voltage
V IL
VDD = 4.75V
-
0.7
V
Input Leakage
lIH
VDD = 5.25V,VIN = 5.25V
-
1.5
µA
Input Leakage
IlL
VDD = 5.25V, VIN = 0.0V
-1.5
-
µA
ALL OTHER INPUTS Pins 8-10, 28, 29, 33, 34, 37, 39
Logic “1” Input Voltage
VIH
VDD = 5.25V
3.5
-
V
Logic “0” Input Voltage
V IL
VDD = 4.75V
-
0.7
V
Input Leakage
IlH
VDD = 5.25V, VIN = 5.25V
-
10
µA
Input Leakage
IlL
VDD = 5.25V, VIN = 0.0V
-75
-
µA
2.7
-
V
OUTPUTS Pins 6, 7, 11-20, 22-27, 30-32, 38, Supply Pin 1
Logic “1” Output Voltage
V OH
VDD = 4.75V, IOH = -1.5mA
Logic “0” Output Voltage
VOL
VDD = 4.75V lOL= 1.8mA
-
0.4
V
Standby Supply Current
lCC1
VDD = 5.25V, VIN = 0V Except 9,10,
29 = 5.25V
-
20
mA
Operating Supply Current
lCC2
VDD = 5.25V, VIN = 5.25V Except 8,
33 = 0.0V, CLK = 1MHz
-
20
mA
191
HS-3282
AC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Clock Frequency
FC
VDD = 4.75V, 5.25V
-
1
MHz
Data Rate 1/
FD
VDD = 4.75V, 5.25V
-
100
kHz
Data Rate 2/
FD
VDD = 4.75V, 5.25V
-
12.5
kHz
TMR
VDD = 4.75V, 5.25V
200
-
ns
Receiver Ready Time From 32nd Bit 1/
TD/R2
VDD = 4.75V, 5.25V
-
16
µs
Receiver Ready Time From 32nd Bit 2/
TD/R2
VDD = 4.75V, 5.25V
-
128
µs
TD/REN
VDD = 4.75V, 5.25V
0
-
ns
TEN
VDD = 4.75V, 5.25V
200
-
ns
Data Enable to Data Enable Time
TENEN
VDD = 4.75V, 5.25V
50
-
ns
Data Enable to Device Ready Reset Time
TEND/R
VDD = 4.75V, 5.25V
-
200
ns
Output Data Valid to Enable Time
TENDATA
VDD = 4.75V, 5.25V
-
200
ns
Data Enable to Data Select Time
TENSEL
VDD = 4.75V, 5.25V
20
-
ns
Data Select to Data Enable Time
TSELEN
VDD = 4.75V, 5.25V
20
-
ns
TDATAEN
VDD = 4.75V, 5.25V
-
80
ns
Control Word Strobe Pulse Width
TCWSTR
VDD = 4.75V, 5.25V
130
-
ns
Control Word Setup Time
TCWSET
VDD = 4.75V, 5.25V
130
-
ns
Control Word Hold Time
TCWHLD
VDD = 4.75V, 5.25V
0
-
ns
TPL
VDD = 4.75V, 5.25V
200
-
ns
Parallel Load to Parallel Load 2 Delay
TPL12
VDD = 4.75V, 5.25V
0
-
ns
Transmitter Ready Delay Time
TTX/R
VDD = 4.75V, 5.25V
-
840
ns
Data Word Setup Time
TDWSET
VDD = 4.75V, 5.25V
110
-
ns
Data Word Hold Time
TDWHLD
VDD = 4.75V, 5.25V
0
-
ns
Enable Transmit to Output Data Valid Time 1/
TENDAT
VDD = 4.75V, 5.25V
-
25
µs
Enable Transmit to Output Data Valid Time 2/
TENDAT
VDD = 4.75V, 5.25V
-
200
µs
Output Data Bit Time 1/
TBlT
VDD = 4.75V, 5.25V
4.95
5.05
µs
Output Data Bit Time 2/
TBlT
VDD = 4.75V, 5.25V
39.6
40.4
µs
Output Data Null Time 1/
TNULL
VDD = 4.75V, 5.25V
4.95
5.05
µs
Output Data Null Time 2/
TNULL
VDD = 4.75V, 5.25V
39.6
40.4
µs
Master Reset Pulse Width
RECEIVER TIMING
Device Ready to Enable Time
Data Enable Pulse Width
Output Data Disable Time
CONTROL WORD TIMING
TRANSMITTER FIFO Write Timing
Parallel Load Pulse Width
TRANSMITTER Output Timing
192
HS-3282
AC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8) (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Data Word Gap Time 1/
TGAP
VDD = 4.75V, 5.25V
39.6
40.4
µs
Data Word Gap Time 2/
TGAP
VDD = 4.75V, 5.25V
316.8
323.2
µs
TDTX/R
VDD = 4.75V, 5.25V
-
400
ns
TENTX/R
VDD = 4.75V, 5.25V
0
-
ns
Data Enable to Parallel Load Delay Time
TENPL
VDD = 4.75V, 5.25V
0
-
ns
Data Enable Hold for Parallel Load Time
TPLEN
VDD = 4.75V, 5.25V
0
-
ns
TTX/REN
VDD = 4.75V, 5.25V
0
-
ns
MIN
MAX
UNITS
Data Transmission Word to TX/R Set Time
Enable Transmit Turnoff Time
REPEATER OPERATION TIMING
Enable Transmit Delay Time
NOTES:
1. 100kHz Data Rate.
2. 12.5kHz Data Rate.
Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8)
LIMITS
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
Differential Input Capacitance
CD
VDD = Open, f = 1MHz, Note 2, 3
-
20
pF
Input Capacitance to VDD
CH
VDD = GND, f = 1MHz, Note 2, 3
-
20
pF
lnput Capacitance to GND
CG
VDD = Open, f = 1MHz, Note 2, 3
-
20
pF
Input Capacitance
Cl
VDD = Open, f = 1MHz, Note 2, 4
-
15
pF
Output Capacitance
CO
VDD = Open, f = 1MHz, Note 2, 5
-
15
pF
Clock Rise Time
TLHC
CLK = 1MHz, From 0.7V to 3.5V
-
10
ns
Clock Fall Time
THLC
CLK = 1MHz, From 3.5V to 0.7V
-
10
ns
Input Rise Time
TLHI
From 0.7V to 3.5V, Note 6
-
15
ns
Input Fall Time
THLI
From 3.5V to 0.7V, Note 6
-
15
ns
NOTES:
1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes affecting these parameters.
2. All measurements are referenced to device GND.
3. Pins 2-3, 4-5.
4. Pins 8-10, 28, 29, 33, 34, 37, 39.
5. Pins 6, 7, 11-20, 22-27, 30-32, 38.
6. Pins 8-20, 22-29, 33, 34.
193
HS-3282
Timing Waveforms
TX/R
TX ENABLE
DATA BUS
PL1
PL2
D/R1
D/R2
EN1
EN2
SEL
TIME
INTERVAL A
TIME
INTERVAL B
TIME
INTERVAL C
BUS IS BEING USED AS AN OUTPUT
TIME
INTERVAL D
TIME
INTERVAL E
BUS IS BEING USED AS AN INPUT
FIGURE 2. TYPICAL INTERFACE TIMING SEQUENCE
429DI
BIT
32
tD/R
tEND/R
D/R
tD/REN
tENEN
EN
tSELEN
SEL
tEN
tENDATA
BD00-15
tSELEN
tENSEL
tENSEL
tEN
tDATAEN
tENDATA
WORD
1
tDATAEN
WORD
2
OR
SEL
BD00-15
WORD
2
FIGURE 3. RECEIVER TIMING
194
WORD
1
HS-3282
Timing Waveforms
(Continued)
tCWSTR
CWSTR
tCWHLD
tCWSET
BD00-15
CONTROL WORD
FIGURE 4. CONTROL WORD TIMING
PL1
tPL12
tPL
PL2
tTX/R
tPL
TX/R
tDWSET
tDWSET
tDWHLD
BD00-15
WORD 1
tDWHLD
WORD 2
FIGURE 5. TRANSMITTER FIFO WRITE TIMING
TX/R
tENTX/R
ENTX
tBIT
tNUL
tENDAT
42900
BIT
1
tNUL
BIT
2
BIT
32
tNUL
tGAP
BIT
1
BIT
32
tDTX/R
FIGURE 6. TRANSMITTER OUTPUT TIMING
195
HS-3282
Timing Waveforms
429DI
(Continued)
BIT
32
tEND/R
tD/R
D/R
tD/REN
EN
tSELEN
tEN
tENEN
tEN
tSELEN
tENSEL
tENSEL
SEL
tENPL
tPLEN
PL1
tENPL
tPLEN
PL2
tTX/R
TX/R
tTX/REN
tENTX/R
ENTX
tENDAT
tNUL
BIT
1
429D0
BIT
32
tDTX/R
FIGURE 7. REPEATER OPERATION TIMING
196
HS-3282
Burn-In Circuits
HS-3282 CERDIP
C
GND
VDD
1 VDD
NC 40
NC
F4
2 DI1(A)
MR 39
F15
GND
3 DI1(B)
TX CLK 38
NC
F4
4 DI2(A)
CLK 37
F0
GND
5 DI2(B)
NC 36
NC
NC
6 D/R1
NC 35
NC
NC
7 D/R2
CWSTR 34
VDD
F9
8 SEL
ENTX 33
GND
VDD
9 EN1
429D0 32
NC
F8
10 EN2
429D0 31
NC
F15
11 BD15
TX/R 30
NC
F14
12 BD14
PL2 29
F8
F13
13 BD13
PL1 28
F8
F12
14 BD12
BD00 27
F0
F11
15 BD11
BD01 26
F1
F10
16 BD10
BD02 25
F2
F9
17 BD09
BD03 24
F3
F8
18 BD08
BD04 23
F4
F7
19 BD07
BD05 22
F5
F6
20 BD06
21
GND
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
197
Burn-In Circuits
HS-3282 CLCC
NC
DI2(A)
DI1(B)
DI1(A)
NC
F4
VDD
2
F0
GND
3
NC
F4
4
F15
GND
5
C
NC
NC
6
DI2(B)
GND
NC
CLK
TXCLK
MR
NC
VCC
1 44 43 42 41 40
NC
7
NC
NC 39
NC
NC
8
D/R1
NC 38
NC
NC
9
D/R2
CWSTR 37
VDD
F9
10 SEL
ENTX 36
GND
VDD
11 EN1
D0 35
NC
F8
12 EN2
D0 34
NC
F0
F11
17 BD11
BD01 29
F1
BD02
BD00 30
BD03
16 BD12
BD04
F8
F12
BD05
F13
PL1 31
GND
F8
15 BD13
BD06
PL2 32
BD07
14 BD14
BD08
NC
F14
BD09
TX/R 33
BD10
13 BD15
NC
F15
NOTES:
1. Resistors = 47kΩ, 5%, 1/4W (Min)
2. GND = Ground
3. VDD = +5.5V, ±0.5V
4. C = 0.01mF/Socket (Min)
5. F0 = 100kHz, F1 = F0/2, . . . F15 = F14/2
198
F02
F03
F04
F05
GND
F06
F07
F08
F09
NC
F10
18 19 20 21 22 23 24 25 26 27 28
Die Characteristics
DIE DIMENSIONS:
246 x 224 x 19 mils)
(6250 x 5700 x 483µm)
GLASSIVATION:
Type: SiO2
Thickness: 8kA ±1kÅ
METALLIZATION:
Type: Si-Al
Thickness: 11kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
2 x 105 A/cm2
Metallization Mask Layout
(37) CLK
(38) TX CLK
(39) MR
(40) N/C
(2) 429DI1(A)
(1) VDD
(4) 429DI2(A)
(3) 429DI1(B)
(5) 429DI2(B)
(6) D/R1
HS-3282
D/R2 (7)
(36) N/C
SEL (8)
EN1 (9)
(35) N/C
EN1 (10)
(34) CWSTR
BD15 (11)
(33) ENTX
BD14 (12)
(32) 429D0
(31) 429D0
BD13 (13)
(30) TX/R
BD12 (14)
(29) PL2
BD11 (15)
(28) PL1
BD10 (16)
BD01 (26)
BD02 (25)
BD03 (24)
BD04 (23)
BD05 (22)
GND (21)
BD06 (20)
BD07 (19)
BD08 (18)
BD09 (17)
(27) BD00
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
199
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