DATASHEET

Single 8/Differential 4-Channel CMOS Analog
Multiplexers with Active Overvoltage Protection
HI-548/883, HI-549/883
Features
The HI-548/883 and HI-549/883 are analog multiplexers with
active overvoltage protection and guaranteed rON matching.
Analog input levels may greatly exceed either power supply
without damaging the device or disturbing the signal path of
other channels. Active protection circuitry assures that signal
fidelity is maintained even under fault conditions that would
destroy other multiplexers.
• This Circuit is Processed in Accordance to MIL-STD-883 and
is Fully Conformant Under the Provisions of Paragraph 1.2.1.
Analog inputs can withstand constant 70VP-P levels with ±15V
supplies. Digital inputs will also sustain continuous faults up to
4V greater than either supply. In addition, signal sources are
protected from short circuiting should multiplexer supply loss
occur. Each input presents 1kΩ of resistance under this
condition. These features make the HI-548/883 and
HI-549/883 ideal for use in systems where the analog inputs
originate from external equipment or separately powered
circuitry. Both devices are fabricated with 44V Dielectrically
Isolated CMOS technology. The HI-548/883 is an 8-channel
device, and the HI-549/883 is a 4-channel differential version.
If input overvoltage protection is not needed, the HI-508/883
and HI-509/883 multiplexers are recommended. For further
information see Application Note AN520.
• No Channel Interaction During Overvoltage
• Guaranteed rON Matching
• 44V Maximum Power Supply
• Break-Before-Make Switching
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0µs
• Power Dissipation (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 45mW
Applications
• Data Acquisition Systems
• Control Systems
• Telemetry
Ordering Information
PART #
April 9, 2012
FN8256.0
1
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
HI1-0548/883 HI1-548/883
-55 to 125
16 Ld CerDIP F16.3
HI4-0548/883 HI4-0548 /883
-55 to 125
20 Ld CLCC
HI1-0549/883 HI1-549/883
-55 to 125
16 Ld CerDIP F16.3
J20.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HI-548/883, HI-549/883
Pin Configurations
HI-549/883
(16 LD CERDIP)
TOP VIEW
HI-548/883
(16 LD CERDIP)
TOP VIEW
A0 1
16 A1
ENABLE 2
15 A2
A0 1
ENABLE 2
14 GND
-VSUPPLY 3
-VSUPPLY 3
16 A1
15 GND
14 +VSUPPLY
IN 1 4
13 +VSUPPLY
IN 1A 4
13 IN 1B
IN 2 5
12 IN 5
IN 2A 5
12 IN 2B
IN 3 6
11 IN 6
IN 3A 6
11 IN 3B
IN 4 7
10 IN 7
IN 4A 7
10 IN 4B
OUT 8
9 IN 8
OUT A 8
9 OUT B
HI-548/883
(20 LD CLCC)
A2
2
A1
A0
3
NC
ENABLE
TOP VIEW
1 20 19
18 GND
-VSUPPLY 4
17 +VSUPPLY
IN 1 5
NC 6
16 NC
IN 2 7
15 IN 5
14 IN 6
IN 3 8
2
IN 7
IN 8
NC
OUT
IN 4
9 10 11 12 13
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Functional Diagrams
TRUTH TABLE HI-548/883
HI-548/883
1k
OUT
IN 1
IN 2
1k
DECODER/
DRIVER
1k
IN 8
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
5V
REF
LEVEL
SHIFT
† DIGITAL INPUT
PROTECTION
†
†
A0
†
A1 A2
†
A2
A1
A0
EN
“ON” CHANNEL
X
X
X
L
None
L
L
L
H
1
L
L
H
H
2
L
H
L
H
3
L
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
EN
TRUTH TABLE HI-549/883
HI-549/883
1k
OUT A
IN 1A
1k
IN 4A
IN 1B
OUT B
1k
1k
DECODER/
DRIVER
IN 4B
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
5V
REF
A1
A0
EN
“ON” CHANNEL PAIR
X
X
L
None
L
L
H
1
L
H
H
2
H
L
H
3
H
H
H
4
LEVEL
SHIFT
† DIGITAL INPUT
PROTECTION
3
†
†
†
A0
A1
EN
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Absolute Maximum Ratings
Thermal Information
Voltage Between Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
+VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
-VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Analog Input Voltage, +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +20V
Analog Input Voltage, -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-VSUPPLY -20V
Digital Input Voltage, +VEN, +VA . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V
Digital Input Voltage, - VEN, -VA . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY +4V
or 20mA, whichever occurs first
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed at 1ms, 10% Duty Cycle Max) . . . . . . . . 40mA
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤2000V
Thermal Resistance
θJA (°C/W) θJC (°C/W)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . .
80
26
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . .
76
19
Power Dissipation (AT +75°C)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.32W
Power Dissipation Derating Factor (Above +75°C)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.5mW/°C
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.2mW/°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . .+275°C
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage (±VSUPPLY) . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V
Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4V to +VSUPPLY
Max RMS Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 4.0V, unless otherwise specified.
D.C. PARAMETERS
Input Leakage Current
SYMBOL
IIH
IIL
Source “OFF”
Leakage Current
+IS(OFF)
-IS(OFF)
Drain “OFF”
Leakage Current
+ID(OFF)
-ID(OFF)
Channel “ON”
Leakage Current
+ID(ON)
-ID(ON)
4
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
Measure inputs sequentially,
connect all unused inputs to GND
1, 2, 3
+25, +125, -55
-1.0
1.0
µA
1, 2, 3
+25, +125, -55
-1.0
1.0
µA
VS = +10V, VD = -10V, VEN = 0.8V,
All unused inputs = -10V
1
+25
-10
10
nA
2, 3
+125, -55
-50
50
nA
1
+25
-10
10
nA
2, 3
+125, -55
-50
50
nA
1
+25
-10
10
nA
HI-548/883
2, 3
+125, -55
-200
200
nA
HI-549/883
2, 3
+125, -55
-100
100
nA
1
+25
-10
10
nA
HI-548/883
2, 3
+25 to +125
-200
200
nA
HI-549/883
2, 3
+125, -55
-100
100
nA
1
+25
-10
10
nA
HI-548/883
2, 3
+125, -55
-200
200
nA
HI-549/883
2, 3
+125, -55
-100
100
nA
1
+25
-10
10
nA
HI-548/883
2, 3
+125, -55
-200
200
nA
HI-549/883
2, 3
+125, -55
-100
100
nA
CONDITIONS
VS = -10V, VD = +10V, VEN = 0.8V,
All unused inputs = +10V
VD = +10V, VEN = 0.8V,
All unused inputs = -10V
VD = -10V, VEN = 0.8V,
All unused inputs = +10V
VS = VD = +10V
All unused inputs = -10V
VS = VD = -10V
All unused inputs = +10V
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 4.0V, unless otherwise specified.
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
MAX
UNITS
ID(OFF)
Overvoltage Protected,
VS = 33V, VD = 0V, VEN = 0.8V
Leakage Current Into the
Overvoltage VS applied at ≤25% duty cycle
Drain Terminal of an “OFF”
VS = -33V, VD = 0V, VEN = 0.8V
Switch
VS applied at ≤25% duty cycle
1, 2, 3
+25, +125, -55
-2.0
2.0
µA
1, 2, 3
+25, +125, -55
-2.0
2.0
µA
Positive Supply Current
+I
VA = 0V, VEN = 4.0V
1, 2, 3
+25, +125, -55
-
2.0
mA
Negative Supply Current
-I
VA = 0V, VEN = 4.0V
1, 2, 3
+25, +125, -55
-1.0
-
mA
Standby Positive Supply
Current
+ISBY
VA = 0V, VEN = 0V
1, 2, 3
+25, +125, -55
2.0
mA
Standby Negative Supply
Current
-ISBY
VA = 0V, VEN = 0V
1, 2, 3
+25, +125, -55
--1.0
-
mA
Switch “ON” Resistance
+rDS1
VS = 10V, ID = 100µA
1
+25
-
1500
Ω
2, 3
+125, -55
-
1800
Ω
1
+25
-
1500
Ω
2, 3
+125, -55
-
1800
Ω
D.C. PARAMETERS
SYMBOL
-rDS1
Logic Level Voltage
Difference in Switch “ON”
Resistance Between
Channels
CONDITIONS
VS = -10V, ID = -100µA
VAL
Notes 1, 2
1, 2, 3
+25, +125, -55
-
0.8
V
VAH
Notes 1, 2
1, 2, 3
+25, +125, -55
4.0
-
V
+ΔrDS1
( +r DS1 MAX ) – ( +r DS1 MIN ) × 100
-------------------------------------------------------------------------------------------+r DS1 AVE
1
+25
-
7
%
-ΔrDS1
( -r DS1 MAX ) – ( -r DS1 MIN ) × 100
-----------------------------------------------------------------------------------------r DS1 AVE
1
+25
-
7
%
MAX
UNITS
TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 4.0V, unless otherwise specified.
PARAMETERS
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C)
MIN
25
Break-Before-Make Time
Delay
tD
RL = 1kΩ, CL = 12.5pF
9
+25
Propagation Delay Times:
Address Inputs to I/O
Channel Times
tA
RL = 10MΩ, CL = 14pF
9
+25
500
ns
10, 11
+125, -55
1000
ns
9
+25
500
ns
10, 11
+125, -55
1000
ns
9
+25
500
ns
10, 11
+125, -55
1000
ns
Enable to I/O
tON(EN)
tOFF(EN)
5
RL = 1kΩ, CL = 12.5pF
RL = 1kΩ, CL = 12.5pF
ns
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 4.0V,, unless otherwise specified.
PARAMETERS
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
(°C)
3
MIN
MAX
UNITS
+25
10
pF
Capacitance Address Input
CA
V+ = V- = 0V, f = 1MHz
Capacitance Output Switch
COS
V+ = V- = 0V
HI-548/883
3
+25
45
pF
f = 1MHz
HI-549/883
3
+25
25
pF
V+ = V- = 0V, f = 1MHz
3
+25
15
pF
3
+25
10
mV
3, 4
+25
Capacitance Input Switch
CIS
Charge Transfer Error
VCTE
VS = GND, VGEN = 0V to 5V, f = 200kHz
Off Isolation
VISO
VEN = 0.8V, RL = 1kΩ, CL = 15pF,
VS = 7VRMS, f = 100kHz
-50
dB
NOTES:
1. Used for forcing conditions for all DC Tests, unless otherwise specified.
2. To drive from DTL/TTL circuits, 1kΩ pull-up resistors to +5.0V supply are recommended.
3. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design release and upon design changes which would affect these characteristics.
4. Worst case isolation occurs on channel 8B due to proximity of the output pins.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-in)
Final Electrical Test Parameters
Group A Test Requirements
Groups C & D Endpoints
SUBGROUPS (See Tables 1, 2, 3)
1
1 (Note 5), 2, 3, 9, 10, 11
1, 2, 3, 9, 10, 11
1
NOTE:
5. PDA applies to Subgroup 1 only. No other subgroups are included in PDA.
6
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Test Circuits
INPUT LEAKAGE CURRENT
ID(OFF)
IS(OFF)
ID(ON)
ID(OFF) OVERVOLTAGE
RDS
SUPPLY CURRENTS
CHARGE TRANSFER ERROR
OFF CHANNEL ISOLATION
7
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Switching Waveforms
BREAK-BEFORE-MAKE DELAY (tOPEN)
BREAK-BEFORE-MAKE DELAY (tOPEN)
+15V
4V
ADDRESS
DRIVE (VA)
0V
IN 1
50Ω
A1
50%
+4V
tOPEN
VA INPUT
2V/DIV.
IN 2
THRU
IN 7
VA
OUTPUT
50%
+5V
A2
CH 1 ON
HI-548/883*
A0
IN 8
EN
OUT
GND
V-
CH 8 ON
VOUT
OUTPUT
1V/DIV.
12.5pF
1kΩ
-15V
100ns/DIV.
*SIMILAR CONNECTION FOR HI-549/883
ACCESS TIME vs LOGIC LEVEL (HIGH)
ACCESS TIME
+15V
V+
ADDRESS
DRIVE (VA)
50%
0V
50Ω
+10V
tA
CH 1 ON
A1 HI-548/883*
OUTPUT
90%
IN 2
THRU
IN 7
A2
VA
VA INPUT
2V/DIV.
±10V
IN 1
A0
IN 8
±
4.0V
10V
PROBE
-10V
+4V
EN
GND
OUT
V-
OUTPUT
5V/DIV.
10MΩ
14pF
-15V
CH 8 ON
200ns/DIV.
*SIMILAR CONNECTION FOR HI-549/883
ENABLE DELAY
tON(EN), tOFF(EN)
ENABLE DELAY
tON(EN), tOFF(EN)
ENABLE DRIVE
+15V
A2
VAH = 4V
50%
A0
OUTPUT
90%
t ON(EN)
+10V
ENABLE DRIVE
2V/DIV.
IN 2
THRU
IN 8
A1
0V
90%
IN 1
HI-548/883*
50Ω
t OFF
CH1 ON
OUT
EN
VA
GND
V-
1k
-15V
(EN)
*SIMILAR CONNECTION FOR HI-549/883
8
OUTPUT
2V/DIV.
12.5pF
CH1 OFF
100ns/DIV.
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Burn-In Circuits
HI-548/883 CERDIP
HI-548/883 CLCC
5V
5V
-15V
+15V
-15V
+15V
NOTES:
R1 = 10kΩ ± 5% 1/2W or 1/4W (per socket)
C1, C2 = 0.01µF (per socket) or 0.1µF (per row)
D1, D2 = 1N4002 (or equivalent) (per board)
NOTES:
R1 = 10kΩ ± 5% 1/2W or 1/4W (per socket)
C1, C2 = 0.01µF (per socket) or 0.1µF (per row)
D1, D2 = 1N4002 (or equivalent) (per board)
HI-549/883 CERDIP
5V
-15V
+15V
NOTES:
R1, R2 = 10kΩ ± 5% 1/2W or 1/4W (per socket)
C1, C2 = 0.01µF (per socket) or 0.1µF (per row)
D1, D2 = 1N4002 (or equivalent) (per board)
9
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Schematic Diagrams
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
TTL REFERENCE CIRCUIT
V+
R10
R9
Q1
Q4
D3
GND
LEVEL SHIFTER
V+
OVERVOLTAGE
PROTECTION
P
P
P
N
R2
P
P
P
P
R5
V+
R3
P
LEVEL
SHIFTED
ADDRESS
TO
DECODE
R7
R8
N
D1
P
R4
D2
R1
200Ω
P
N
N
R6
N
N
N
N
N
N
V-
V-
GND
ADD
IN
ADDRESS DECODER
V+
P
P
P
A0 OR A0
A1 OR A1
P
P
P
N
N
N
TO P-CHANNEL
DEVICE OF
THE SWITCH
N
N
TO N-CHANNEL
DEVICE OF
THE SWITCH
A2 OR A2
N
ENABLE
DELETE A2 OR A2 INPUT FOR HI-549/883
V-
10
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Schematic Diagrams
(Continued)
MULTIPLEX SWITCH
FROM
DECODE
OVERVOLTAGE PROTECTION
N
V+
P
R11
1k
D6
Q5
D7
D4
D5
N
IN
OUT
N
Q6
V-
P
FROM
DECODE
11
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Typical Performance Curves
1.4
100nA
125oC
1.3
LEAKAGE CURRENT
ON RESISTANCE (kΩ)
1.2
1.1
25oC
1.0
-55oC
0.9
0.8
LEAKAGE
10nA
ON LEAKAGE
CURRENT ID(ON)
1nA
OFF INPUT
LEAKAGE CURRENT
IS(OFF)
100pA
0.7
0.6
-10
-8
-6
-4
-2
0
2
4
6
8
10pA
25
10
50
ANALOG INPUT (V)
FIGURE 1. ON RESISTANCE vs ANALOG INPUT VOLTAGE
±14
12
4
9
3
6
2
OUTPUT OFF LEAKAGE
CURRENT ID(OFF)
3
15
1
18
21
24
27
30
33
ANALOG INPUT OVERVOLTAGE (±V)
125
-55oC
25oC
±12
SWITCH CURRENT (mA)
5
OUTPUT OFF LEAKAGE CURRENT (nA)
(IIN) ANALOG INPUT CURRENT (mA)
15
0
75
100
TEMPERATURE (oC)
FIGURE 2. LEAKAGE CURRENT vs TEMPERATURE
18
ANALOG INPUT
CURRENT (IIN)
OFF OUTPUT
CURRENT
ID(OFF)
±10
125oC
±8
±6
±4
±2
0
0
36
2
0
FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
4
6
8
10
12
(VIN) VOLTAGE ACROSS SWITCH (±V)
14
FIGURE 4. ON CHANNEL CURRENT vs VOLTAGE
SUPPLY CURRENT (mA)
8
6
VSUPPLY = ± 15V
4
VSUPPLY = ± 10V
2
0
1k
10k
100k
1M
10M
TOGGLE FREQUENCY (Hz)
FIGURE 5. SUPPLY CURRENT vs TOGGLE FREQUENCY
12
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Die Characteristics
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
DIE DIMENSIONS:
TRANSISTOR COUNT:
83 mils x 108 mils x 19 mils
HI-548/883 - 253
HI-549/883 - 253
METALLIZATION:
Type: Al
Thickness: 16kÅ ±2kÅ
PROCESS:
CMOS-DI
GLASSIVATION:
Type: Nitride
Thickness: 7kÅ ± 0.7kÅ
Metallization Mask Layouts
HI-548/883
IN 6
(11)
IN 7 IN 8
(10) (9)
HI-549/883
OUT
(8)
IN 4 IN 3
(7)
(6)
IN 3B IN 4B OUT B
(11) (10)
(9)
OUT A
(8)
IN 4A IN 3A
(7)
(6)
IN 5
(12)
IN 2
(5)
IN 2B
(12)
IN 2A
(5)
+V
(13)
IN 1
(4)
IN 1B
(13)
IN 1A
(4)
GND
(14)
-V
(3)
+V
(14)
-V
(3)
A2
(15)
A1
(16)
A0
(1)
EN
(2)
GND
(15)
A1
(16)
A0
(1)
EN
(2)
NOTE: Pad numbers correspond to CerDIP numbers only.
13
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
BASE
METAL
E
M
-Bbbb S
C A-B S
(c)
Q
-C-
SEATING
PLANE
S1
b2
b
C A-B S
eA/2
NOTES
-
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
c
aaa M C A - B S D S
D S
MAX
0.014
eA
e
MIN
b
α
A A
MILLIMETERS
MAX
A
A
L
MIN
M
(b)
SECTION A-A
D S
INCHES
SYMBOL
b1
D
BASE
PLANE
ccc M
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
16
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN8256.0
April 9, 2012
HI-548/883, HI-549/883
Ceramic Leadless Chip Carrier Packages (CLCC)
J20.A
MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
0.010 S E H S
D
INCHES
D3
SYMBOL
j x 45o
E3
B
E
h x 45o
0.010 S E F S
A
PLANE 2
PLANE 1
-E-
e
-H-
L3
0.100
1.52
2.54
6, 7
0.088
1.27
2.23
-
B
-
-
-
-
-
B1
0.022
0.028
0.56
0.71
2, 4
B2
0.072 REF
1.83 REF
-
B3
0.006
0.022
0.15
0.56
-
D
0.342
0.358
8.69
9.09
-
D1
0.200 BSC
5.08 BSC
D2
0.100 BSC
2.54 BSC
D3
-
0.358
-
E
0.342
0.358
8.69
0.200 BSC
E2
0.100 BSC
E3
-
e
0.358
0.050 BSC
0.015
-
0.040 REF
0.020 REF
-
9.09
2
9.09
-
5.08 BSC
-
2.54 BSC
-
-
9.09
2
1.27 BSC
0.38
-
2
1.02 REF
5
0.51 REF
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.91
2.41
-
L3
0.003
0.015
0.08
0.38
-
ND
5
5
NE
5
5
3
N
20
20
3
-F-
3
Rev. 0 5/18/94
B3
E1
E2
NOTES
0.060
j
L
MAX
0.050
h
B1
MIN
A
e1
0.007 M E F S H S
MILLIMETERS
MAX
A1
E1
A1
MIN
L2
B2
L1
D2
e1
D1
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
15
FN8256.0
April 9, 2012
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