IRFSL9N60A, SiHFSL9N60A Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Halogen-free According to IEC 61249-2-21 Definition • Low Gate Charge Qg Results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness • Fully Characterized Capacitance and Avalanche Voltage and Current • Compliant to RoHS Directive 2002/95/EC 600 RDS(on) () VGS = 10 V Qg (Max.) (nC) 0.75 49 Qgs (nC) 13 Qgd (nC) 20 Configuration Single D I2PAK (TO-262) APPLICATIONS • • • • G S D G Switch Mode Power Supply (SMPS) Uninterruptable Power Supply High Speed Power Switching This Device is only for Through Hole Application APPLICABLE OFF LINE SMPS TOPOLOGIES S N-Channel MOSFET • Active Clamped Forward • Main Switch ORDERING INFORMATION I2PAK (TO-262) SiHFSL9N60A-GE3 IRFSL9N60APbF SiHFSL9N60A-E3 Package Lead (Pb)-free and Halogen-free Lead (Pb)-free ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID UNIT V 9.2 5.8 A IDM 37 1.3 W/°C EAS 290 mJ Currenta IAR 9.2 A Repetitive Avalanche Energya EAR 17 mJ Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s PD 170 W dV/dt 5.0 V/ns TJ, Tstg - 55 to + 150 300d °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 6.8 mH, Rg = 25 , IAS = 9.2 A (see fig. 12). c. ISD 9.2 A, dI/dt 50 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 90362 S11-1045-Rev. C, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFSL9N60A, SiHFSL9N60A Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB Mounted, steady-state) RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 0.75 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT V Static VDS VGS = 0, ID = 250 μA 600 - - VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 600 V, VGS = 0 V - - 25 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 250 Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 5.5 Ab μA - - 0.75 5.5 - - S - 1400 - - 180 - - 7.1 - VDS = 1.0 V, f = 1.0 MHz - 1957 - VDS = 480 V, f = 1.0 MHz - 49 - - 96 - - - 49 - - 13 VGS = 10 V VDS = 25 V, ID = 3.1 Ab Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Output Capacitance Coss Effective Output Capacitance VGS = 0 V VDS = 25 V f = 1.0 MHz, see fig. 5 VGS = 0 V Coss eff. Total Gate Charge Qg Gate-Source Charge Qgs VDS = 0 V to 480 VGS = 10 V Vc ID = 9.2 A, VDS = 400 V see fig. 6 and 13b pF nC Gate-Drain Charge Qgd - - 20 Turn-On Delay Time td(on) - 13 - - 25 - - 30 - - 22 - - - 9.2 - - 37 - - 1.5 - 530 800 ns - 3.0 4.4 μC Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 300 V, ID = 9.2 A Rg = 9.1 , RD = 35.5 , see fig. 10b tf ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 9.2 A, VGS = 0 Vb TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μsb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. c. COSS eff. is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 80% VDS. www.vishay.com 2 Document Number: 90362 S11-1045-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFSL9N60A, SiHFSL9N60A Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.7V I D , Drain-to-Source Current (A) 10 1 4.7V 20µs PULSE WIDTH TJ = 25 °C 0.1 0.1 100 1 10 100 TJ = 150 ° C TJ = 25 ° C 1 0.1 4.0 V DS = 50V 20µs PULSE WIDTH 5.0 6.0 7.0 8.0 9.0 VDS , Drain-to-Source Voltage (V) VGS , Gate-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics 3.0 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.7V TOP I D , Drain-to-Source Current (A) 10 10 4.7V 20µs PULSE WIDTH TJ = 150 °C 1 1 10 VDS , Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics Document Number: 90362 S11-1045-Rev. C, 30-May-11 100 RDS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) TOP 10.0 ID = 9.2A 2.5 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 TJ , Junction Temperature ( °C) Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFSL9N60A, SiHFSL9N60A Vishay Siliconix V GS C is s C rss C o ss C , Capacitance (pF ) 2000 = = = = 100 0V, f = 1M H z C g s + C g d , Cd s S H O R TE D C gd C ds + C gd ISD , Reverse Drain Current (A) 2400 C iss 1600 C oss 1200 800 C rss 400 0 10 TJ = 150 ° C 1 TJ = 25 ° C 0.1 0.2 A 1 10 100 1000 1.0 1.2 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 1000 ID = 9.2A OPERATION IN THIS AREA LIMITED BY RDS(on) 400V VDS = 480V VDS = 300V VDS = 120V 16 100 I D , Drain Current (A) VGS , Gate-to-Source Voltage (V) 0.7 VSD ,Source-to-Drain Voltage (V) V D S , D rain-to-S ource V olta ge (V ) 20 V GS = 0 V 0.5 12 8 10us 10 100us 1ms 1 10ms 4 FOR TEST CIRCUIT SEE FIGURE 13 0 0 10 20 30 40 50 Q G , Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 0.1 TC = 25 ° C TJ = 150 ° C Single Pulse 10 100 1000 10000 VDS , Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area Document Number: 90362 S11-1045-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFSL9N60A, SiHFSL9N60A Vishay Siliconix RD VDS 10.0 VGS D.U.T. Rg + - VDD I D , Drain Current (A) 8.0 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 6.0 Fig. 10a - Switching Time Test Circuit 4.0 VDS 90 % 2.0 0.0 25 50 75 100 TC , Case Temperature 125 10 % VGS 150 ( °C) td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (Z thJC ) 1 D = 0.50 0.20 0.1 0.10 P DM 0.05 t1 0.02 0.01 0.01 0.00001 t2 SINGLE PULSE (THERMAL RESPONSE) 0.0001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 90362 S11-1045-Rev. C, 30-May-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFSL9N60A, SiHFSL9N60A Vishay Siliconix VDS tp 15 V Driver L VDS Rg D.U.T. + A - VDD IAS 20 V tp IAS A 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms EAS , Single Pulse Avalanche Energy (mJ) 600 ID 4.1A 5.8A 9.2A TOP 500 BOTTOM 400 300 200 100 0 25 50 75 100 125 150 Starting TJ , Junction Temperature ( °C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 90362 S11-1045-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFSL9N60A, SiHFSL9N60A Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?90362. Document Number: 90362 S11-1045-Rev. C, 30-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000