DATASHEET

82C82
CMOS Octal Latching Bus Driver
August 25, 2015
Features
Description
• Full Eight-Bit Parallel Latching Buffer
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this signal. The active low output enable (OE) permits simple interface to state-of-the-art microprocessor systems.
• Bipolar 8282 Compatible
• Three-State Noninverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10A
• Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Pinouts
DI1
DI0
VCC
DO0
2
1
20
19
20 VCC
DI1
2
19 DO0
DI2
3
18 DO1
DI3
4
17 DO2
DI4
5
16 DO3
DI5 6
DI5
6
15 DO4
DI6 7
O
DI7 8 N
13 DO6
OE
9
12 DO7
GND 10
11 STB
N
LE
O
PP
TRUTH TABLE
ED
RT
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
STB
OE
DI
DO
Hi-Z
X
H
X
H
L
L
L
H
L
H
H

L
X
†
H
L
X
†
= Logic One
= Logic Zero
= Don’t Care
= Latched to Value of Last
Data
Hi-Z = High Impedance

= Neg. Transition
PIN NAMES
9
10
11
12
13
DO6
14 DO5
8
LO
R
GE
B
LA
AI
AV
SU
DO7
7
DI7
DI4 5
OR
STB
DI6
DI3 4
GND
1
3
OE
DI0
82C82 (PLCC, CLCC)
TOP VIEW
DI2
82C82 (PDIP, CERDIP)
TOP VIEW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2002, 2015. All Rights Reserved
274
PIN
DESCRIPTION
DI0-DI7
Data Input Pins
DO0-DO7
Data Output Pins
STB
Active High Strobe
OE
Active Low Output
Enable
FN2975.2
82C82
Ordering Information
PART NUMBER
TEMP. RANGE
PACKAGE
0oC to +70oC
CP82C82
(No longer available)
IP82C82 (No longer available)
-40oC to +85oC
CS82C82 (No longer available)
0oC to +70oC
IS82C82 (No longer available)
-40oC to +85oC
CD82C82 (No longer available)
0oC to +70oC
ID82C82 (No longer available)
-40oC to +85oC
MD82C82/B (No longer available)
-55oC to +125oC
8406701RA
PKG. NO.
20 Ld PDIP
E20.3
20 Ld PLCC
N20.35
20 Ld CERDIP
F20.3
SMD #
-55oC to +125oC
MR82C82/B (No longer available)
20 Pad CLCC
84067012A(No longer available)
J20.A
SMD #
Functional Diagram
DIO
D Q
CLK
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
STB
OE
Gated Inputs
During normal system operation of a latch, signals on the bus
at the device inputs will become high impedance or make
transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically
cause an increase in power dissipation in CMOS devices by
creating a low resistance path between VCC and GND when
the signal is at or near the input switching threshold. Additionally, if the driving signal becomes high impedance (“float” condition), it could create an indeterminate logic state at the input
and cause a disruption in device operation.
GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held
to a valid logic level internal to the device.
The Intersil 82C8X Series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disabled
(OE = logic one for 82C86H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power
supply pins by turning off the upper P-channel and lower Nchannel (see Figures 1, 2). No new current flow from VCC to
275
82C82
DC input voltage levels can also cause an increase in ICC if
these input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the input circuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the trans
parent mode (STB = logic one). ICC remains below the maximum ICC standby specification of l0mA during the time
inputs are disabled, thereby, greatly reducing the average
power dissipation of the 82C8X series devices
Typical 82C82 System Example
In a typical 80C86/88 system, the 82C82 is used to latch
multiplexed addresses and the STB input is driven by ALE
(Address Latch Enable) (see Figure 3). The high pulse width
of ALE is approximately 100ns with a bus cycle time of
800ns (80C86/88 at 5MHz). The 82C82 inputs are active
only 12.5% of the bus cycle time. Average power dissipation
related to input transitioning is reduced by this factor also.
VCC
VCC
VCC
P
P
P
STB
N
OE
P
DATA IN
INTERNAL
DATA
DATA IN
P
INTERNAL
DATA
VCC
P
N
N
N
N
N
FIGURE 16. 82C82/83H
FIGURE 17. 82C86H/87H GATED INPUTS
Application Information
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C82 data sheet is
276
82C82
where tR = 20ns, VCC = 5.0V, CL = 300pF on each of eight
outputs.
determined by:
I = C L (dv/dt)
(EQ. 1)
Assuming that all outputs change state at the same time and
that dv/dt is constant;
I = CL
(EQ. 2)
 V CC x 80% 
----------------------------------tR/tF
(EQ. 3)
I =  8 x 300 x 10
-12
x (5.0V x 0.8)/  20 x 10
–9
 = 480mA
(EQ. 4)
This current spike may cause a large negative voltage spike
on VCC, which could cause improper operation of the
device. To filter out this noise, it is recommended that a
0.1F ceramic disc decoupling capacitor be placed between
VCC and GND at each device, with placement being as near
VCC
VCC
P
P
ALE
MULTIPLEXED
BUS
N
STB
ADDRESS
ADDRESS
P
INTERNAL
DATA
DATA IN
N
ICC
N
FIGURE 18. SYSTEM EFFECTS OF GATED INPUTS
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
M82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
JA
JC
CERDIP . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W
18oC/W
CLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 85oC/W
22oC/W
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . .
75
N/A
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Minimum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
(PLCC Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5.0V 10%;
SYMBOL
VIH
VIL
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
TA = 0oC to +70oC (C82C82);
TA = -40oC to +85oC (I82C82);
TA = -55oC to +125oC (M82C82)
MIN
MAX
UNITS
2.0
-
V
C82C82, I82C82 (Note 1)
2.2
-
V
M82C82 (Note 1)
-
0.8
V
277
TEST CONDITIONS
82C82
DC Electrical Specifications VCC = 5.0V 10%;
TA = 0oC to +70oC (C82C82);
TA = -40oC to +85oC (I82C82);
TA = -55oC to +125oC (M82C82)
SYMBOL
PARAMETER
MIN
MAX
UNITS
VOH
Logical One Output Voltage
2.9
-
V
IOH = -8mA, OE = GND
VCC -0.4V
-
V
IOH = -100A, OE = GND
-
0.4
V
IOL = 8mA, OE = GND
VOL
Logical Zero Output Voltage
TEST CONDITIONS
II
Input Leakage Current
-1.0
1.0
A
VIN = GND or VCC, DIP Pins 1-9, 11
IO
Output Leakage Current
-10.0
10.0
A
VO = GND or VCC, OE  VCC -0.5V
DIP Pins 12-19
VIN = VCC or GND, VCC = 5.5V, Outputs Open
ICCSB
Standby Power Supply Current
-
10
A
ICCOP
Operating Power Supply
Current
-
1
mA/MHz
TA = +25oC, VCC = 5V, Typical (See Note 2)
NOTES:
1. VIH is measured by applying a pulse of magnitude = VIH min to one data input at a time and checking the corresponding device output
for a valid logical “1” during valid input high time. Control pins (STB, OE) are tested separately with all device data input pins at VCC -0.4.
2. Typical ICCOP = 1mA/MHz of STB cycle time. (Example: 5MHz P, ALE = 1.25MHz, ICCOP = 1.25mA).
Capacitance
SYMBOL
TA = +25oC
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
Freq = 1MHz, all measurements are
referenced to device GND
CIN
Input Capacitance
13
pF
COUT
Output Capacitance
20
pF
TA = 0oC to +70oC (C82C82);
CL = 300pF (Note 1), Freq = 1MHz TA = -40oC to +85oC (I82C82);
TA = -55oC to +125oC (M82C82)
AC Electrical Specifications VCC = 5.0V 10%;
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
(1)
TIVOV
Propagation Delay Input to Output
-
35
ns
Notes 2, 3
(2)
TSHOV
Propagation Delay STB to Output
-
55
ns
Notes 2, 3
(3)
TEHOZ
Output Disable Time
-
35
ns
Notes 2, 3
(4)
TELOV
Output Enable Time
-
50
ns
Notes 2, 3
(5)
TIVSL
Input to STB Setup Time
0
-
ns
Notes 2, 3
(6)
TSLIX
Input to STB Hold Time
25
-
ns
Notes 2, 3
(7)
TSHSL
STB High Time
25
-
ns
Notes 2, 3
(8)
TR, TF
Input Rise/Fall Times
-
20
ns
Notes 2, 3
NOTES:
1. Output load capacitance is rated at 300pF for ceramic and plastic packages.
2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V.
3. Input test signals must switch between VIL - 0.4V and VIH +0.4V.
278
82C82
Timing Waveforms
TR, TF (8)
2.0V
0.8V
INPUTS
TIVSL (5)
TSLIX
(6)
STB
TSHSL (7)
OE
TIVOV
(1)
TELOV (4)
TEHOZ (3)
VOH -0.1V
OUTPUTS
2.4V
0.8V
VOL +0.1V
TSHOV (2)
Test Load Circuits
1.7V
150
OUTPUT
0.6V
3.3V
300
TEST
POINT
OUTPUT
300
TEST
POINT
OUTPUT
50pF
(NOTE)
300pF
(NOTE)
TIVOV, TSHOV, TELOV
50pF
(NOTE)
TEHOZ OUTPUT HIGH DISABLE
TEHOZ OUTPUT LOW DISABLE
NOTE: Includes stray and jig capacitance.
Burn-In Circuits
MD82C82 CERDIP
VCC
F2
F2
F2
F2
F2
F2
F2
F2
F0
R1
R1
R1
R1
R1
R1
R1
R1
R1
1
TEST
POINT
C1
20
2
19
A
3
18
A
4
17
A
5
16
A
6
15
A
7
14
A
8
13
A
9
12
10
11
279
R1
VCC
R2
A
A
F1
R2
82C82
Burn-In Circuits
MR82C82 CLCC
C1
VCC
F2
F2
R3
3
F2
F2
F2
F2
F2
R3
R3
R3
R3
R3
VCC/2
F2
R3
2
R3
R3
1
20
19
18
4
5
17
16
6
15
7
14
8
9
10
R3
F0
11
12
R3
R3
R3
R3
R3
R3
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
13
R3
R3
F1 VCC/2 VCC/2
NOTES:
1. VCC = 5.5 0.5V, GND = 0V.
2. VIH = 4.5V 10%.
3. VIL = -0.2V to 0.4V.
4. R1 = 47k 5%.
5. R2 = 2.0k 5%.
6. R3 = 4.2k 5%.
7. R4 = 470k 5%.
8. C1 = 0.01F minimum.
9. F0 = 100kHz 10%.
10. F1 = F0/2, F2 = F1/2.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
280
82C82
Die Characteristics
DIE DIMENSIONS:
118.1 x 92.1 x 19 1mils
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ 1kÅ
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ 1kÅ
WORST CASE CURRENT DENSITY:
2.00 x 105 A/cm2
Metallization Mask Layout
82C82
D12
D11
D10
VCC
DO0
D01
2
1
20
19
18
3
D13
4
D14
5
D15
6
D16
7
8
9
10
11
12
D17
OE
GND
STB
DO7
281
17
DO2
16
DO3
15
DO4
14
DO5
13
DO6
82C82
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to
make sure that you have the latest revision.
DATE
REVISION
August 25, 2015
FN2975.2
CHANGE
- Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
About Intersil
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products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end
consumer markets.
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282
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