DATASHEET

82C88
Data Sheet
August 13, 2015
FN2979.3
CMOS Bus Controller
Features
The Intersil 82C88 is a high performance CMOS Bus
Controller manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C88 provides the
control and command timing signals for 80C86, 80C88,
8086, 8088, 8089, 80186, and 80188 based systems. The
high output drive capability of the 82C88 eliminates the need
for additional bus drivers.
• Compatible with Bipolar 8288
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
• Provides Advanced Commands for Multi-Master Busses
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
- 80186/80188. . . . . . . . . . . . . . . . . . . . . . . . . . (6/8MHz)
- 8086/8088. . . . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
- 8089
• Three-State Command Outputs
• Bipolar Drive Capability
• Scaled SAJI IV CMOS Process
Pinouts
• Single 5V Power Supply
20 LD PDIP, CERDIP
TOP VIEW
IOB
1
20 VCC
CLK
2
19 S0
S1
3
18 S2
DT/ R
4
17 MCE/PDEN
ALE
5
16 DEN
AEN
6
15 CEN
MRDC
7
14 INTA
AMWC
8
13 IORC
MWTC
9
12 AIOWC
11 IOWC
GND 10
S1
CLK
IOB
VCC
S0
20 LD PLCC, CLCC
TOP VIEW
3
2
1
20
19
• Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10A (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz (Max)
• Operating Temperature Ranges
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
TEMP
RANGE
(°C)
PKG.
DWG. #
CP82C88Z (Note) (No CP82C88Z 20 Ld PDIP
(Pb-free)
longer available or
supported)
0 to +70
E20.3
CS82C88
CS82C88
(No longer available
or supported)
0 to +70
N20.35
PART NUMBER
PART
MARKING PACKAGE
20 Ld
PLCC
MR82C88/B
No longer available
or supported)
MR82C88/B 20 Pad
CLCC
-55 to +125 J20.A
MD82C88/B
MD82C88/B 20 Ld
CERDIP
-55 to +125 F20.3
8406901RA SMD#
17 MCE/PDEN
AEN
6
16 DEN
8406901RA
MRDC
7
15 CEN
8
14 INTA
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
AMWC
9
10
11
12
13
IORC
5
AIOWC
ALE
IOWC
18 S2
GND
4
MWTC
DT/ R
1
F20.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas LLC 2002, 2005, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
82C88
Functional Diagram
S0
S1
STATUS
DECODER
S2
COMMAND
SIGNAL
GENERATOR
MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
MULTIBUSTM
COMMAND
SIGNALS
INTA
DT/R
CLK
CONTROL
INPUT
AEN
CEN
CONTROL
LOGIC
CONTROL
SIGNAL
GENERATOR
DEN
MCE/PDEN
ALE
IOB
VCC
ADDRESS LATCH,
DATA TRANSCEIVER,
AND INTERRUPT
CONTROL SIGNALS
GND
Pin Description
PIN
SYMBOL
NUMBER
VCC
20
VCC: The +5V power supply pin. A 0.1F capacitor between pins 10 and 20 is recommended for decoupling.
GND
10
GROUND.
S0, S1, S2
19, 3, 18
I
STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The
82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins
are not in use (passive), command outputs are held HIGH (See Table1).
CLK
2
I
CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock
generator and serves to establish when command/control signals are generated.
ALE
5
O
ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is
active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent
D type latches, such as the 82C82 and 82C83H.
DEN
16
O
DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This
signal is active HIGH.
DT/R
4
O
DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH
on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory).
AEN
6
I
ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns
maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output
drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH).
CEN
15
I
COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control
outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.
IOB
1
I
INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode.
When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections).
AIOWC
12
O
ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine cycle to
give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal.
AIOWC is active LOW.
IOWC
11
O
I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The signal
is active LOW.
IORC
13
O
I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This signal
is active LOW.
TYPE
DESCRIPTION
2
FN2979.3
August 13, 2015
82C88
Pin Description
(Continued)
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
AMWC
8
O
ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the machine
cycle to give memory devices an early indication of a write instruction. Its timing is the same as a read command
signal. AMWC is active LOW.
MWTC
9
O
MEMORY WRITE COMMAND: This command line instructs the memory to record the data present on the data
bus. This signal is active LOW.
MRDC
7
O
MEMORY READ COMMAND: This command line instructs the memory to drive its data onto the data bus. MRDC
is active LOW.
INTA
14
O
INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its interrupt has been
acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW.
MCE/PDEN
17
O
This is a dual function pin. MCE (IOB IS TIED LOW) Master Cascade Enable occurs during an interrupt sequence
and serves to read a Cascade Address from a master 82C59A Priority Interrupt Controller onto the data bus. The
MCE signal is active HIGH. PDEN (IOB IS TIED HIGH): Peripheral Data Enable enables the data bus transceiver
for the I/O bus that DEN performs for the system bus. PDEN is active LOW.
Functional Description
System Bus Mode
The command logic decodes the three 80C86, 8086, 80C88,
8088, 80186, 80188 or 8089 status lines (S0, S1, S2) to
determine what command is to be issued (see Table 1).
The 82C88 is in the System Bus mode if the IOB pin is
strapped LOW. In this mode, no command is issued until a
specified time period after the AEN line is activated (LOW).
This mode assumes bus arbitration logic will inform the bus
controller (on the AEN line) when the bus is free for use.
Both memory and I/O commands wait for bus arbitration.
This mode is used when only one bus exists. Here, both I/O
and memory are shared by more than one processor.
TABLE 1. COMMAND DECODE DEFINITION
PROCESSOR STATE
82C88
COMMAND
S2
S1
S0
0
0
0
Interrupt Acknowledge
INTA
0
0
1
Read I/O Port
IORC
0
1
0
Write I/O Port
IOWC, AIOWC
0
1
1
Halt
None
1
0
0
Code Access
MRDC
1
0
1
Read Memory
MRDC
1
1
0
Write Memory
MWTC, AMWC
INTA (Interrupt Acknowledge) acts as an I/O read during an
interrupt cycle. Its purpose is to inform an interrupting device
that its interrupt is being acknowledged and that it should
place vectoring information onto the data bus.
1
1
1
Passive
None
The command outputs are:
Command Outputs
The advanced write commands are made available to initiate
write procedures early in the machine cycle. This signal can
be used to prevent the processor from entering an
unnecessary wait state.
MRDC - Memory Read Command
I/O Bus Mode
The 82C88 is in the I/O Bus mode if the IOB pin is strapped
HIGH. In the I/O Bus mode, all I/O command lines IORC,
IOWC, AIOWC, INTA) are always enabled (i.e., not
dependent on AEN). When an I/O command is initiated by
the processor, the 82C88 immediately activates the
command lines using PDEN and DT/R to control the I/O bus
transceiver. The I/O command lines should not be used to
control the system bus in this configuration because no
arbitration is present. This mode allows one 82C88 Bus
Controller to handle two external busses. No waiting is
involved when the CPU wants to gain access to the I/O bus.
Normal memory access requires a “Bus Ready” signal (AEN
LOW) before it will proceed. It is advantageous to use the
IOB mode if I/O or peripherals dedicated to one processor
exist in a multi-processor system.
3
MWTC - Memory Write Command
IORC - I/O Read Command
IOWC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced I/O Write Command
INTA - Interrupt Acknowledge
Control Outputs
The control outputs of the 82C88 are Data Enable (DEN),
Data Transmit/Receive (DT/R) and Master Cascade Enable/
Peripheral Data Enable (MCE/PDEN). The DEN signal
determines when the external bus should be enabled onto
the local bus and the DT/R determines the direction of data
FN2979.3
August 13, 2015
82C88
transfer. These two signals usually go to the chip select and
direction pins of a transceiver.
The MCE/PDEN pin changes function with the two modes of
the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),
the PDEN signal serves as a dedicated data enable signal
for the I/O or Peripheral System bus.
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt acknowledge
cycle if the 82C88 is in the System Bus mode (IOB LOW).
During any interrupt sequence, there are two interrupt
acknowledge cycles that occur back to back. During the first
interrupt cycle no data or address transfers take place. Logic
should be provided to mask off MCE during this cycle. Just
before the second cycle begins the MCE signal gates a
master Priority Interrupt Controller’s (PIC) cascade address
onto the processor’s local bus where ALE (Address Latch
Enable) strobes it into the address latches. On the leading
edge of the second interrupt cycle, the addressed slave PIC
gates an interrupt vector onto the system data bus where it is
read by the processor.
If the system contains only one PIC, the MCE signal is not
used. In this case, the second Interrupt Acknowledge signal
gates the interrupt vector onto the processor bus.
Address Latch Enable and Halt
Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address into the
82C82/82C83H address latches. ALE also serves to strobe
the status (S0, S1, S2) into a latch for halt state decoding.
Command Enable
The Command Enable (CEN) input acts as a command
qualifier for the 82C88. If the CEN pin is high, the 82C88
functions normally. If the CEN pin is pulled LOW, all
command lines are held in their inactive state (not threestate). This feature can be used to implement memory
partitioning and to eliminate address conflicts between
system bus devices and resident bus devices.
4
FN2979.3
August 13, 2015
82C88
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
CERDIP Package. . . . . . . . . . . . . . . .
75
18
CLCC Package . . . . . . . . . . . . . . . . .
85
22
PDIP Package . . . . . . . . . . . . . . . . . .
75
N/A
PLCC Package. . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(PLCC - Lead Tips Only)
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
M82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5.0V 10%;
TA = 0°C to +70°C (C82C88);
TA = -40°C to +85°C (I82C88);
TA = -55°C to +125°C (M82C88)
SYMBOL
PARAMETER
MIN
MAX
UNITS
VIH
Logical One Input Voltage
2.0
2.2
-
V
V
VIL
Logical Zero Input Voltage
-
0.8
V
TEST CONDITIONS
C82C88, I82C88
M82C88
VIHC
CLK Logical One Input Voltage
VCC -0.8
-
V
VILC
CLK Logical Zero Input Voltage
-
0.8
V
VOH
Output High Voltage
Command Outputs
3.0
VCC -0.4
-
V
V
IOH = -8.0mA
IOH = -2.5mA
Output High Voltage
Control Outputs
3.0
VCC -0.4
-
V
V
IOH = -4.0mA
IOH = -2.5mA
Output Low Voltage
Command Outputs
-
0.5
V
IOL= +12.0mA
Output Low Voltage
Control Outputs
-
0.4
V
IOL = +8.0mA
Input Leakage Current
-1.0
1.0
A
VIN = GND or VCC, except S0, S1, S2,
DIP Pins 1-2, 6, 15
Input Leakage Current-Status Bus
-50
-300
A
VIN = 2.0V, S0, S1, S2 (See Note 1)
-10.0
10.0
A
VO = GND or VCC, IOB = GND, AEN = VCC,
DIP Pins 7-9, 11-14
VCC = 5.5V, VIN = VCC or GND, Outputs Open
VOL
II
IBHH
IO
Output Leakage Current
ICCSB
Standby Power Supply
-
10
A
ICCOP
Operating Power Supply Current
-
1
mA/MHz
VCC = 5.5V, Outputs Open (See Note 2)
NOTES:
1. IBHH should be measured after raising the VIN on S0, S1, S2 to VCC and then lowering to valid input high level of 2.0V.
2. ICCOP = 1mA/MHz of CLK cycle time (TCLCL)
Capacitance TA = +25°C
SYMBOL
CIN
COUT
PARAMETER
TYPICAL
UNITS
Input Capacitance
10
pF
Output Capacitance
17
pF
5
TEST CONDITIONS
FREQ = 1MHz, all measurements are
referenced to device GND
FN2979.3
August 13, 2015
82C88
AC Electrical Specifications
VCC = 5.0V 10%;
TA = 0°C to +70°C (C82C88);
TA = -40°C to +85°C (I82C88);
TA = -55°C to +125°C (M82C88)
8MHz
SYMBOL
PARAMETER
10MHz
12MHz
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
TEST
CONDITIONS
TIMING REQUIREMENTS
(1) TCLCL
CLK Cycle Period
125
-
100
-
83
-
ns
(2) TCLCH
CLK Low Time
55
-
50
-
34
-
ns
(3) TCHCL
CLK High Time
40
-
37
-
34
-
ns
(4) TSVCH
Status Active Setup Time
35
-
35
-
35
-
ns
(5) TCHSV
Status Inactive Hold Time
10
-
10
-
5
-
ns
(6) TSHCL
Status Inactive Setup Time
35
-
35
-
35
-
ns
(7) TCLSH
Status Active Hold Time
10
-
10
-
5
-
ns
TIMING RESPONSES
(8) TCVNV
Control Active Delay
5
45
5
45
5
45
ns
1
(9) TCVNX
Control Inactive Delay
10
45
10
45
10
35
ns
1
(10) TCLLH
ALE Active Delay (from CLK)
-
20
-
20
-
20
ns
1
(11) TCLMCH
MCE Active Delay (from CLK)
-
25
-
23
-
23
ns
1
(12) TSVLH
ALE Active Delay (from Status)
-
20
-
20
-
20
ns
1
(13) TSVMCH
MCE Active Delay (from Status)
-
30
-
23
-
23
ns
1
(14) TCHLL
ALE Inactive Delay
4
18
4
18
4
18
ns
1
(15) TCLML
Command Active Delay
5
35
5
35
5
35
ns
2
(16) TCLMH
Command Inactive Delay
5
35
5
35
5
35
ns
2
(17) TCHDTL
Direction Control Active Delay
-
50
-
50
-
50
ns
1
(18) TCHDTH
Direction Control Inactive Delay
-
30
-
30
-
30
ns
1
(19) TAELCH
Command Enable Time (Note 1)
-
40
-
40
-
40
ns
3
(20) TAEHCZ
Command Disable Time
(Note 2)
-
40
-
40
-
40
ns
4
(21) TAELCV
Enable Delay Time
110
250
110
250
110
250
ns
2
(22) TAEVNV
AEN to DEN
-
25
-
25
-
25
ns
1
(23) TCEVNV
CEN to DEN, PDEN
-
25
-
25
-
25
ns
1
(24) TCELRH
CEN to Command
-
TCLML
+10
-
TCLML
-
TCLML
ns
2
(25) TLHLL
ALE High Time
TCLCH 10
-
TCLCH 10
-
TCLCH 10
n
ns
1
NOTES:
1. TAELCH measurement is between 1.5V and 2.5V.
2. TAEHCZ measured at 0.5V change in VOUT.
6
FN2979.3
August 13, 2015
82C88
AC Testing Input, Output Waveform
INPUT
VIH +0.4V
OUTPUT
VOH
1.5V
1.5V
VIL -0.4V
VOL
A.C. Testing: All input signals (other than CLK) must switch
between VIL -0.4V and VIH +0.4. CLK must switch between 0.4V
and VCC -0.4V. Input rise and fall times are driven at 1ns/V.
A.C. Test Circuit
V1
R1
OUTPUT FROM
DEVICE
UNDER TEST
TEST
POINT
C1 (SEE NOTE)
NOTE:
INCLUDES STRAY AND JIG CAPACITANCE
TABLE 2. TEST CONDITION DEFINITION TABLE
TEST CONDITION
V1
R1
C1
1
2.13V
220
80pF
2
2.29V
91
300pF
3
1.5V
187
300pF
4
1.5V
187
50pF
7
FN2979.3
August 13, 2015
82C88
Timing Waveforms (Note 3)
STATE
T4
T1
T2
TCLCL
(1)
T4
TCLCH
(2)
CLK
TCHSV
(5)
T3
TSVCH
(4)
TCHCL
(3)
TSHCL
(6)
TCLSH
(7)
S2, S1, S0
ADDRESS
VALID
ADDRESS/DATA
WRITE
1
DATA VALID
TCHLL (14)
TCLLH
(10)
TSVLH (12)
2
ALE
TCLMH
(16)
MRDC, IORC, INTA,
AMWC, AIOWC
TCLML
(15)
TCLML
(15)
MWTC, IOWC
TCVNV
(8)
DEN (READ)
(INTA)
TCVNX
(9)
PDEN (READ)
(INTA)
TCVNV
(8)
DEN (WRITE)
TCVNX
(9)
PDEN (WRITE)
TCHDTH
(18)
DT/R (READ)
(INTA)
TCHDTL
(17)
TCHDTH
(18)
2
MCE
TCLMCH
(11)
NOTES:
TSVMCH
(13)
TCVNX
(9)
1. Address/Data Bus is shown only for reference purposes.
2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.
3. All timing measurements are made at 1.5V unless otherwise specified.
FIGURE 1.
8
FN2979.3
August 13, 2015
82C88
Timing Waveforms (Note 3)
(Continued)
CEN
AEN
TAEVNV (22)
DEN
TCEVNV (23)
PDEN
FIGURE 2. DEN, PDEN QUALIFICATION TIMING
TAELCV
(21)
AEN
1.5V
1.5V
TAELCH (19)
VOH
TAEHCZ (20)
0.5V VOH
OUTPUT
COMMAND
TCELRH
(24)
CEN
TCELRH (24)
CEN MUST BE LOW OR INVALID PRIOR TO T2 TO PREVENT THE COMMAND FROM BEING GENERATED.
FIGURE 3. ADDRESS ENABLE (AEN) TIMING (THREE-STATE ENABLE/DISABLE)
NOTES:
1. Address/Data Bus is shown only for reference purposes.
2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.
3. All timing measurements are made at 1.5V unless otherwise specified.
9
FN2979.3
August 13, 2015
82C88
Burn-In Circuits
MD82C88 CERDIP
R1
20
1
F7
R1
2
F0
R2
19
F3
3
18
A
4
17
5
16
A
R1
R2
VCC
F4
R2
F2
A
A
R1
F5
6
15
A
7
14
A
A
8
13
A
A
9
12
A
VCC
10
11
A
F6
VCC
R3
A
R3
C1
MR82C88 CLCC
F3
F0
R4 R1
3
VCC/ 2
VCC/ 2
F5
VCC/ 2
VCC/ 2
R4
2
F7 VCC F4
R1
1
R4
20
19
18
4
R4
R1
R4
R4
5
17
6
16
7
15
8
14
R2
R4
R4
R1
9
10
R4
11
12
R4
F2
VCC/ 2
VCC/ 2
F6
VCC/ 2
13
R4 R4 R4
C1
VCC
VCC/ 2
VCC/ 2
NOTES:
1. VCC = 5.5V  0.5V
GND = 0V
2. VIH = 4.5V  10%
VIL = -0.2V to +0.4V
3. Component Values:
R1 = 47k, 1/4W, 5%
R2 = 1.5k, 1/4W, 5%
R3 = 10k, 1/4W, 5%
R4 = 1.2k, 1/4W, 5%
C1 = 0.01F (Min)
F0 = 100kHz  10%
F1 = F0/2
F2 = F1/2 . . . F7 = F6/2
10
FN2979.3
August 13, 2015
82C88
Die Characteristics
Glassivation:
Type: Nitrox
Thickness: 10kÅ
Die Dimensions:
103.5 x 116.5 x 19  1mils
Worst Case Current Density:
Metallization:
1.9 x 105 A/cm2
Type: Si - Al
Thickness: 11kÅ 2kÅ
Metallization Mask Layout
82C88
S1
CLK
IOB
VCC
S0
S2
DT/R
MCE/
PDEN
ALE
DEN
CEN
AEN
INTA
MRDC
AMWC
11
MWTC
GND
IOWC
AIOWC
IORC
FN2979.3
August 13, 2015
82C88
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
August 13, 2015
FN2979.3
CHANGE
Updated Ordering Information Table on page 1.
Added Revision History and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN2979.3
August 13, 2015
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