DATASHEET

82C89
Data Sheet
September 4, 2015
CMOS Bus Arbiter
Features
The Intersil 82C89 Bus Arbiter is manufactured using a selfaligned silicon gate CMOS process (Scaled SAJI IV). This
circuit, along with the 82C88 bus controller, provides full bus
arbitration and control for multi-processor systems. The 82C89
is typically used in medium to large 80C86 or 80C88 systems
where access to the bus by several processors must be
coordinated. The 82C89 also provides high output current and
capacitive drive to eliminate the need for additional bus
buffering.
• Pin Compatible with Bipolar 8289
Static CMOS circuit design insures low operating power. The
advanced Intersil SAJI CMOS process results in
performance equal to or greater than existing equivalent
products at a significant power savings.
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
CP82C89
CP82C89
(No longer
available or
supported)
0 to +70
20 Ld PDIP
E20.3
CP82C89Z* CP82C89Z
(Note) (No
longer
available or
supported)
0 to +70
20 Ld PDIP
(Pb-free)
E20.3
MD82C89/B
MD82C89/B
FN2980.3
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
• Provides Multi-Master System Bus Control and
Arbitration
• Provides Simple Interface with 82C88/8288 Bus
Controller
• Synchronizes 80C86/8086, 80C88/8088 Processors with
Multi-Master Bus
• Bipolar Drive Capability
• Four Operating Modes for Flexible System Configuration
• Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10A (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz (Max)
• Operating Temperature Ranges
- C82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- M82C89 . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
82C89 (PDIP, CERDIP)
TOP VIEW
-55 to +125 20 Ld CERDIP F20.3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
1
S2
1
20 VCC
IOB
2
19 S1
SYSB/RESB
3
18 S0
RESB
4
17 CLK
BCLK
5
16 LOCK
INIT
6
15 CRQLCK
BREQ
7
14 ANYRQST
BPRO
8
13 AEN
BPRN
9
12 CBRQ
GND 10
11 BUSY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC
Copyright Intersil Americas LLC 1997, 2006, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
82C89
Functional Diagram
ARBITRATION
S2
S1
80C86/
80C88
STATUS
S0
LOCK
CLK
CRQLCK
RESB
ANYRQST
CONTROL/
STRAPPING
OPTIONS
STATUS
MULTIBUS
INTERFACE
IOB
CBRQ
LOCAL
BUS
INTERFACE
AEN
SYSB/
RESB
+5V
MULTIBUS™
COMMAND
SIGNALS
BUSY
DECODER
CONTROL
INIT
BCLK
BREQ
BPRN
BPRO
GND
SYSTEM
SIGNALS
MULTIBUS™ is an Intel Corp. trademark.
Pin Description
PIN
SYMBOL
NUMBER TYPE
DESCRIPTION
VCC
20
VCC: The +5V Power supply pin. A 0.1F capacitor between pins 10 and 20 is recommended for decoupling.
GND
10
GROUND.
S0, S1, S2
1, 18-19
I
STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The 82C89 decodes
these pins to initiate bus request and surrender actions. (See Table 1).
CLK
17
I
CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions are initiated.
LOCK
16
I
LOCK: A processor generated signal which when activated (low) prevents the arbiter from surrendering the multimaster system bus to any other bus arbiter, regardless of its priority.
CRQLCK
15
I
COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the multi-master
system bus to any other bus arbiter requesting the bus through the CBRQ input pin.
RESB
4
I
RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a multi-master
system bus and a Resident Bus. Strapped high, the multi-master system bus is requested or surrendered as a
function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB input is ignored.
ANYRQST
14
I
ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered to a lower
priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter requests the use of the
multi-master system bus, the bus is surrendered as soon as it is possible). When ANYRQST is strapped low, the
bus is surrendered according to Table A in Design Information. If ANYRQST is strapped high and CBRQ is
activated, the bus is surrendered at the end of the present bus cycle. Strapping CBRQ low and ANYRQST high
forces the 82C89 arbiter to surrender the multi-master system bus after each transfer cycle. Note that when
surrender occurs BREQ is driven false (high).
IOB
2
I
IO BUS: A strapping option which configures the 82C89 Arbiter to operate in systems having both an IO Bus
(Peripheral Bus) and a multi-master system bus. The arbiter requests and surrenders the use of the multi-master
system bus as a function of the status line, S2. The multi-master system bus is permitted to be surrendered while
the processor is performing IO commands and is requested whenever the processor performs a memory
command. Interrupt cycles are assumed as coming from the peripheral bus and are treated as an IO command.
AEN
13
O
ADDRESS ENABLE: The output of the 82C89 Arbiter to the processor’s address latches, to the 82C88 Bus
Controller and 82C84A or 82C85 Clock Generator. AEN serves to instruct the Bus Controller and address latches
when to three-state their output drivers.
INIT
6
I
INITIALIZE: An active low multi-master system bus input signal used to reset all the bus arbiters on the multimaster system bus. After initialization, no arbiters have the use of the multi-master system bus.
2
FN2980.3
September 4, 2015
82C89
Pin Description
PIN
SYMBOL
(Continued)
NUMBER TYPE
DESCRIPTION
SYSB/RESB
3
I
SYSTEM BUS/RESIDENT BUS: An input signal when the arbiter is configured in the System/Resident Mode
(RESB is strapped high) which determines when the multi-master system bus is requested and multi-master
system bus surrendering is permitted. The signal is intended to originate from a form of address-mapping
circuitry, such as a decoder or PROM attached to the resident address bus. Signal transitions and glitches are
permitted on this pin from 1 of T4 to 1 of T2 of the processor cycle. During the period from 1 of T2 to 1 of T4,
only clean transitions are permitted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it,
and the multi-master system bus may be requested or surrendered, depending upon the state of the glitch. The
arbiter requests the multi-master system bus in the System/Resident Mode when the state of the SYSB/RESB
pin is high and permits the bus to be surrendered when this pin is low.
CBRQ
12
I/O
COMMON BUS REQUEST: An input signal which instructs the arbiter if there are any other arbiters of lower
priority requesting the use of the multi-master system bus.
The CBRQ pins (open-drain output) of all the 82C89 Bus Arbiters which surrender to the multi-master system
bus upon request are connected together.
The Bus Arbiter running the current transfer cycle will not itself pull the CBRQ line low. Any other arbiter
connected to the CDRQ line can request the multi-master system bus. The arbiter presently running the current
transfer cycle drops its BREQ signal and surrenders the bus whenever the proper surrender conditions exist.
Strapping CBRQ low and ANYRQST high allows the multi-master system bus to be surrendered after each
transfer cycle. See the pin definition of ANYRQST.
BCLK
5
I
BUS CLOCK: The multi-master system bus clock to which all multi-master system bus interface signals are
synchronized.
BREQ
7
O
BUS REQUEST: An active low output signal in the Parallel Priority Resolving Scheme which the arbiter activates
to request the use of the multi-master system bus.
BPRN
9
I
BUS PRIORITY IN: The active low signal returned to the arbiter to instruct it that it may acquire the multi-master
system bus on the next falling edge of BCLK. BPRN active indicates to the arbiter that it is the highest priority
requesting arbiter presently on the bus. The loss of BPRN instructs the arbiter that it has lost priority to a higher
priority arbiter.
BPRO
8
O
BUS PRIORITY OUT: An active low output signal used in the serial priority resolving scheme where BPRO is
daisy-chained to BPRN of the next lower priority arbiter.
BUSY
11
I/O
BUSY: An active low open-drain multi-master system bus interface signal used to instruct all the arbiters on the
bus when the multi-master system bus is available. When the multi-master system bus is available the highest
requesting arbiter (determined by BPRN) seizes the bus and pulls BUSY low to keep other arbiters off of the bus.
When the arbiter is done with the bus, it releases the BUSY signal, permitting it to go high and thereby allowing
another arbiter to acquire the multi-master system bus.
Functional Description
The 82C89 Bus Arbiter operates in conjunction with the
82C88 Bus Controller to interface 80C86, 80C88 processors
to a multi-master system bus (both the 80C86 and 80C88 are
configured in their max mode). The processor is unaware of
the arbiter’s existence and issues commands as though it
has exclusive use of the system bus. If the processor does
not have the use of the multi-master system bus, the arbiter
prevents the Bus Controller (82C88), the data transceivers
and the address latches from accessing the system bus (e.g.
all bus driver outputs are forced into the high impedance
state). Since the command sequence was not issued by the
82C88, the system bus will appear as “Not Ready” and the
processor will enter wait states. The processor will remain in
Wait until the Bus Arbiter acquires the use of the multi-master
system bus whereupon the arbiter will allow the bus controller,
the data transceivers, and the address latches to access the
system. Typically, once the command has been issued and a
data transfer has taken place, a transfer acknowledge (XACK)
is returned to the processor to indicate “READY” from the
3
accessed slave device. The processor then completes its
transfer cycle. Thus the arbiter serves to multiplex a processor
(or bus master) onto a multi-master system bus and avoid
contention problems between bus masters.
Arbitration Between Bus Masters
In general, higher priority masters obtain the bus when a
lower priority master completes its present transfer cycle.
Lower priority bus masters obtain the bus when a higher
priority master is not accessing the system bus. A strapping
option (ANYRQST) is provided to allow the arbiter to
surrender the bus to a lower priority master as though it were
a master of higher priority. If there are no other bus masters
requesting the bus, the arbiter maintains the bus so long as
its processor has not entered the HALT State. The arbiter will
not voluntarily surrender the system bus and has to be forced
off by another master’s bus request, the HALT State being the
only exception. Additional strapping options permit other
modes of operation wherein the multi-master system bus is
surrendered or requested under different sets of conditions.
FN2980.3
September 4, 2015
82C89
Priority Resolving Techniques
Since there can be many bus masters on a multi-master
system bus, some means of resolving priority between bus
masters simultaneously requesting the bus must be
provided. The 82C89 Bus Arbiter provides several resolving
techniques. All the techniques are based on a priority
concept that at a given time one bus master will have priority
above all the rest. There are provisions for using parallel
priority resolving techniques, serial priority resolving
techniques, and rotating priority techniques.
BCLK
BREQ
BPRN
1
2
4
3
BUSY
FIGURE 2. HIGHER PRIORITY ARBITER OBTAINING THE
BUS FROM A LOWER PRIORITY ARBITER
NOTES:
Parallel Priority Resolving
1. Higher priority bus arbiter releases BUSY.
The parallel priority resolving technique uses a separate bus
request line BREQ for each arbiter on the multi-master
system bus, see Figure 1. Each BREQ line enters into a
priority encoder which generates the binary address of the
highest priority BREQ line which is active. The binary address
is decoded by a decoder to select the corresponding BPRN
(Bus Priority In) line to be returned to the highest priority
requesting arbiter. The arbiter receiving priority (BPRN true)
then allows its associated bus master onto the multi-master
system bus as soon as it becomes available (i.e., the bus is
no longer busy). When one bus arbiter gains priority over
another arbiter it cannot immediately seize the bus, it must
wait until the present bus transaction is complete. Upon
completing its transaction the present bus occupant
recognizes that it no longer has priority and surrenders the
bus by releasing BUSY. BUSY is an active low “OR” tied
signal line which goes to every bus arbiter on the system
bus. When BUSY goes inactive (high), the arbiter which
presently has bus priority (BPRN true) then seizes the bus
and pulls BUSY low to keep other arbiters off of the bus. See
waveform timing diagram, Figure 2. Note that all multimaster
system bus transactions are synchronized to the bus clock
(BCLK). This allows the parallel priority resolving circuitry or
any other priority resolving scheme employed to settle.
2. Higher priority bus arbiter then acquires the bus and pulls BUSY
down.
Serial Priority Resolving
The serial priority resolving technique eliminates the need
for the priority encoder-decoder arrangement by
daisychaining the bus arbiters together, connecting the
higher priority bus arbiter’s BPRO (Bus Priority Out) output
to the BPRN of the next lower priority. See Figure 3.
BPRN
BUS
ARBITER
1
BPRN
BUS
ARBITER
3
74HC148
PRIORITY
ENCODER
• •
• •
BREQ
BPRO
BPRN
BUS
ARBITER
4
BPRO
BPRN
BREQ
BUS
BPRN
ARBITER
2
BUS
ARBITER
3
BPRO
BPRN
BUS
ARBITER BPRO
2
BREQ


CBRQ
74HC138
3 TO 8
ENCODER


BUSY


FIGURE 3. SERIAL PRIORITY RESOLVING
••
••
BUS
ARBITER
1
3. Lower priority bus arbiter releases BUSY.
4. Higher priority bus arbiter then acquires the bus and pulls BUSY
down.
BPRN
NOTE: The number of arbiters that may be daisy-chained together
in the serial priority resolving scheme is a function of BCLK and the
propagation delay from arbiter to arbiter. Normally, at 10MHz only 3
arbiters may be daisychained.
BREQ
•
•
•
•
CBRQ
BUSY
BUS
ARBITER BPRN
4
Rotating Priority Resolving
FIGURE 1. PARALLEL PRIORITY RESOLVING TECHNIQUE
4
The rotating priority resolving technique is similar to that of
the parallel priority resolving technique except that priority is
dynamically re-assigned. The priority encoder is replaced by
a more complex circuit which rotates priority between
requesting arbiters thus allowing each arbiter an equal
chance to use the multi-master system bus, over time.
FN2980.3
September 4, 2015
82C89
Which Priority Resolving Technique To Use
There are advantages and disadvantages for each of the
techniques described above. The rotating priority resolving
technique requires substantial external logic to implement
while the serial technique uses no external logic but can
accommodate only a limited number of bus arbiters before the
daisy-chain propagation delay exceeds the multimaster’s
system bus clock (BCLK). The parallel priority resolving
technique is in general a good compromise between the other
two techniques. It allows for many arbiters to be present on
the bus while not requiring too much logic to implement.
82C89 Modes Of Operation
There are two types of processors for which the 82C89 will
provide support: An Input/Output processor (i.e. an NMOS
8089 IOP) and the 80C86, 80C88. Consequently, there are
two basic operating modes in the 82C89 bus arbiter. One,
the IOB (I/O Peripheral Bus) mode, permits the processor
access to both an I/O Peripheral Bus and a multi-master
system bus. The second, the RESB (Resident Bus mode),
permits the processor to communicate over both a Resident
Bus and a multi-master system bus. An I/O Peripheral Bus is
a bus where all devices on that bus, including memory, are
treated as I/O devices and are addressed by I/O commands.
All memory commands are directed to another bus, the
multi-master system bus. A Resident Bus can issue both
memory and I/O commands, but it is a distinct and separate
bus from the multi-master system bus. The distinction is that
the Resident Bus has only one master, providing full
availability and being dedicated to that one master.
5
The IOB strapping option configures the 82C89 Bus Arbiter
into the IOB mode and the strapping option RESB
configures it into the RESB mode. It might be noted at this
point that if both strapping options are strapped false, the
arbiter interfaces the processor to a multi-master system bus
only (see Figure 4). With both options strapped true, the
arbiter interfaces the processor to a multi-master system
bus, a Resident Bus, and an I/O Bus.
In the IOB mode, the processor communicates and controls
a host of peripherals over the Peripheral Bus. When the I/O
Processor needs to communicate with system memory, it
does so over the system memory bus. Figure 5 shows a
possible I/O Processor system configuration.
The 80C86 and 80C88 processors can communicate with a
Resident Bus and a multi-master system bus. Two bus
controllers and only one Bus Arbiter would be needed in
such a configuration as shown in Figure 6. In such a system
configuration the processor would have access to memory
and peripherals of both busses. Memory mapping
techniques are applied to select which bus is to be
accessed. The SYSB/RESB input on the arbiter serves to
instruct the arbiter as to whether or not the system bus is to
be accessed. The signal connected to SYSB/RESB also
enables or disables commands from one of the bus
controllers. A summary of the modes that the 82C89 has,
along with its response to its status lines inputs, is shown in
Table 1.
FN2980.3
September 4, 2015
82C89
X1
X2
RDY2
82C84A/85
CLOCK
GENERATOR
AEN2
READY RDY1
AEN1
CLK
VCC
XACK MULTI-MASTER
SYSTEM BUS
82C89
BUS
ARBITER
MULTI-MASTER
CONTROL BUS
ANYRQST
READY
CLK
CLK
VCC
IOB
S0-S2 RESB
AEN
S0
AD0-AD15 S1
A16-A19 S2
STATUS (S0, S1, S2)
AEN
82C88
BUS
CONTROLLER
CLK
IOB
ALE
DEN
DT/R
MULTI-MASTER SYSTEM
COMMAND BUS
OE
STB
ADDRESS
LATCH
82C82/
82C83H
(2 OR 3)
PROCESSOR
LOCAL BUS
MULTI-MASTER SYSTEM
ADDRESS BUS
MULTI-MASTER SYSTEM BUS
80C86
CPU
XCVR
DISABLE
OE
DT/R
TRANSCEIVER
82C86H/
82C87H
(2)
MULTI-MASTER SYSTEM
DATA BUS
FIGURE 4. TYPICAL MEDIUM COMPLEXITY CPU SYSTEM
6
FN2980.3
September 4, 2015
82C89
AEN1
82C84A/85
CLOCK
RDY1
RDY2
XACK(I/O BUS)
XACK
MULTI-MASTER
SYSTEM BUS
82C89
BUS
ARBITER
READY
CLK
AEN2
CLK
READY
S0-S2
CLK
8089
IOP
I/O BUS
PROCESSOR
LOCAL BUS
OE
STB
ADDRESS
LATCH
82C82/
82C83H
(2 OR 3)
OE
I/O
DATA
BUS
STATUS (S0, S1, S2)
ANYRQST
AEN
AEN
82C88
BUS
CONTROLLER
I/O
COMMAND
BUS
I/O
ADDRESS
BUS
VCC
IOB
RESB
T
TRANSCEIVER
82C86H/
82C87H
(2)
CLK
ALE
IOB
PDEN DEN DT/R
OE
STB
ADDRESS
LATCH
82C82/
82C83H
(2 OR 3)
OE
MULTI-MASTER
SYSTEM
COMMAND BUS
VCC
XCVR
DISABLE
MULTI-MASTER
SYSTEM
ADDRESS BUS
MULTI-MASTER SYSTEM BUS
AD0-AD15 S0
A16-A19 S2
MULTI-MASTER
CONTROL BUS
T
TRANSCEIVER
82C86H/
82C87H
(2)
MULTI-MASTER
SYSTEM
DATA BUS
FIGURE 5. TYPICAL MEDIUM COMPLEXITY IOB SYSTEM
7
FN2980.3
September 4, 2015
82C89
AEN2
AEN1
82C84A/85
CLOCK
XACK
RESIDENT BUS
XACK MULTI MASTER
SYSTEM BUS
RDY2 RDY1
READY CLK
READY CLK
STATUS
S0-S2
80C86
CPU
82C89
S0
BUS
S1 ARBITER
S2
MULTI MASTER
SYSTEM BUS CONTROL
RESB
IOB
ANYRQST
SYSB/
RESB
AEN
CLK
AD0-AD15
A16-A19
CEN
AEN
RESIDENT BUS
AEN
S0-S2
82C88
CLK
RESIDENT
COMMAND BUS
PROM
OR
DECODER
OR
CMOS HPL
(NOTE)
DT/R
ALE
DEN
DEN
ALE
STB
OE
OE
STB
OE
T
TRANSCEIVER
82C86H/
82C87H
(2)
RESIDENT
DATA BUS
MULTI MASTER
SYSTEM COMMAND BUS
DT/R
ADDR
LATCH
82C82/
82C83H
(2 OR 3)
RESIDENT
ADDRESS BUS
S0-S2
82C88
CLK
IOB
ADDR
LATCH
82C82/
82C83H
(2 OR 3)
T
MULTI MASTER SYSTEM BUS
CEN
VCC
MULTI MASTER
SYSTEM ADDRESS BUS
OE
TRANSCEIVER
82C86H/
82C87H
(2)
MULTI MASTER
SYSTEM DATA BUS
FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYSTEM - RESIDENT BUS CONFIGURATION
NOTE: By adding another 82C89 arbiter and connecting its AEN to the 82C88 whose AEN is presently grounded, the processor could have access
to two multi-master buses.
8
FN2980.3
September 4, 2015
82C89
TABLE 1. SUMMARY OF 82C89 MODES, REQUESTING AND RELINQUISHING THE MULTI-MASTER SYSTEM BUS
SINGLE LINES FROM
80C86 OR 80C88 OR 8088
RESB MODE ONLY
IOB = HIGH, RESB = HIGH
IOB MODE RESB MODE
IOB = LOW, RESB = HIGH
S2
S1
S0
IOB MODE
ONLY
IOB = LOW
RESB = LOW
I/O
Commands
0
0
0
0
0
1
0
1
0
X
X
X
†
†
†
X
X
X
X
X
X
X
X
X
†
†
†
Halt
0
1
1
X
X
X
X
X
X
Memory
Commands
1
1
1
0
0
1
0
1
0†
†
†
†
†
†
†
X
X
X
†
†
†
X
X
X
†
†
†
Idle
1
1
1
X
X
X
X
X
X
SYSB/RESB =
HIGH
SYSB/RESB =
LOW
SYSB/RESB =
HIGH
SYSB/RESB =
LOW
SINGLE BUS
MODE
IOB = HIGH
RESB = LOW
NOTES:
1. X = Multi-Master System Bus is allowed to be Surrendered.
2. † = Multi-Master System Bus is Requested.
PIN
STRAPPING
MODE
MULTI-MASTER SYSTEM BUS
REQUESTED**
SURRENDERED*
Single Bus Multi-Master Mode
IOB = High RESB = Whenever the processor’s status lines go
Low
active
HLT + TI • CBRQ + HPBRQ ‡
RESB Mode Only
IOB = High RESB = SYSB/RESB + High •
High
ACTIVE STATUS
(SYSB/RESB = Low + TI) •
CBRQ + HLT + HPBRQ
IOB Mode Only
IOB = Low
RESB = Low
Memory Commands
(I/O Status + TI) • CBRQ + HLT +
HPBRQ
IOB Mode RESB Mode
IOB = Low
RESB = High
(Memory Command) •
(SYSB/RESB = High)
(I/O Status Commands) +
SYSB/RESB = Low) • CBRQ +
HPBRQ + HLT
NOTES:
* LOCK prevents surrender of Bus to any other arbiter, CRQLCK prevents surrender of Bus to any lower priority arbiter.
** Except for HALT and Passive or IDLE Status.
‡ HPBRQ, Higher priority Bus request or BPRN = 1.
1. IOB Active Low.
2. RESB Active High.
3. + is read as “OR” and • as “AND”
4. TI = Processor Idle Status S2, S1, S0 = 111
5. HLT = Processor Halt Status S2, S1, S0 = 011
9
FN2980.3
September 4, 2015
82C89
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Note 1)
JA (°C/W)
JC (°C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
80
20
PDIP Package* . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
M82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Electrical Specifications
VCC = 5.0V ± 10%;
TA = 0°C to +70°C (C82C89);
TA = -55°C to +125°C (M82C89)
SYMBOL
PARAMETER
TEST CONDITIONS
VIH
Logical One Input Voltage
C82C89,
M82C89, Note 1
VIL
Logical Zero Input Voltage
Note 1
MIN
MAX
UNITS
2.0
2.2
-
V
V
-
0.8
V
VIHC
CLK Logical One Input Voltage
0.7 VCC
-
V
VILC
CLK Logical Zero Input Voltage
-
0.2 VCC
V
VOL
Output Low Voltage
BUSY, CBRQ
IOL = 20mA
-
0.45
V
AEN
IOL = 16mA
-
0.45
V
BPRO, BREQ
IOL = 8mA
-
0.45
V
Open-Drain
VOH1
Output High Voltage
BUSY, CBRQ
VOH2
Output High Voltage
IOH = -2.5mA
3.0
-
V
All Other Outputs
IOH = -100A
VCC -0.4
-
V
II
Input Leakage Current
VIN = GND or VCC, DIP Pins 1-6, 9, 14-19
-1.0
1.0
A
IO
I/O Leakage
VO = GND or VCC, DIP Pins 11-12
-10.0
10.0
A
ICCSB
Standby Power Supply
VCC = 5.5V, VIN = VCC or GND, Outputs Open
-
10
A
ICCOP
Operating Power Supply Current
VCC = 5.5V, Outputs Open, Note 2
-
1
mA/MHz
NOTES:
1. Does not apply to IOB, RESB, or ANYRQST. These are strap options and should be held to VCC or GND.
2. Maximum current defined by CLK or BCLK, whichever has the highest operating frequency
Capacitance TA = +25°C
SYMBOL
CIN
COUT
CIO
PARAMETER
Input Capacitance
Output Capacitance
I/O Capacitance
10
TEST CONDITIONS
FREQ = 1MHz, all measurements are
referenced to device GND
TYPICAL
UNITS
10
pF
10
pF
15
pF
FN2980.3
September 4, 2015
82C89
AC Electrical Specifications VCC = 5.0V 10%; GND = 0V:
TA = 0°C to +70°C (C82C89);
TA = -55°C to +125°C (M82C89)
SYMBOL
PARAMETER
MIN
MAX
UNIT
TEST CONDITIONS
(1)
TCLCL
CLK Cycle Period
125
-
ns
Note 3
(2)
TCLCH
CLK Low Time
55
-
ns
Note 3
(3)
TCHCL
CLK High Time
35
-
ns
Note 3
(4)
TSVCH
Status Active Setup
65
TCLCL-10
ns
Note 3
(5)
TSHCL
Status Inactive Setup
50
TCLCL-10
ns
Note 3
(6)
THVCH
Status Inactive Hold
10
-
ns
Note 3
(7)
THVCL
Status Active Hold
10
-
ns
Note 3
(8)
TBYSBL
BUSY Setup to BCLK
20
-
ns
Note 3
(9)
TCBSBL
CBRQ Setup to BCLK
20
-
ns
Note 3
(10)
TBLBL
BCLK Cycle Time
100
-
ns
Note 3
(11)
TBHCL
BCLK High Time
30
0.65
(TBLBL)
ns
Note 3
(12)
TCLLL1
LOCK Inactive Hold
10
-
ns
Note 3
(13)
TCLLL2
LOCK Active Setup
40
-
ns
Note 3
(14)
TPNBL
BPRN to BCLK Setup Time
20
-
ns
Note 3
(15)
TCLSR1
SYSB/RESB Setup
0
-
ns
Note 3
(16)
TCLSR2
SYSB/RESB Hold
30
-
ns
Note 3
(17)
TIVIH
Initialization Pulse Width
675
-
ns
Note 3
(18)
TBLBRL
BCLK to BREQ Delay
-
35
ns
Note 3
(19)
TBLPOH
BCLK to BPRO
-
35
ns
Note 1 and 3
(20)
TPNPO
BPRN to BPRO Delay
-
22
ns
Note 1 and 3
(21)
TBLBYL
BCLK to BUSY Low
-
60
ns
Note 3
(22)
TBLBYH
BCLK to BUSY Float
-
35
ns
Note 2 and 3
(23)
TCLAEH
CLK to AEN High
-
65
ns
Note 3
(24)
TBLAEL
BCLK to AEN Low
-
40
ns
Note 3
(25)
TBLCBL
BCLK to CBRQ Low
-
60
ns
Note 3
(26)
TBLCBH
BCLK to CBRQ Float
-
40
ns
Note 2 and 3
(27)
TOLOH
Output Rise Time
-
20
ns
From 0.8V to 2.0V, Note 4
(28)
TOHOL
Output Fall Time
-
12
ns
From 2.0V to 0.8V, Note 4
(29)
TILIH
Input Rise Time
-
20
ns
From 0.8V to 2.0V
(30)
TIHIL
Input Fall Time
-
20
ns
From 2.0V to 0.8V
NOTES:
1. BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated through BPRON.
2. Measured at 0.5V above GND.
3. All AC parameters tested as per AC test load circuits. Input rise and fall times are driven at 1ns/V.
4. Except BUSY and CBRQ.
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82C89
AC Test Load Circuits
BUSY, CBRQ LOAD CIRCUIT
AEN LOAD CIRCUIT
2.5V
2.9V
102
OUTPUT FROM
DEVICE
UNDER TEST
2.9V
249.6
157.2
OUTPUT FROM
DEVICE
UNDER TEST
TEST
POINT
100pF
(NOTE)
NOTE:
BPRO, BREQ LOAD CIRCUIT
OUTPUT FROM
DEVICE
UNDER TEST
TEST
POINT
100pF
(NOTE)
TEST
POINT
100pF
(NOTE)
Includes Stray and Jig Capacitance
AC Testing Input, Output Waveform
INPUT
OUTPUT
VIH +0.4V
VOH
1.5V
1.5V
AC Testing: Inputs are driven at VIH +0.4V for a logic “1” and VIL
-0.4V for a logic “0”. The clock is driven at VCC -0.4V and 0.4V.
Timing measurements are made at 1.5V for both a logic “1” and “0”.
VOL
VIL -0.4V
Burn-In Circuits
MD82C89 CERDIP
VCC
R2
F7
F13
F14
F12
F0
VCC
VCC/2
R2
R2
R2
R2
R1
R1
R1
R2
F8
C1
1
20
2
19
3
18
4
17
5
6
7
15
14
8
13
9
12
10
12
16
R2
R2
R2
F6
F5
F0
R2
R2
R2
F9
F10
F11
R1
R1
VCC/2
R1
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FN2980.3
September 4, 2015
82C89
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
92.9 x 95.7 x 19 1 mils
Type: Nitrox
Thickness: 10kÅ 2kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: Si - Al
Thickness: 11kÅ ±2kÅ
1.8 x 105 A/cm2
Metallization Mask Layout
S0
S1
VCC
S2
IOB
SYSB/RESB
82C89
RESB
CLK
BCLK
ANYRQST
LOCK
INIT
CRQLCK
ANYRQST
13
AEN
CBRQ
BUSY
GND
BPRN
BPRO
BREQ
FN2980.3
September 4, 2015
82C89
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
September 4, 2015
FN2980.3
CHANGE
- Ordering Information Table on page 1.
- Added Revision History and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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14
FN2980.3
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