DATASHEET

HA-5320
Data Sheet
1 Microsecond Precision Sample and
Hold Amplifier
The HA-5320 was designed for use in precision, high speed
data acquisition systems.
The circuit consists of an input transconductance amplifier
capable of providing large amounts of charging current, a
low leakage analog switch, and an output integrating
amplifier. The analog switch sees virtual ground as its load;
therefore, charge injection on the hold capacitor is constant
over the entire input/output voltage range. The pedestal
voltage resulting from this charge injection can be adjusted
to zero by use of the offset adjust inputs. The device
includes a hold capacitor. However, if improved droop rate is
required at the expense of acquisition time, additional hold
capacitance may be added externally.
This monolithic device is manufactured using the Intersil
Dielectric Isolation Process, minimizing stray capacitance
and eliminating SCRs. This allows higher speed and latchfree operation. For further information, please see
Application Note AN538.
August 11, 2015
FN2857.10
Features
• Gain, DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 x 106 V/V
• Acquisition Time . . . . . . . . . . . . . . . . . . . . . .1.0µs (0.01%)
• Droop Rate. . . . . . . . . . . . . . . . . . . . . 0.08µV/µs (+25°C)
17µV/µs (Full Temperature)
• Aperture Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
• Hold Step Error (See Glossary) . . . . . . . . . . . . . . . . . 5mV
• Internal Hold Capacitor
• Fully Differential Input
• TTL Compatible
• Pb-Free Available (RoHS Compliant)
Applications
• Precision Data Acquisition Systems
• Digital to Analog Converter Deglitcher
• Auto Zero Circuits
• Peak Detector
Pinouts
Ordering Information
HA-5320
(CERDIP)
TOP VIEW
PART
NUMBER
(Note 2)
-INPUT 1
14 S/H CONTROL
+INPUT 2
13 SUPPLY GND
HA1-5320-2
PART
MARKING
12 NC
HA9P5320-5Z HA9P5320-5Z
(Note 1)
OFFSET ADJUST 4
11 CEXT
NOTES:
10 NC
SIG. GND 6
9 V+
OUTPUT 7
INTEGRATOR
8 BANDWIDTH
HA-5320
(SOIC)
TOP VIEW
-INPUT 1
16 S/H CONTROL
+INPUT 2
15 SUPPLY GND
OFFSET ADJUST 3
14 NC
OFFSET ADJUST 4
13 CEXT
V- 5
PACKAGE
PKG.
DWG. #
HA1-5320-2 -55 to +125 14 Ld CERDIP F14.3
OFFSET ADJUST 3
V- 5
TEMP.
RANGE
(°C)
0 to +75
16 Ld SOIC
(Pb-free)
M16.3
1. Add X96 for Tape and Reel.
2. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
12 NC
11 V+
INTEGRATOR
10 BANDWIDTH
SIG. GND 6
OUTPUT 7
9 NC
NC 8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003, 2005, 2012, 2013, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HA-5320
Functional Diagram
OFFSET
ADJUST
3
V+
9
4
100pF
HA-5320
-INPUT 1
-
+INPUT 2
7
+
OUTPUT
S/H
CONTROL 14
13
5
SUPPLY
GND
V-
6
8
INTEGRATOR
BANDWIDTH
SIG.
GND
11 CEXT
2
FN2857.10
August 11, 2015
HA-5320
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V, -15V
Output Current, Continuous (Note 1) . . . . . . . . . . . . . . . . . . . 20mA
Thermal Resistance (Typical, Note 5)
JA (°C/W)
JC (°C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
70
18
SOIC Package . . . . . . . . . . . . . . . . . . .
90
N/A
Maximum Junction Temperature (Ceramic Package) . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Pb-Free Reflow Profilesee link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
HA-5320-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C
HA-5320-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Supply Voltage Range (Typical, Note 2) . . . . . . . . . 13.5V to 20V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. Internal Power Dissipation may limit Output Current below 20mA.
4. Specification based on a one time characterization. This parameter is not guaranteed.
5. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VSUPPLY = 15.0V; CH = Internal; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold),
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified
TEST
CONDITIONS
HA-5320-2
HA-5320-5
TEMP.
(°C)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Voltage Range
Full
10
-
-
10
-
-
V
Input Resistance
25
1
5
-
1
5
-
M
Input Capacitance
25
-
-
5
-
-
5
pF
Offset Voltage
25
-
0.2
-
-
0.5
-
mV
Full
-
-
2.0
-
-
1.5
mV
25
-
70
200
-
100
300
nA
Full
-
-
200
-
-
300
nA
25
-
30
100
-
30
300
nA
Full
-
-
100
-
-
300
nA
Full
10
-
-
10
-
-
V
PARAMETER
INPUT CHARACTERISTICS
Bias Current
Offset Current
Common Mode Range
VCM = 5V
CMRR
Offset Voltage Temperature Coefficient
25
80
90
-
72
90
-
dB
Full
-
5
15
-
5
20
µV/°C
TRANSFER CHARACTERISTICS
Gain
DC, (Note 14)
25
106
2 x 106
-
3 x 105
2 x 106
-
V/V
Gain Bandwidth Product
(AV = +1, Note 7)
CH = 100pF
25
-
2.0
-
-
2.0
-
MHz
CH = 1000pF
25
-
0.18
-
-
0.18
-
MHz
Output Voltage
Full
10
-
-
10
-
-
V
Output Current
25
10
-
-
10
-
-
mA
OUTPUT CHARACTERISTICS
Full Power Bandwidth
Note 6
25
-
600
-
-
600
-
kHz
Output Resistance
Hold Mode
25
-
1.0
-
-
1.0
-

Total Output Noise (DC to 10MHz)
Sample
25
-
125
200
-
125
200
µVRMS
Hold
25
-
125
200
-
125
200
µVRMS
3
FN2857.10
August 11, 2015
HA-5320
Electrical Specifications
VSUPPLY = 15.0V; CH = Internal; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold),
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued)
TEST
CONDITIONS
PARAMETER
HA-5320-2
HA-5320-5
TEMP.
(°C)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TRANSIENT RESPONSE
Rise Time
Note 7
25
-
100
-
-
100
-
ns
Overshoot
Note 7
25
-
15
-
-
15
-
%
Slew Rate
Note 8
25
-
45
-
-
45
-
V/µs
VIH
Full
2.0
-
-
2.0
-
-
V
VIL
Full
-
-
0.8
-
-
0.8
V
VIL = 0V
25
-
-
4
-
-
4
µA
Full
-
-
10
-
-
10
µA
Full
-
-
0.1
-
-
0.1
µA
To 0.1%
25
-
0.8
1.2
-
0.8
1.2
µs
To 0.01%
25
-
1.0
1.5
-
1.0
1.5
µs
Aperture Time (Note 10)
25
-
25
-
-
25
-
ns
Effective Aperture Delay Time
25
-50
-25
0
-50
-25
0
ns
Aperture Uncertainty
25
-
0.3
-
-
0.3
-
ns
Droop Rate
25
-
0.08
0.5
-
0.08
0.5
µV/µs
Full
-
17
100
-
1.2
100
µV/µs
25
-
8
50
-
8
50
pA
Full
-
1.7
10
-
0.12
10
nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage
Input Current
VIH = +5V
SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time (Note 9)
Drift Current
Note 11
Charge Transfer
Note 11
25
-
0.5
1.1
-
0.5
1.1
pC
Hold Step Error
Note 11
25
-
5
11
-
5
11
mV
Hold Mode Settling Time
To 0.01%
Full
-
165
350
-
165
350
ns
Hold Mode Feedthrough
10VP-P, 100kHz
Full
-
2
-
-
2
-
mV
Positive Supply Current
Note 12
25
-
11
13
-
11
13
mA
Negative Supply Current
Note 12
25
-
-11
-13
-
-11
-13
mA
Supply Voltage Range
Note 4
13.5

20
13.5
-
20
V
Power Supply Rejection
V+, Note 13
Full
80
-
-
80
-
-
dB
V-, Note 13
Full
65
-
-
65
-
-
dB
POWER SUPPLY CHARACTERISTICS
NOTES:
6. VO = 20VP-P; RL = 2k; CL = 50pF; unattenuated output.
7. VO = 200mVP-P; RL = 2k; CL = 50pF.
8. VO = 20V Step; RL = 2k; CL = 50pF.
9. VO = 10V Step; RL = 2k; CL = 50pF.
10. Derived from computer simulation only; not tested.
11. VIN = 0V, VIH = +3.5V, tR < 20ns (VIL to VIH).
12. Specified for a zero differential input voltage between +IN and -IN. Supply current will increase with differential input (as may occur in the Hold
mode) to approximately 46mA at 20V.
13. Based on a 1V delta in each supply, i.e. 15V 0.5VDC.
14. RL = 1k, CL = 30pF.
4
FN2857.10
August 11, 2015
HA-5320
Test Circuits and Waveforms
1
2
S/H
CONTROL
INPUT
14
-INPUT
OUTPUT
7
8
+INPUT
11
S/H CONTROL
VO
NC
NC
HA-5320
(CH = 100pF)
FIGURE 1. CHARGE TRANSFER AND DRIFT CURRENT
HOLD (+3.5V)
SAMPLE (0V)
S/H CONTROL
VO
VO
VO
t
VP
NOTES:
NOTES:
17. Observe the voltage “droop”, VO/t.
15. Observe the “hold step” voltage VP.
18. Measure the slope of the output during hold, VO/t, and
compute drift current: ID = CH VO/t.
16. Compute charge transfer: Q = VPCH.
FIGURE 2. CHARGE TRANSFER TEST
FIGURE 3. DRIFT CURRENT TEST
V+
V IN
10VP-P
100kHz
SINE WAVE
HOLD (+3.5V)
SAMPLE (0V)
S/H CONTROL
9
1
-IN
2
+IN
14
AIN
S/H CONTROL
INPUT
VHA-5320
ANALOG
MUX OR
SWITCH
OUT
S/H CONTROL
SUPPLY
CEXT
GND
13
TO
SUPPLY
COMMON
NOTE:
5
11
NC
REF
COM
6
TO
SIGNAL
GND
7
VOUT
INT.
COMP.
Feedthrough in
V OUT
dB = 20 log -------------V IN
where:
VOUT = VP-P, Hold Mode, VIN = VP-P.
8
NC
FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION
Application Information
Hold Capacitor
The HA-5320 has the uncommitted differential inputs of an
op amp, allowing the Sample and Hold function to be
combined with many conventional op amp circuits. See the
Intersil Application Note AN517 for a collection of circuit
ideas.
The HA-5320 includes a 100pF MOS hold capacitor,
sufficient for most high speed applications (the Electrical
Specifications section is based on this internal capacitor).
Layout
A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01F to 0.1F,
ceramic) should be provided from each power supply
terminal to the Supply Ground terminal on pin 13.
The ideal ground connections are pin 6 (SIG. Ground)
directly to the system Signal Ground, and pin 13 (Supply
Ground) directly to the system Supply Common.
5
Additional capacitance may be added between pins 7 and
11. This external hold capacitance will reduce droop rate at
the expense of acquisition time, and provide other trade-offs
as shown in the Performance Curves.
If an external hold capacitor CEXT is used, then a noise
bandwidth capacitor of value 0.1CEXT should be connected
from pin 8 to ground. Exact value and type are not critical.
The hold capacitor CEXT should have high insulation
resistance and low dielectric absorption, to minimize droop
errors. Polystyrene dielectric is a good choice for operating
temperatures up to +85°C. Teflon® and glass dielectrics
offer good performance to +125°C and above.
FN2857.10
August 11, 2015
HA-5320
The hold capacitor terminal (pin 11) remains at virtual ground
potential. Any PC connection to this terminal should be kept
short and “guarded” by the ground plane, since nearby
signal lines or power supply voltages will introduce errors
due to drift current.
Aperture Time
Typical Application
Hold Step Error
Figure 5 shows the HA-5320 connected as a unity gain
noninverting amplifier - its most widely used configuration.
As an input device for a fast successive - approximation A/D
converter, it offers very high throughput rate for a monolithic
IC sample/hold amplifier. Also, the HA-5320’s hold step error
is adjustable to zero using the Offset Adjust potentiometer, to
deliver a 12-bit accurate output from the converter.
Hold Step Error is the output error due to Charge Transfer (see
above). It may be calculated from the specified parameter,
Charge Transfer, using the following relationship:
The application may call for an external hold capacitor CEXT as
shown. As mentioned earlier, 0.1CEXT is then recommended at
pin 8 to reduce output noise in the Hold mode.
Effective Aperture Delay Time (EADT)
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is the interval
between the conditions of 10% open and 90% open.
Charge Transfer (pC)
Hold Step (V) = -----------------------------------------------------------Hold Capacitance (pF)
See Performance Curves.
The difference between the digital delay time from the Hold
command to the opening of the S/H switch, and the
propagation time from the analog input to the switch.
The HA-5320 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an A/D conversion are absorbed
at the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to VIN at the instant the
Hold command was received. For negative EADT, the output in
Hold (exclusive of pedestal and droop errors) will correspond to
a value of VIN that occurred before the Hold command.
Aperture Uncertainty
Glossary of Terms
The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay Uncertainty,
Aperture Time Jitter, etc.) sets a limit on the accuracy with
which a waveform can be reconstructed from sample data.
Acquisition Time
The time required following a “sample” command, for the
output to reach its final value within 0.1% or 0.01%. This is
the minimum sample time required to obtain a given accuracy,
and includes switch delay time, slewing time and settling time.
Drift Current
The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
Charge Transfer
The small charge transferred to the holding capacitor from
the inter-electrode capacitance of the switch when the unit is
switched to the HOLD mode. Charge transfer is directly
proportional to sample-to-hold offset pedestal error, where:
Charge Transfer (pC) = CH (pF) x Hold Step Error (V)
OFFSET
ADJUST
15mV
10k
VIN
S/H CONTROL
4
5
9
11
2
CEXT
100pF
+
-
-
13
7
+
14
INPUT
DIGITAL
OUTPUT
CONVERT
HA-5320
H
S
-15V +15V
HI-574A
3
1
V
I D (pA) = C H  pF   -------- (V/s)
t
13
6
5
8
0.1CEXT
SYSTEM POWER
GROUND
SYSTEM SIGNAL
GROUND
9
R/C
ANALOG
COMMON
NOTE: Pin Numbers Refer to
DIP Package Only.
FIGURE 5. TYPICAL HA-5320 CONNECTIONS; NONINVERTING UNITY GAIN MODE
6
FN2857.10
August 11, 2015
HA-5320
Typical Performance Curves
CH = 100pF, INTERNAL
10
ACQUISITION TIME FOR
10V STEP TO +0.01% (µs)
5
1000
0.5
0.1
IDRIFT (pA)
VOLTAGE DROOP DURING
HOLD MODE, (mV/100ms)
1.0
SAMPLE-TO-HOLD OFFSET
(HOLD STEP) ERROR, (mV)
0.05
0.01
100
100
10
1
1000
10k
0
100k
-25
0
CH VALUE (pF)
25
50
75
100
125
TEMPERATURE (°C)
FIGURE 6. TYPICAL SAMPLE AND HOLD PERFORMANCE
AS A FUNCTION OF HOLD CAPACITOR
FIGURE 7. DRIFT CURRENT vs TEMPERATURE
100
0
80
45
PHASE
90
60
(CH = 100pF)
GAIN
GAIN
(CH = 1100pF)
40
135
180
20
0
PHASE (°)
GAIN (dB)
120
10
0
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 8. OPEN LOOP GAIN AND PHASE RESPONSE
CH = 100pF
TA = +25°C
-10
-8
-6
-4
5.0
CH = 100pF
0.5
CH = 1000pF
0.05
CH = 0.01µF
-2
2
4
6
+75°C
HOLD STEP VOLTAGE
HOLD STEP VOLTAGE (mV)
8
DC INPUT (V)
FIGURE 9A. HOLD STEP vs INPUT VOLTAGE
10
+25°C
2
3
4
LOGIC LEVEL HIGH (V)
5
FIGURE 9B. HOLD STEP vs LOGIC (VIH) VOLTAGE
FIGURE 9. TYPICAL SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR
7
FN2857.10
August 11, 2015
HA-5320
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos)
Silox Thickness: 12kÅ 2kÅ
Nitride Thickness: 3.5kÅ 1.5kÅ
92 mils x 152 mils x 19 mils
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ 2kÅ
TRANSISTOR COUNT:
184
SUBSTRATE POTENTIAL:
V-
Metallization Mask Layout
HA-5320
CEXT
(11)
SUPPLY GND
(13)
V+
(9)
S/H CTRL (14)
-INPUT (1)
(8) INT BW
(7) OUTPUT
+INPUT (2)
(6) SIG GND
8
(3)
(4)
(5)
VIO ADJ
VIO ADJ
V-
FN2857.10
August 11, 2015
HA-5320
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
August 11, 2015
FN2857.10
CHANGE
Added Rev History beginning with Rev 10.
Added About Intersil Verbiage.
Updated Ordering Information on page 1
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
9
FN2857.10
August 11, 2015
HA-5320
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
(c)
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
b2
b
ccc M
C A-B S
eA/2
-
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
5
E
0.220
0.310
5.59
7.87
5
c
aaa M C A - B S D S
D S
NOTES
0.014
eA
e
MAX
b

A A
MIN
A
A
L
MILLIMETERS
MAX
M
(b)
D
BASE
PLANE
MIN
b1
SECTION A-A
D S
INCHES
SYMBOL
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
N
14
14
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
10
FN2857.10
August 11, 2015
HA-5320
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
INDEX
AREA
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e

B S
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N

NOTES:
MILLIMETERS
16
0°
16
8°
0°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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11
FN2857.10
August 11, 2015
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